Advanced d Processor Architecture. Computer Systems Laboratory Sungkyunkwan University
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1 Advanced d Processor Architecture Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University
2 Modern Microprocessors More than just GHz CPU Clock Speed SPECint2000 SPECfp2000 Athlon 64 FX GHz Pentium 4 Extreme Edition 3.46GHz Pentium 4 Prescott 3.8GHz Opteron GHz Itanium2 9MB 1.6GHz Pentium M GHz POWER5 1.9GHz SPARC64 V 1.89GHz Athlon GHz Alpha 21264C 1.25GHz
3 Pipelining Sequential execution Inst s Pipelining (RISC) Clock cycles Inst s Clock cycles 3
4 Superpipelining Superpipelining p p Subdivide each pipeline stage Higher clock speed in Athlon, 12+ in Pentium Pro/II/III, 14 in UltraSparc-III, in PowerPC G5, 20+ in Pentium 4 Inst s Clock cycles 4
5 Superscalar Superscalar The execution stage has a bunch of different functional units. Execute multiple instructions in parallel Pentium: 2-way superscalar int wb Inst s fetch float 1 float 2 float 3 wb test branch address mem 1 mem 2 wb Clock cycles decode & dispatch 5
6 Superpipelined Superscalar (1) Superpipelining p p + Superscalar 2-way: MIPS R way: PowerPC G3/G4, Pentium Pro/II/III/M/4, / / / Athlon 4-way: UltraSparc, MIPS R10000, PowerPC G4e Alpha & 21264, Core 2 Duo 5-issue: PowerPC G5 Inst s Clock cycles 6
7 Superpipelined Superscalar (2) Tackling instruction dependencies Branch prediction + speculative execution Mispredict penalty: cycles in Pentium Pro/II/III Instruction scheduling In-order execution + compiler optimization» Rearrange the instructions at compile time.» Compiler can see further down the program than the hardware.» SuperSparc, Spa HyperSparc, UltraSparc, Alpha & Out-of-order execution» Reorder instruction execution sequence in hardware at runtime»register renaming reduces the dependency d further.» MIPS R10000, Alpha 21264, POWER/PowerPC, Pentium Pro, Pentium 4, Core 2 Duo 7
8 Intel Architectures Architecture Brand Name XScale (IXA) IA 32 Intel 64 (IA 32e, EM64T, x86 64) Itanium (IA 64) Microarchitecture Brand Name Processor Brand Name P5 P6 NetBurst Mobile Core Pentium Pentium MMX Pentium Pro Pentium II Pentium III Pentium 4 Pentium D Pentium M Core Duo/Solo Core 2 Quad/Duo/Solo Processor Code Name P5, P54C, P54CS P55C, Tillamook Pentium Pro Klamath, Deschutes Katmai, Coppermine, Tualatin Willamette, Northwood, Prescott, Cedar Mill Smithfield, Presler Banias, Dothan Yonah Conroe, Allendale, Wolfdale Merom, Penryn Kentsfield, Yorkfield 8
9 Pentium Integer Pipeline 2-way superscalar with 5 stages PF Fetch and align instruction u pipe D1 v pipe Decode instruction & generate control word Check for instruction pairability Perform branch prediction D2 D2 Decode control word Compute memory address E E Access data cache or calculate ALU result WB WB Write result 9
10 Intel Pentium Pro In-order front-end Multiple branch prediction Micro-operations Register renaming Out-of-order order execution core 3-way superscalar Multiple execution units Dataflow analysis Speculative execution In-order retirement Precise faulting semantics Execute Fetch Decode reorder out of order core reorder WB in order front end Execute in order retirement 10
11 P6 Microarchitecture 11
12 Intel Pentium 4 Netburst microarchitecture Hyper pipelined for clock rates > 1 GHz Need deeper pipelines pp Diminishing performance returns Requires deeper buffering to cover the longer pipelines Clock skew, jitter, and latch/wire delay matter Reduced percentage of the clock cycle usable by actual logic Heavily depends d on circuit i design techniques, process technology, power and thermal constraints, etc. Increases complexity Harder to balance More challenges to architect around Greater validation effort 12
13 NetBurst Pipeline Hyper pipelined p technology 20 (Willamette) ~ 31 (Prescott) stages Minimum misprediction penalty: 20 cycles Max clock rate: 3.80 GHz (Prescott) P6 misprediction pipeline (introduced at 0.18μ) Fetch Fetch Decode Decode Decode Rename ROB Rd Rdy/Sch Dispatch Exec NetBurst misprediction pipeline (introduced at 1.4GHz 4GHz@ 0.18μ) TC Nxt IP TC Fetch DriveAlloc Rename Que Sch Sch Sch Disp Disp RF RF Ex Flgs Br CkDrive 13
14 Core Microarchitecture 14
15 Multi-core (1) Multi-core Put two or more processor cores onto a single chip Previously called CMP (Chip Multiprocessor) Examples AMD Opteron: dual-core (Apr. 2005) AMD dual-core Athlon 64 X2: dual-core (May 2005) Intel Core Duo, Core 2 Duo, Xeon: dual-core Sun UltraSparc T1: eight-core, 32 threads (Nov. 2005) Intel Core 2 Extreme Quad-core processor (Sep. 2006) Intel Xeon X7460 Six-core processor (Sep. 2008) Microsoft s Xbox 360: triple-core PowerPC microprocessor 15
16 Multi-core (2) 16
17 Multi-core (3) Memory wall CPU 55%/year, Memory 10%/year (1986 ~ 2000) Caches show diminishing returns. ILP wall Control dependency Data dependency Power wall Dynamic power Frequency 3 Static ti power Frequency Total power The number of cores 17
18 Multi-core (4) Performance 1.73x Power PERFORM MANCE 1.13x 1.00x More MIPS/watt POWER Single Core Source: Intel Raise Clock (20%) Lower Clock (20%) PERFOR RMANCE 0.87x E FORMANC PER POWER 0.51x POW WER Dual Core 1.73x PER RFORMAN NCE 1.02x WER PO 18
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WAR: Write After Read
WAR: Write After Read write-after-read (WAR) = artificial (name) dependence add R1, R2, R3 sub R2, R4, R1 or R1, R6, R3 problem: add could use wrong value for R2 can t happen in vanilla pipeline (reads
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