From Pentium to Pentium 4: memory hierarchy evolution

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1 From Pentium to Pentium 4: memory hierarchy evolution Rui Miguel Borges Department of Informatics, University of Minho 4710 Braga, Portugal Abstract. This communication describes and compares the evolution of technical features developed for IA32 processors - Pentium to Pentium 4 to reduce the bottleneck memory. In previous years, the CPUs are increasing your clock rate and this feature was not followed by the memory technologies. But, the evolutions on hierarchy memory will permit to dream about more performance in future; the changes on caches memories are responsible for the main evolutions, such as, cache separated by data and instructions, dual independent bus, advanced transfer cache, new cacheability and execution trace cache. 1 Introduction A computer system s memory hierarchy has a large impact on its overall performance. The memory hierarchy on early computers was constituted by tree levels: CPU registers, main DRAM memory and disk storage. However, problem with time is that processors are waiting for data from memory, the architects create a small piece of hardware L1 cache between registers and memory. The L1 cache can be accessed on one or two clock cycles. Because the performance gap between the CPU and main memory is large the architects create more levels of cache memory. On our days we have tree levels of cache (on Xeon processors) on current chips. The cluster SeARCH is equipped with Xeon processors with tree levels of memory cache Trace Cache, L2 Cache and L3 Cache. The GPU nodes have 4 Mb of L2 cache and remains have 2 Mb. The Xeon processor has the same architecture of P4 processor. The caches allow a reduction of latency between CPU and main memory but increase latency between CPU and cache levels (L1 and L2), if large. The evolution on CPU chips, on previous years it was felt mainly on capacity of processing on CPU and the performance on memory does not have the same growth. That is, time to reduce the time to access (load, read, write) to the data blocks on each other level of hierarchy memory. The problematic is, how to define reasonable values to have more performance [1][2]: 1

2 Figure 1 - CPU/Memory Map (source: Professor Randy H. Katz) Reducing miss rate decrease number of references that are not satisfied in the upper level. ; Reducing miss penalty decrease time to access to the lower level on hierarchy memory; Reducing the miss penalty or miss rate via parallelism; Reducing the time to hit in the cache decrease time to send a word from cache to the CPU; 2 Features In the last years the IA32 processors architecture has had many evolutions to reduce the time to access the data between the levels of memory hierarchy. Cache separated by data and instructions Dual Independent Bus Advanced Transfer Cache New Cacheability Execution Trace Cache 2.1 Cache separated by data and instructions This technique separate instructions and data - was known by Harvard architecture, which allow in the same CPU clock to read the instruction word and data word [2]. 2

3 2.2 Dual Independent Bus On Pentium II, the architects of Intel developed the new feature, to increase the speed between L2 cache, CPU and main memory. They are creating two buses: system bus and cache bus. The processor can use both simultaneous to transfer and receive data from L2 cache or from main memory. With this, the system bus (100 Mhz) is faster in 50% than the first Pentium processors and L2 cache (225 Mhz) is faster than the first Pentium processors three times [4]. With this feature, after Pentium Pro, the L2 cache is a part of Processor package (not on-chip). 2.3 Advanced Transfer Cache The Advanced Transfer Cache is a 256-bit (32-byte) interface that transfers data on each core clock [7]. On Pentium III Coppermine, the L2 cache is on chip, which allows increase bandwidth between L2 cache and processor core. With this the latency could be reduced and the data word was received faster than in the previous versions. This feature was improved on Pentium 4, it is possible to transfer data at 48 Gb/s when on Pentium III it has a transfer rate of 16 Gb/s. These numbers are possible because the high-frequency of clock on Pentium 4 is increased and the processor is ability to keep the high-frequency execution units busy executing instructions instead of sitting idle. 2.4 New Cacheability The 8 instructions are referred by Intel as the New Cacheability instructions. They improve the efficiency of the CPU's Level 1 cache and allow sophisticated software developers to boost the performance of their applications or games. [4] 2.5 Execution Trace Cache The last innovation is this feature which permits to remove the instruction cache and add a new piece called trace cache, which permit to cache decoded instructions. The Execution Trace Cache is an innovative way to implement a 1st level instruction cache. It caches decoded IA-32 instructions (or micro-ops), thus removing the latency associated with the instruction decoder from the main execution loops. In addition, the Execution Trace Cache stores these micro-ops in the path of program execution flow, where the results of branches in the code are integrated into the same cache line. This increases the instruction flow from the cache and makes better use of the overall cache 3

4 storage space (12K micro-ops) since the cache no longer stores instructions that are branched over and never executed. The net result is a means to deliver a high volume of instructions to the processor s execution units and a reduction in the overall time required to recover from branches that have been mispredicted. [6][7] 3 Comparative Analysis Processors Characteristics [4][5][6] P5 family L1 cache separated by data and instructions (pre-decoded instructions) L1 cache with Harvard architecture: data cache (L1 d-cache) plus instruction cache (L1 i-cache) o 16 KByte, 4-way set associative, 32-byte cache line size; o 8 KByte, 2-way set associative for earlier processors; o write-back data L2 unified cache is off-chip; o Typically 256 or 512 KByte, 4-way set associative, 32 byte cache line size; P6 family Dual Independent Bus (DIB) ; L1 cache (i-cache and d-cache): o 16 KByte, 4 way set associative, 32 byte cache line size; o 8 KBytes, 2-way set associative for earlier P6 processors; L2 unified cache: o 128 KByte, 256 KByte, 512 KByte, 1 MByte or 2 MByte, 4 way set associative, 32 byte cache line size; o On processor package - before Pentium III Katmai o On-chip after Pentium III Coppermine - Advanced Transfer Cache New Cacheability instructions (Pentium III); Pentium 4 Execution Trace Cache; Trace cache: o 12K micro-op, 8-way set associative; L1 d-cache: o 8 KByte, 4-way set associative, 64 byte cache line size; L2 unified cache: o 256 or 512 KByte, 8-way set associative, sectored 1, 64 byte cache line size; o Increase data transfer rate; L3 unified cache Pentium Extreme Edition o 512 KByte or 1 MByte, 8-way set associative, sectored, 64 byte cache line size; 1 Sectored cache is a design trade-off between a low size of the tag array which is possible with large line size and a low memory traffic which requires a small line size 4

5 4 Conclusion Most architectural designs are characterized by fast processors, fast but small caches, and large but slow memories. As a result, problems of small sizes that fit in cache perform exceedingly well, whereas the performance of larger problems is limited by the speed of memory. Why large DRAM is not on processor chip? The memories on CPU chip are very expensive and today this feature is not possible. Intensive use of cache memories is the reasonable solution between performances versus cost of components. References [1] Hennessy, John L. and Patterson, David A.: Computer Architecture A quantitative approach Chapter 5, Third edition, Elsevier Science USA, 2003 [2] Bryant, Randal E., O Hallaron, David,: Computers Systems A programmer s perspective Chapter 6.3 and 6.4, Prentice Hall, 2003 [3] Monteiro, R., Neves, F., Pereira J., Rodrigues, N., Martinho, R.: Tecnologia dos Equipamentos Informáticos, Chapter 3, FCA, 2004 [4] Scott Mueller, Mark Edward Soper, Microprocessor Types and Specifications - Chapter 3, 16-19, 2006 [5] Intel: IA-32 Intel Architecture Software Developer s Manual. Volume 3: System Programming Guide, p 10-1 to 10-5, [6] Intel: The Microarchitecture of the Pentium 4 Processor, Intel Technology Journal Q1, 2001 [7] Intel: Desktop Performance and Optimization for Intel Pentium 4 Processor, Intel, Page 6-7, 2001 [8] Universidade do Minho, SeARCH cluster - 5

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