40-nm Stratix IV FPGAs
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- Christopher Norman
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1 40-nm Stratix IV FPGAs Innovation Without Compromise
2 Partnering With TSMC on 40-nm Development Altera and TSMC continue 15-year partnership A competitive edge for TSMC, Altera, and their customers Created leading-edge 40-nm process Employs 193-nm immersion photolithography, strained silicon, and extreme low-k material Accelerated development methodology Process co-development euse of core technologies Enhanced test chip methodology Allows for industry s fastest time to advanced processes Earliest access to 40-nm technology AND low-risk path to production 2
3 Stratix IV FPGAs: A Closer Look Highest density Up to 680K logic elements (LEs) Up to 22.4-Mbits internal AM Up to 1, x 18 multipliers Highest bandwidth and performance Up to 48 transceivers operating up to 8.5 Gbps Up to 4 x8 hard intellectual property (IP) blocks for PCI Express Gen 1 and Gen 2 Up to 748 giga multiply-accumulate operations per second (GMACS) digital signal processing (DSP) performance 2 speed grade performance advantage Lowest power Programmable Power Technology Quartus II PowerPlay technology 40-nm process benefits including 0.9V core voltage Highest density, highest performance AND lowest power Seamless FPGA prototyping to HardCopy ASIC production Quartus II 8.0: #1 in Performance and Productivity 3
4 Stratix IV FPGA Device Family Plan Device LEs Transceivers (8.5, 3.2 Gbps 1 ) LVDS I/Os Memory (Mbits) Multipliers (18x18) EP4SGX70 70K 24 (16,8) >40 > EP4SGX K 24 (16,8) >40 > Stratix IV GX device EP4SGX K 36 (24,12) EP4SGX K 36 (24,12) ,288 EP4SGX K 36 (24,12) EP4SGX K 36 (24,12) ,040 EP4SGX K 48 (32,16) ,024 EP4SE K EP4SE K ,288 Stratix IV E device EP4SE K EP4SE K ,040 EP4SE K ,024 EP4SE K , ,360 Notes: 1) Full duplex serial transceivers 2) Details on roadmap to faster speed transceivers available upon request Details subject to change 4
5 Stratix IV GX Device Package Plan Device F780 (29 mm) F1152 (35 mm) F1152 (35 mm) F1517 (40 mm) F1760 (43 mm) F1932 (45 mm) EP4SGX70 368, 28, 8 >450, >40, 24 EP4SGX , 28, 8 368, 28, 16 >450, >40, 24 Pin Migration EP4SGX , 28, 8 560, 44, , 44, , 88, 36 EP4SGX230 1 st Device 368, 28, 8 560, 44, , 44, , 88, 36 EP4SGX , 0, , 44, , 44, , 88, , 88, 36 EP4SGX , 0, , 44, , 44, , 88, , 88, 36 EP4SGX530 2 nd Device 560, 44, , 88, , 88, , 98, 48 Pin migration Total I/O, LVDS, transceiver counts Details subject to change Notes: FlipChip ball-grid array (BGA) with 1.0-mm pitch 5
6 Stratix IV E Device Package Plan Device F780 (29 mm) F1152 (35 mm) F1517 (40 mm) F1760 (43 mm) EP3SL , 112 Stratix III device EP3SE , 112 EP3SL , 112 1,104, 132 EP4SE , 56 EP4SE , 56 Stratix IV device EP4SE , , , 88 EP4SE , , , 88 EP4SE , , , 112 EP4SE , , 112 1,104, 132 Notes: FlipChip ball-grid array (BGA) with 1.0-mm pitch LVDS I/O count represents full duplex channels and are included in the total I/O count 6 Details subject to change
7 Unprecedented Transceiver Bandwidth Transceiver bandwidth (Gbps) Innovation Zone Devices kles Stratix II GX Stratix IV GX Virtex-5 LXT Virtex-5 SXT Virtex-5 FXT Transceivers available on both sides Up to 320 Gbps full-duplex bandwidth Up to 32 transceivers operating from 600 Mbps to 8.5 Gbps Up to 16 additional transceivers operating from 600 Mbps to 3.2 Gbps Up to 4 x8 PCI Express Gen 1, Gen 2 hard IP at 2.5/5.0 Gbps 7
8 Excellent 40-nm Transceiver Test Chip esults Transceiver test chip results Pattern: PBS 7 V od : 600 mv DJ: 10.3 ps J (MS): 1.23 ps Excellent jitter performance Low-risk path to production Watch the demo video at nm-stratix-iv-video.html 8.5 Gbps 8
9 obust Transceiver System Design 8.5 Gbps transceivers with superior signal integrity Jitter compliance for PCI Express, CEI-6, and Sonet/synchronous digital hierarchy (SDH) with margin Ability to drive 50 of F-4 backplane at Gbps with built-in pre-emphasis and equalization Plug & Play Signal Integrity, only from Altera Monitors and optimizes receive equalization over process, voltage, and temperature (PVT) Supports hot swapping of transceivers Watch the demo video to see Plug & Play Signal Integrity in action at 9
10 Protocol Support Protocol HardCopy IV ASICs Stratix IV FPGAs 3G Protocols PCI Express Gen 1 (x1, x2, x4, x8), PCI Express Cable Serial apidio (1x, 4x) Gigabit Ethernet, XAUI (IEEE 802.3ae), HiGig+ 3G Basic (proprietary), 3G SerialLite II CPI v3.0, OBSAI v2.0/p3-01 v4.0 SONET OC-3/12/48, GPON SATA, SAS SD, HD and 3G SDI, ASI Serial Data Converter (JESD204) SFI 5.1 Up to 8 Channels HyperTransport 3.0 Up to 8 Channels 6G Protocols PCI Express Gen 2 (x1, x2, x4, x8) HiGig2, CEI 6G (S/L), Interlaken, DD-XAUI, SPAUI 6G basic (proprietary), 6G SerialLite II 6G CPI/OBSAI Fibre Channel (FC1/FC2/FC4) 10
11 Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit + - Output egister Unit Optional ND & SAT Unit DSP Performance Through Parallelism ΣΣΣ + Optional ND & SAT Unit Output egister Unit + - ΣΣΣ + Σ + ΣΣΣ + ΣΣΣ + ΣΣΣ + + ΣΣΣ Optional ND & SAT Unit Output egister Unit + ΣΣΣ + Σ + ΣΣΣ Optimal DSP/memory/ logic ratio + ΣΣΣ + ΣΣΣ + ΣΣΣ Total 18 x 18 multipliers = 1,360 esources per 18 x 18 multiplier 400 registers + ΣΣΣ Maximum clock frequency = 550 MHz 17 Kbit embedded memory + ΣΣΣ DSP performance = 1,360 * 550 MHz = 500 LEs + ΣΣΣ 748 GMACS 11
12 Advantages Over Dedicated DSPs Combination of logic, memory, and multipliers allows for efficient implementation of arithmetic DSP functions Integrate multiple DSP devices into a single Stratix IV FPGA Process multiple signal data streams at lower cost per channel than dedicated DSP devices DSP DSP DSP DSP 12
13 Power Efficiency = Maximum Performance/Watt 40-nm process benefits enable power reduction Programmable Power Technology Highest performance where you need it, lowest power everywhere else 13
14 HardCopy IV ASICs: A Closer Look Seamless prototyping One design, one register transfer level Now with transceivers (TL), one IP set, one tool delivers FPGA and ASIC implementations Now with transceivers Low risk, lowest total cost access to deep sub-micron ASIC benefits Low power 50 percent or lower than companion FPGA Guaranteed first-time right The benefits of FPGAs AND the benefits of ASICs 14
15 HardCopy IV GX ASICs HardCopy IV GX ASIC Device 1 FPGA Prototype Packages 2 FF780 LF1152 FF1152 LF1517 FF1517 I/O Pins Memory Bits (Mbits) 18x18 Mult. PLLs ASIC Gates 3 HC4GX1YZ EP4SGX M M HC4GX2YZ EP4SGX M M HC4GX3YZ EP4SGX M 13.3M /6/8 9.2M HC4GX4YZ EP4SGX M 13.3M 832 3/6/8 7.7M HC4GX5YZ EP4SGX M 17.7M /6/8 9.4M HC4GX6YZ EP4SGX M M /8 11.5M Note1: Y = I/O count, Z = package type Note 2: Numbers in cells indicate package availability and denote the number of 6.5+ and 3.2+ Gbps transceivers. Performance may increase based on characterization Note 3: ASIC gates calculated as 12 gates per LE; 5000 gates per 18x18 multiplier. 15
16 HardCopy IV E ASICs HardCopy IV E ASIC Device 1 FPGA Prototype Packages F484 F780 F1152 F1517 I/O Pins Memory Bits 18x18 Multipliers PLLs ASIC Gates 3 HC4E2YZ EP4SE110 W,F W,F M M HC4E3YZ EP4SE230 W,F W,F M 1, M HC4E4YZ EP4SE290 W,F L,F L,F M 13.3M 832 4/8/12 7.6M HC4E5YZ EP4SE360 L,F L,F M 1,040 4/8/12 9.5M HC4E6YZ EP4SE530 L,F L,F M 1,024 8/ M HC4E7YZ EP4SE680 L,F L,F M 1,024 8/ M Note1: Y = I/O count, Z = package type Note 2: Performance may increase based on characterization Note 3: ASIC gates calculated as 12 gates per LE; 5000 gates per 18x18 multiplier 16
17 HardCopy IV E ASICs HardCopy IV E ASIC Device 1 FPGA Prototype Packages F484 F780 F1152 F1517 I/O Pins Memory Bits 18x18 Multipliers PLLs ASIC Gates 3 HC4E2YZ EP4SE110 W,F W,F M M HC4E3YZ EP4SE230 W,F W,F M 1, M HC4E4YZ EP4SE290 W,F L,F L,F M 13.3M 832 4/8/12 7.6M HC4E5YZ EP4SE360 L,F L,F M 1,040 4/8/12 9.5M HC4E6YZ EP4SE530 L,F L,F M 1,024 8/ M HC4E7YZ EP4SE680 L,F L,F M 1,024 8/ M Note1: Y = I/O count, Z = package type Note 2: Performance may increase based on characterization Note 3: ASIC gates calculated as 12 gates per LE; 5000 gates per 18x18 multiplier 17
18 Technical Engagement Process Tape in Bring up system with FPGA prepare design for hand-off Design center implementation andverification Tape out Production-quality, fully tested samples Custom mask fabrication assembly and test System ready Sample approval Production 6 weeks standard 8 weeks standard ~ 3 Weeks 12 Weeks Time to samples: 9-14 Wks Complete flow: as fast as 24 weeks 18
19 equired Tools HardCopy ASIC Standard cell ASIC COT TL synthesis Physical synthesis Simulation STA (front-end) Place and route (front-end) Pin planning Quartus II software Third-party EDA Power estimation Third-party EDA DFT STA (back-end) Place and route (back-end) Formal verification Parasitic extraction LVS/DC Single handoff turn-key process performed by Altera in 6 weeks typical ECO driven flow with numerous handoffs performed by ASIC vendor in 8 to 26 weeks Typical tool cost $3K ~$300K ~$1M 19
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