Hardware Reference Manual: Reference Design Application Note

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1 Hardware Reference Manual: Reference Design Application Note AN002 Introduction The Reference Design hardware board demonstrates the hardware s ability to interface between the computer, an 8051 microcontroller, Serial Flash memory, and an OSRAM OLED display. This application note provides a detailed technical description of the Reference Design Hardware board as a starting point for complex designs utilizing different types of OSRAM OLED display or a guideline to modify our existing design. Figure 1 shows the system block diagram, which consists of a rechargeable battery circuit for system power, an 8051 microcontroller, a serial flash memory, and an OLED display. 5V - 24V Power Supply Battery Charger System Power 3.3V 8051 Microcontroller 8080/6800 OLED Display Module SPI 3.3V, 12V RS232 UART Serial Flash Memory Figure 1. System Block Diagram Rechargeable Battery Circuitry The Reference Design Hardware board uses a constant current, constant voltage single cell 4.2V Lithium-ion battery charger controller, LTC4002ES The purpose to choose a switch mode battery charger is to minimize the current drain from the battery, generate less heat, and improve efficiency. It accepts any voltage input between 5V- 24V. When adequate power supplies to the board, the charging cycle initiates only if the battery voltage is below the 4.05V recharge threshold voltage. The charging algorithm is categorized into three stages: trickle charge, bulk charge, and constant voltage charge. The first stage is the trickle charge stage. If the battery voltage is below the trickle January 17, 2005 page 1 of 11

2 charge threshold voltage of 2.9V, the charger will consider the battery as a defective device and will terminate the charging cycle if the battery voltage doesn t rise to its trickle threshold voltage in half an hour. If the battery voltage reaches beyond the trickle threshold voltage, the bulk charge begins by increasing the charging current as the battery charging voltage ramps up. An internal timer will signify the charger to exit the bulk charge stage either after 2 hours charging time or the battery charge voltage reached to 4.2V. Bulk charge ends to begin the Constant Voltage stage. At this stage, the charging cycle continues for half an hour before the charging cycle being terminated by automatically enters a low current sleep mode. Along with the required external protection circuit on each Lithium-Ion battery cell, the Reference Design charger controller has an internal safety protection circuit to serve as a primary protector against overcharge, undercharge, or excessive current. If the input voltage is applied to the board for more than 3 hours or whenever the charge voltage reaches 4.2V, the charging cycle automatictly enters the sleep mode until the battery voltage drops below its threshold voltage of 4.05V. Designing a reliable battery charger circuit, choosing the right type of battery, and understanding the charger technology are essential to maximize its full potential and most importantly, to help avoid risk of injury. Figure 2. Battery Charger Circuitry January 17, 2005 page 2 of 11

3 Figure 2 is the battery charger circuitry, which consists of 8 pins as described below: Pin 1 is the COM pin, which serves as a Soft-Start and Shutdown Control Pin. When a charging cycle begins, the current at this pin has to be maintained at 100uA at 800mV to soft-start the IC. Otherwise, the IC shuts down. Pin 2 is the VCC power supply input voltage pin. It has to be at any voltage level between 5V 24V to activate the IC. Pin 3 is the Gate pin of the P-channel MOSFET, which serves at a gate current output drive. Pin 4 is the GND pin. Pin 5 is the charging control pin, which is pulled low when the battery is being charged. Otherwise, it is high impedance. Pin 6 is the Battery Sense Input pin, which is used to monitor the voltage at the battery to whether controlling the charger into the charging mode or sleep mode. Pin 7 is the Current Amplifier Sense Input pin to determine the charging current. It is calculated at 100mV/Rsense (R21). Pin 8 is the Thermistor Input pin. It is used to monitor the temperature of the battery cell. If the battery temperature is outside the range of 0 o C to 50 o C, it disables the charging circuitry Microcontroller Interface The Reference Design board uses the Philips 8051 microcontroller P89LV51RD2, which is programmed with the embedded software to function as the master controlling the entire hardware. It receives data from the computer using UART, Universal Asynchronous Receiver Transmitter, via the RS232 cable from the COM port, stores it in the Serial Flash Memory via the SPI bus before sending it to the OLED display. Communications between UART and P89LV51RD2 Microcontroller Sending data to most microcontroller devices using RS232 protocol is very simple because they have a built-in UART. Data is sent or received serially using the 9-pin connector COM port on the back of most computers. However, in many applications, there are only three pins to be used: RXD for Receiving, TXD for Transmitting, and the Ground signal, GND. We always refer to the computer as the master and the 8051 microcontroller as a slave. Therefore, using the computer s perspective, transmitting data using the UART s TXD signal is referring to data to be sent from the computer to the 8051, and receiving data via the UART s RXD signal is referring to data to be transferred from the 8051 microcontroller to the computer. Since it doesn t have a clock signal or control line to initiate the communication, the port has to be configured correctly before data can be transmitted or received via the COM port. The UART communication has 4 modes of operation. Mode 0 is for a standard 8-bit shift registers where only 8-bit of data is shifted serially. Mode 1 is used when the communication has 1 Start bit, 8 Data bits, and 1 Stop bit. This mode is commonly used. Mode 2 and 3 has 1 Start bit, 8 Data bits, 1 Parity bit, and 1 Stop bit. The baud rate is calculated as: Baud rate = (External Oscillator Frequency/(384 * (256 TH1))) where TH1 is the timer on the 8051 microcontroller. Referred to the Reference Design Software Application Note for further instructions on baud rate settings. January 17, 2005 page 3 of 11

4 Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Figure 3. Asynchronous Data Frame Stop Bit Figure 3 is an example of a typical asynchronous data frame, which consists of one Start bit, 8 Data bits with LSB transmitted first, and a Stop bit. The transmitter always brings the Start bit to low to signify the receiver that the followed 8 bits are the actual data bits. When data is successfully received, the communication ends by bringing the Stop bit to high. Depending on what mode is set, some mode has a parity bit that is generated by the receiver. Its main function is to perform error checking. The receiver always looks for a Stop bit to frame the receiving data byte. If it doesn t receive the Stop bit as expected, it uses the Parity bit to report a communication error to the transmitting device. Without the Start and Stop bits, there is no way the receiver knows when to receive data from the transmitter using UART. UART data UART clock Start Start Bit 8 clocks D0 bit Figure 4. UART Receiver Clock Format In any type of communication, timing always plays an extremely important role. If the sender is faster than the receiver, or vice versa, then the communication is corrupted. In UART communications, the baud rate, which is the speed at which the serial data is transferred in bits per second, has to be configured so that the transmitter and the receiver send or receive data at the same clock speed. Figure 4 illustrates a waveform of the receiver when receives a data frame. The UART hardware has an internal clock to synchronize the received data, which is 16 times faster than the bit rate. Therefore, every bit of data has 16 UART internal clocks. When the Start bit goes low to initiate the data transfer, the UART starts its internal counter to 16 clocks. The receiver always samples the data bit at the 8th clock. The counter is reset after every 16 th clock to restart the same sequence for sampling the next data bit. P89LV51DR2 Receiving Serial Data via RS232 Protocol The microcontroller has a designated serial communication interrupt to send and received data from the serial communication port. The microcontroller automatically enables the serial interrupt to signify that a new byte of data arrives from the serial port. The microcontroller stops whatever it is doing to serve the serial interrupt request. When the microcontroller receives a byte of data, it converts into an 8-bit parallel format before automatically storing it in a Special Function Register (SFR) SBUF and set the RI flag to high. RI flag is a received interrupt flag that when high, it signifies that the entire 8 bit of data has successfully been received and stored in SBUF. After retrieving data from SBUF, RI flag has to be reset to low by software to prepare for the arrival of the next data byte. January 17, 2005 page 4 of 11

5 Figure 5. Schematic for RS232 Interface to P89LV51RD2 Microcontroller Figure 5 schematically shows RS232 communications interface between the computer and the 8051 microcontroller. Port 3.0 is an I/O pin but at anytime can be configured as a RXD signal to receive data from the computer and Port 3.1 is a TXD signal to transmit data to the computer. Because RS232 uses a single ended signal referencing to the GND to indicate data voltage levels, the voltage at the COM port ranges between 12V to 12V. When sending to or receiving data from the computer, the data voltage level is from 3V to 12V for logic 0 and 3V to 12V for logic 1. Any voltage between -3V to 3V is for noise margin. Because the 8051 microcontroller, P89LV51RD2BBC, can only handle voltage level from 0V to 3.3V, the MAX3232CWP functions as a voltage translator to generate the necessary voltage level to perform any serial communications. January 17, 2005 page 5 of 11

6 SPI Communication Between Flash Memory and P89LV51RD2 Figure 6 shows the hardware interface between a 4Mbit SPI (Serial Peripheral Interface) Serial Flash memory from SST and the P89LV51RD2 microcontroller. The Serial Flash is an erasable programmable memory that data can be stored or retrieved from. The 8051 microcontroller plays the role of SPI bus master to accesses the memory. P89LV51RD2 Microcontroller CLK CE_n SI SO Serial Flash Memory Figure 6. SPI Communication to P89LV51RD2 Microcontroller HOLD_n WP_n VCC In addition to the Write Protected pin (WP_n) that is used to protect the memory from any write or erase operation, the Hold pin (HOLD_n) is used to halt any active operation with the memory, the SPI Serial Flash communications has 4 wires: chip enables (CE_n), serial data input (SI), serial data output (SO), and serial clock (SCK). The CE_n is a control signal to enable the flash. Designer has to enable this pin by bringing it to low before performing any read, write, or erase operations. Using the SPI SCK signal to synchronize the communications between the microcontroller and the memory. When CE_n is low, memory is ready to receive data via the SO line on the falling edge of the clock and send data to the 8051 microcontroller via the SI line on the rising edge of the SCK as shown on Figure 7. CE_n SCK SI SO Invalid Data Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 High Impedance Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Figure 7. SPI Timing Many modern microcontrollers have built-in SPI. In our case, Port 1.4 to Port 1.7 of the microcontroller are used to configure for SPI communications. There are three SFR registers that are allocated for SPI: SPCR for SPI control register, SPSR for status register, and SPDR for data register. Once configured by writing a byte to the SPCR register, the SPSR register is used to indicate the status of the data transfer and the state of the memory. Configuring the SPI port is simple, communicating using SPI port is even simpler. All we have to do is to write or read data from the Serial Flash memory by writing or reading data from the SPDR SFR without worrying about its timing or controlling appropriate signals to initiate the communications. January 17, 2005 page 6 of 11

7 Communications Between 8051 Microcontroller and OLED driver The Reference Design board has the flexibility to communicate to an OLED driver by either configuring for an 8-bit 6800-serial Motorola interface or 8080-series Intel interface. 4-wire SPI communication is independent from the hardware because it is a can be modified from the display module by changing a jumper on the flex circuit. Connecting the BS1 (C86) to VCC by installing R25 will set the OLED driver to 8800 parallel interface. If BS1 (C86) is connected to GND by installing R26, it opens the communication to an OLED driver using 6800 interface. Refer to Figure 7 for interface setting. BS BS1 BS Series Parallel Interface 8800-Series Parallel Interface Serial Interface (SPI) Figure 7. Interface Protocol CS_n: This is the chip select input pin. It enables the 8051 microcontroller to communication to the OLED driver. RESET_n: This is the reset input pin. It resets the OLED driver by turning the OLED display off, all registers are set to default values. BS1 (C86): This pin is used to configure the OLED driver to choose different interface protocol. If this pin is low, the OLED driver is configured to 6800-series interface. If this pin is high, it is configured to 8080-series interface. D/C_n: If this pin is high, the data byte to be sent to an OLED driver is data. Otherwise, it is a command. R/W (WR_n): This pin is pulled low to enable the 8051 microcontroller to perform a write operation. E (RD_n): Pull this pin to low to read the status register from the OLED driver. DATA [7:0]: Data Byte VDC: 12 V OLED driver power GND: Ground OLED Driver SSD0323 CS_n RESET_n BS1(C86) D/C_n R/W(WR_n) E(RD_n) DATA[7:0] VCC (3.3V) VDC (12V) GND P89LV51RD2 Microcontroller Figure 8. Communication to OLED Driver Block Diagram The 8080-series interface requires 8 bidirectional data signals (D0-D7), E (RD_n), R/W (WR_n), D/C_n, CS_n, and RESET_n. The microcontroller is capable of driving as many OLED drives as it desires. All signals can be shared among each other except CS_n control line. It is used to enable the communications to any specific driver. Designers can request either a write or read operation. When CS_n is low, R/W (WR_n) is low to enable the write operation, if D/C_n is low, the data will be written to the OLED driver s command register as a command. If D/C_n is high, data will be interpreted as data and will be stored in the OLED data RAM. If R/W (WR_n) is high and E (RD_n) is low, the OLED driver will clock January 17, 2005 page 7 of 11

8 out the status data from its status register. Notice that the data from the command register or its data RAM can t be read. The 8600-series consists of exact signal as the 8080-series but the timings between them are different. Serial interface uses SPI protocol that consists of Serial Clock, SCLK (D0), Serial Data (D1), SDIN, D/C_n, and CS_n. When CS_n is active low to select desire OLED driver, if D/C_n is low to shift a command byte into an 8-bit command shift register on the rising edge of the SCLK with MSB (Most Significant Bit) first. If D/C_n is high, 8-bit data is shifted into an 8_bit Data RAM. Refer to the specific product specifications for timing information. Depend on each application s requirements, one common advantage of using Serial interface over parallel interface is that it requires very minimal signals. However, the trade-off is the speed is slower and it requires more software effort to manipulate data. January 17, 2005 page 8 of 11

9 January 17, 2005 page 9 of 11

10 January 17, 2005 page 10 of 11

11 Author: Paulina T. Nguyen OLED Display Engineering San Jose, USA About Osram Opto Semiconductors Osram Opto Semiconductors GmbH, Regensburg, is a wholly owned subsidiary of Osram GmbH, one of the world s three largest lamp manufacturers, and offers its customers a range of solutions based on semiconductor technology for lighting, sensor and visualisation applications. The company operates facilities in Regensburg (Germany), San José (USA) and Penang (Malaysia). Further information is available at All information contained in this document has been checked with the greatest care. OSRAM Opto Semiconductors GmbH can however, not be made liable for any damage that occurs in connection with the use of these contents. January 17, 2005 page 11 of 11

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