Group #6 Sam Drazin (Partner: Brian Grahn) Lucas Blanck, TA


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1 Digital Design Lab EEN 35 Section H Lab # Seven Segment Display / Sequence Detector Group #6 Sam Drazin (Partner: Brian Grahn) Lucas Blanck, TA University of Miami February, 28
2 Abstract The purpose of this lab was to become comfortable with the ins and outs of utilizing a breadboard, as well as constructing a proper seven segment display and sequence detector using only NAND gates and one D Flip Flop. Important points of the project included overcoming certain logic obstacles such as creating a five input prime implicate with only two, three and four input NAND gates. Another goal of this project was to accustom ourselves with problem solving techniques necessary for de bugging circuits with a large range of possible weaknesses / points of possible error. This lab also was successful in familiarizing us with the Voltage Sources in the lab, and showing us how power, input switching, and manual clock cycles are all variables that we have the ability to control. The key results of our Lab were to create a seven segment display that would show numbers one through nine with the appropriate binary value input, and show nothing for any numbers above that when inputted. The sequence detector was designed to show until it received the sequence, upon which its output would show. Overlapping was okay in this scenario. My overall conclusion is that this lab was a good launching point to learn the workings of a breadboard, and the goal was a reasonable and relatable outcome to achieve that was a familiar and understandable circuit from EEN 34. 2
3 Table of Contents Overview... 4 Objectives... 4 Equipment... 4 Description... 5 Specifications... 6 Design Synthesis... 6 Complete Logic Diagram Questions.. Conclusion... 3
4 Overview This experiment embodies a very simple, yet versatile application of Logic circuits. A seven segment display is wide used in most digital notation of numbers (clocks, signs, etc.), and designing one is trivial and common in Logic. The seven segment display is divided into seven parts, each labeled with a different letter. To wire a seven segment display, one must utilize the proper inputs from a power source, a ground, and four inputs (both regular and compliment) to wire each segment appropriately to be able to control the display. Then, a special Flip Flop must be implemented to recognize a certain input from a single switch and should display a whenever it sees a certain pattern. Boolean algebra and Logic are both crucial precursors to understanding these concepts. Objectives The student must create a seven segment display that responds to binary inputs zero through nine by displaying the decimal digit, and responds to any binary input over nine with nothing. A sequence detector must be implemented as well to recognize the sequence from the lease significant bit and display when the pattern is received, and zero all other times (overlapping is okay). Equipment The IC s that we used for this lab were:  Five 74 Quad 2 Input NAND gates  Five 74 Triple 3 Input NAND gates  Three 742 Dual 4 Input NAND gates  One 7474 Dual Positive Edge Triggered D Flip Flop 4
5 Description To begin the design of this project, the seven segment display had to be set up primarily. To do this, we first had to draw out the display and realize which displays (A G) were to be powered to signify each number. This data was portrayed in a Truth Table comparing four X inputs and seven letter outputs (corresponding to the user inputs and LED outputs respectively). The Truth Table then assisted us in organizing and completing a set of K Maps which each portrayed a different letter s specific Boolean formula. The K Maps were solved for equations for each letter of the seven segment display, and the formulas were compiled on a single list of equations, each implicate assigned with its own number. Once complete with the K Maps, another list of individual terms was then compiled, removing all repeated Boolean components. The list of prime implicates and unique non prime implicates was then used to assign a list of inputs that each NAND gate would receive. To begin, all of the simple implicates were assigned to the gates; any two element implicates or any involving X and or were established. Then, the more complex implicates were assigned, both creating new terms and using already created ones. Once all implicates were designated, the chips were set on the breadboard and the wiring of the circuit could begin. With the layout of the gates already designated, wiring the circuit was much simpler than anticipated. Each gate was supplied with power and connected to ground, and the appropriate inputs were wired to their assigned implicates. Repeated terms were wired to the same existing implicates whenever possible. Once we had completed setting up all of the gates, all that had to be done was to connect the corresponding LED s to the correct output of each gate. Once they had the right output, power, and a ground, the display worked perfectly when controlled by the user input switches. In designing the sequence detector, we had to complete the State Machine outline by modeling it on paper. The State Machine diagram allowed us to create a Next State table which gave us the input requirements to recognize the sequence. We then used K Maps to extract the formulas that the D Flip Flop would need to detect the appropriate sequence. With the formulas from the K Maps, we designed a circuit on paper that would take a single user input with a manual clock and detect the desired sequence while allowing overlapping. From there, we needed to convert our seven segment display to a sequence detector. To convert the seven segment display into a sequence detector, we first had to ground the three most significant bits due to the fact that the sequence that was to be detected was solely comprised of s and s. Once isolated, the least significant bit was ready to be integrated with the D Flip Flop to wait for the proper sequence. By adding several more implicates to our existing gates and altering the expected input via the Flip Flop, we were able to create the sequence detector that recognized and gave an output of, and otherwise showed. 5
6 Specifications Only NAND gates were allowed to be used to create the seven segment display. The sequence detector utilized only NAND gates and one D Flip Flop. Design Synthesis Truth Table N X X2 X3 X4 A B C D E F G The Truth Table was filled out using basic Logic Design concepts. The left side in blue is organized by incrementing binary values, each X N term representing one binary bit (most to least significant left to right). The letters on the right side in light pink represent the different segments of the seven segment display. For each binary numeric entry, the LED s with s (rather than s) will light to create the decimal number (N) corollary to the binary input. 6
7 K Maps The K Maps above represent each individual LED element (labeled as letters). These are constructed by reading down the right side of the Truth Table for each letter, and filling out the K Map accordingly to the value on the left side of the table. Circled in varying colors are the implicates (prime and non) that comprise each elements behavior. s must be circled in groups of 2 n quantities (,2,4,8 ). Any grouping of s in which a certain is only able to be circled by one color only is known as a prime implicate, because that grouping of s is necessary to the completion of the K Map. Boolean Expressions A = X X 3 + X 2 X 3 X 4 + X X 2 X 3 + X X 2 X 4 B = X X 2 + X 2 X 3 + X X 3 X 4 + X X 3 X 4 C = X 2 X 3 + X X 2 + X X 3 D = X 2 X 3 X 4 + X X 2 X 3 + X X 2 X 3 + X X 3 X 4 + X X 2 X 3 X 4 E = X 2 X 3 X 4 + X X 3 X 4 F = X X 3 X 4 + X X 2 X 3 + X X 2 X 4 + X X 2 X 3 G = X X 2 X 3 + X X 2 X 3 + X X 2 X 3 + X X 3 X 4 These formulas listed above are derived from the K Maps. Each one is specific and tailors exactly to the K Map of its equal name. To find these formulas, one must find the groupings of 2 n s on the K Maps. Where they are circled are the most efficient ways to group as few as possible while still covering every single. From the circled implicate, one must see where the s in that block share common terms (derivable from the little numbers on top of/to the left of every K Map). The top numbers signify X and X 2, while the left numbers signify X 3 and X 4. A in those terms represents a normal, or high value, while a represents a 7
8 complemented ( ), or low value. In the example of the K Map for A, the orange circle in the bottom left corner shares the first term on top, as well as the first term on the bottom. The top one (X ) is, and the left one (X 3 ) is ; hence, the resulting term is X X 3. This process is done to retrieve all circled implicates to gather all of the formulas for each element. Complete Logic Diagram For the ease of showing and comprehending the circuit, all implicates will be numbered (P N ) for organization s sake in the following fashion: P = X X 3 X 4 P 2 = X X 2 X 3 P 3 = X X 2 X 3 P 4 = X X 2 X 3 P 5 = X 2 X 3 X 4 P 6 = X X 2 X 4 P 7 = X 2 X 3 P 8 = X X 2 P 9 = X X 4 P = X X 2 P = X X 3 X 4 P 2 = X X 3 X 4 P 3 = X X 3 P 4 = X X 2 X 3 X 4 P P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 9 P P P 2 P 3 P 4 8
9 This Logic diagram shows the different prime implicates run to their appropriate NAND gates, each specified with its own source LED (A G). The NAND gates are fed to the LED s, and with the appropriate binary input, the decimal digit ( 9) will appear on the seven segment display. Connections were made via the breadboard with our jumper kit, and although we utilized specific IC s with set numbers of inputs and outputs to form implicates, the diagram above reads completely true to which terms were sent to each LED. Considering the sequence detector, X, X 2 and X 3 were all grounded to isolate the least significant bit. Then, a single switch and a manual clock were wired together with the Flip Flop and the existing seven segment display. The following new implicates were utilized: P 5 = BX P 6 = AB X P 7 = AB A and B represent the two outputs from the Flip Flop, and X represents the user input (either or ). Below are the steps taken to calculate and create the sequence detector. State Machine S / S / S 3 / S 2 / This State Machine diagram shows the process the circuit must take between states to accomplish the detection of the sequence. Because it s Moore model, the output is shown by step as the number after the slash in each state. Next State Table AB PS X = X = Z S S S2 S3 This Next State Table illustrates how at each present state (PS), the value of X determines which of the states the machine will go to next, as each two bit binary number 9
10 correlates with a state, shown on the left. A and B are each a Flip Flop used each as a bit of binary to represent four states. K Maps The K Maps above represent the progression of the Next State table in the previous state. Each one signifies the behavior of each Flip Flop, both A and B. Boolean Expressions D A = AX + AB X D B = X Similarly to the other Boolean Expressions, these formulas accurately describe the behavior of each Flip Flop in detecting the correct sequence. Complete Logic Diagram B X A B X D A Q A Q A Z X D B Q B Clock Q B
11 Questions X X X 2 3 4: X X D A 4: X 2 X 3 D B A B A B Sequence detectors can be utilized to accomplish many things, especially in the digital world we live in today. Several applications of a sequence detector can be found in the transfer of the digital audio protocol, MIDI (Musical Instrument Digital Interface). Whenever you plug in an electronic keyboard or synthesizer into a computer using a MIDI interface, each note that is played or knob that is turned sends a MIDI message to the audio device. When the musician presses down on a key, the computer is sent a Note On call, which no doubt is detected by a sequence detector. This tells the computer that the certain note specified in the message following the Note On call has been played. Likewise, the release of any note triggers a Note Off call, which works in exactly the same way. With all MIDI data transfers and controllers, the sequence detector is constantly at work, awaiting certain sequences and performing appropriately when a certain combination of data is received. Conclusion In conclusion, I come away from this lab with a much clearer understanding of physical Logic circuits and breadboards. The seven segment display and sequence detector were both excellent examples of Logic problems we covered in EEN 34, and having to implement them by hand was not only a great learning experience, but an eye opening connection between the theoretical and the actual in the world of integrated circuits and Boolean Logic. We certainly had problems along the way in the debugging efforts and wire mapping, but all in all, this project went over very well, and I enjoyed it thoroughly.
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