Seven-Segment Display

Save this PDF as:

Size: px
Start display at page:

Transcription

1 ENEE 245: Digital Circuits & Systems Lab Lab 8 Seven-Segment Display ENEE 245: Digital Circuits and Systems Laboratory Lab 8 Objectives The objectives of this laboratory are the following: To become familiar with the seven-segment displays on the Nexys2 board To design a circuit using decoders and multiplexers that drives the seven-segment displays on the Nexys2 board To implement a 4-digit hex-to-7-segment decoder on the Nexys2 FPGA prototyping board Seven-segment displays are commonly used as alphanumeric displays by logic and computer systems. A seven segment display is an arrangement of 7 LEDs (see below) that can be used to show any hex number between 0000 and 1111 by illuminating combinations of these LEDs. For example, the red digits on a digital clock use 2-segment LED displays. 7-segment displays come in two flavors: common anode and common cathode. A common anode 7-segment display has all of the anodes tied together while a common cathode 7-segment display has all the cathodes tied together. A 7-segment display contains seven light emitting diodes (LEDs) Seven-Segment Displays on the Nexys2 Board The Nexys2 board has four 7-segment displays. Each seven-segment display consists of seven LED bars and a single LED round (for the decimal point), as shown in the figure below. You can reference the Digilent Nexys2 Board Reference Manual for more information: 1

2 ENEE 245: Digital Circuits & Systems Lab Lab 8 Nexys2 seven-segment displays The Nexys2 board uses the common anode method for its displays. This means that all the anodes are tied together and connected through a pnp transistor to +3.3V, as shown in Figure 7.3. A different FPGA output pin is connected through a 100Ω current-limiting resistor to each of the cathodes, a g, plus the decimal point. A control signal of 0 will turn on an LED segment and a signal of 1 will turn it off. A hex-to-7-segment decoder takes a 4-bit input (a Hex digit) and generates the corresponding 8-bit pattern to light the appropriate LED segments in the display. Nexys2 I/O devices and circuits 2

3 ENEE 245: Digital Circuits & Systems Lab Lab 8 The table below shows output cathode values for each segment a g needed to display all hex values from 0 F. x a b c d e f g = off = on A B C D E F Hex-to-7-Segment Decoder: Logic Equations To display hexadecimal digits on a 7-segment display, we need to design a hex-to-7-segment decoder (called hex7seg), whose input is a 4-bit number (x[3:0]), and outputs are the 7-segment values a g given by the truth table above. We can make a Karnaugh map for each segment and then develop logic equations for the segments a g. For example, a logic equation for the segment e is e = ~x[3] & x[0] ~x[3] & x[2] & ~x[1] ~x[2] & ~x[1] & x[0] You can similarly develop equations for the other six segments and then write the Verilog program for the 7-segment decoder. Multiplexing 4 Hex-to-7-Segment Displays As described in the Nexys2 User s Guide, the Nexys2 board designers saved FPGA pins by wiring the four seven-segment displays to the same set of control lines. The user can display four separate characters simultaneously by time-multiplexing the seven-segment display control lines at a fast enough rate so that the human eye views all four of the displays as ON and displaying the correct value. Each digit is illuminated just one-quarter of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the digit appears continuously illuminated. If the refresh rate is slowed to about 45 hertz, the display will start flickering. For each of the four digits to appear bright and continuously illuminated, all four digits should be driven at least once every 16 ms, for a refresh frequency of 60 Hz. In a 60 Hz refresh scheme, the entire display would be refreshed once every 16 ms, and each digit would be illuminated for ¼ of the refresh cycle, or 4 ms. The controller must drive the cathodes with the correct pattern when the corresponding anode signal is driven. To illustrate the process, if AN0 is asserted while CB and CC are asserted, then a 1 will be displayed in digit position 1 (leftmost of the four displays). Then, if AN1 is asserted while CA, CB and CC are asserted, then a 7 will be displayed in digit position 2. If AN0 along with CB and CC are driven for 4 ms, and then A1 along with CA, CB, and CC are driven for 4 ms in an endless succession, the display will show 17 in the first two digits. The figure below shows an example timing diagram for a four-digit controller. 3

4 ENEE 245: Digital Circuits & Systems Lab Lab 8 Seven-segment display timing diagram Counters and Clock Dividers Our 4-digit seven-segment controller will take a clock and four characters (4-bit each) as inputs, and will write the seven-segment control signals as well as the four anode signals to display all four characters simultaneously. The figure below shows a block diagram of a possible implementation of this controller. A block diagram of a possible implementation of the seg7_driver Clock Converter To sequence through the display anodes, you will need to have a clock in your design. The Nexys-2 board has an onboard 50 MHz clock. This 50 MHz clock signal is a square wave with a period of 4

5 ENEE 245: Digital Circuits & Systems Lab Lab 8 20 ns. This clock signal is too fast for this application, so you will need to down convert that clock for this lab. For example, you can down convert the 50 MHz clock to 1 KHz, using an N-bit counter, whose block diagram is shown in the figure below. Block Diagram of an N-bit Counter The following Verilog program can be used to generate this counter. Note that the sensitivity list of the always statement contains the phrase posedge clk or posedge clr. This means that the if statement within the always block will execute whenever either clr or clk goes high. If clr goes high then the output q[n-1:0] will go to zero. On the other hand, if clr = 0 and clk goes high, then the output q[n-1:0] will be incremented by 1. The default value of the parameter N in this code is 4. A simulation of this 4-bit counter is shown in the figure below the code. Note that this counter counts from 0 to F and then wraps around to 0. // Example N-bit counter module counter #(parameter N = 4) (input wire clr, input wire clk, output reg [N-1:0] q ); // N-bit counter clk or posedge clr) begin if (clr == 1) q <= 0; else q <= q + 1; end endmodule 5

6 ENEE 245: Digital Circuits & Systems Lab Lab 8 Simulation of the 4-bit counter In these simulation results, note that the output q[0] is a square wave at half the frequency of the input clk. Similarly, the output q[1] is a square wave at half the frequency of the input q[0], the output q[2] is a square wave at half the frequency of the input q[1], and the output q[3] is a square wave at half the frequency of the input q[2]. Note also that the binary numbers q[3:0] count from 0000 to You can instantiate larger counters such as a 24-bit counter, for instance, that would count from 0 to by using an instantiation statement such as the following: counter #(.N(24)) cnt24 (.clr(clr),.clk(clk),.q(q) ); Thus, a counter can be used to divide the frequency f of a clock, where the frequency of the output q(i) is f i = f / 2 i+1. This shows one way you can obtain a lower clock frequency by simply using one of the outputs q[i]. For instance, the output q[0] will have a frequency of 25 MHz, the output q[17] will have a frequency of Hz, and the output q[23] will have a frequency of 2.98 Hz. Anode Driver Unit Using the clock signal, you need to develop a system that time-multiplexes among signals AN3-AN0 as depicted earlier. This will require using some sequential logic elements. The figure below shows a block, which provides the desired signals described beneath it. 6

7 ENEE 245: Digital Circuits & Systems Lab Lab 8 " Clk: The Clock for this component can be set to 1 KHz Reset: Resets this block (on logic 1) CE: Enables this component (on logic 1) O_1,O_0: binary representation of the activated output. AN0-AN3: Active low outputs that will activate selected anode. Anode driving block During each clock period only one of the outputs (AN3-AN0) is activated and O_1, O_0 corresponds to the active signal 00, 01, 10 or 11. The sequence O_1, O_0 can be generated by a 2- bit counter that counts input clock tics. Thus, the output of a 2-bit counter cycles from 00 to 11, incrementing the count with each clock tic. After O_1O_0 = 11 is generated on the fourth clock cycle, the count will rollover back to 00 and continue. To generate the individual anode control signals AN0-AN3, you can use a 2-to-4 decoder with O_1, O_0 as the inputs. However, remember that AN0-AN3 need to be active LOW outputs. Pre-Lab Preparation Part 1: Reading Read pages 4-6 in the Nexys2 Board Reference Manual available at Data/Products/NEXYS2/Nexys2_rm.pdf Part 2: Hex-to-7-Segment Decoder Using Continuous Assignment 1. Design a hex-to-7-segment decoder, with x[3-0] as input. 2. Define Inputs and Outputs. Draw a block diagram of the circuit showing the inputs and outputs for the circuit. 3. Draw a truth-table that shows the 4 inputs and the 7 outputs. 4. Create Verilog code using continuous assignment statements. 5. Functional Simulation. Perform a functional simulation of the circuit to verify that it is working correctly. 6. Create a symbol for the hex7seg to use in the graphical editor. This creates a symbol file that is a Graphic File and can be viewed and edited by opening it. Part 3: Hex-to-7-Segment Decoder Using Case Statement 7. Design a hex-to-7-segment decoder using the Verilog case statement. 8. Perform a functional simulation of the circuit. Paste the results in your prelab report. 7

Multiplexers Two Types + Verilog

Multiplexers Two Types + Verilog ENEE 245: Digital Circuits and ystems Laboratory Lab 7 Objectives The objectives of this laboratory are the following: To become familiar with continuous ments and procedural

Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts)

Dr. Greg Tumbush, gtumbush@uccs.edu Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement

Lab 17: Building a 4-Digit 7-Segment LED Decoder

Phys2303 L.A. Bumm [Nexys 1.1.2] Lab 17 (p1) Lab 17: Building a 4-Digit 7-Segment LED Decoder In this lab your will make 4 test circuits, the 4-digit 7-segment decoder, and demonstration circuit using

CHAPTER 11: Flip Flops

CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach

Modeling Registers and Counters

Lab Workbook Introduction When several flip-flops are grouped together, with a common clock, to hold related information the resulting circuit is called a register. Just like flip-flops, registers may

EXPERIMENT 8. Flip-Flops and Sequential Circuits

EXPERIMENT 8. Flip-Flops and Sequential Circuits I. Introduction I.a. Objectives The objective of this experiment is to become familiar with the basic operational principles of flip-flops and counters.

3-Digit Counter and Display

ECE 2B Winter 2007 Lab #7 7 3-Digit Counter and Display This final lab brings together much of what we have done in our lab experiments this quarter to construct a simple tachometer circuit for measuring

LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters

LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters LAB OBJECTIVES 1. Introduction to latches and the D type flip-flop 2. Use of actual flip-flops to help you understand sequential

Introduction to Digital Design Using Digilent FPGA Boards Block Diagram / Verilog Examples

Introduction to Digital Design Using Digilent FPGA Boards Block Diagram / Verilog Examples Richard E. Haskell Darrin M. Hanna Oakland University, Rochester, Michigan LBE Books Rochester Hills, MI Copyright

Decimal Number (base 10) Binary Number (base 2)

LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be

Counters and Decoders

Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students

Session: 2220 Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students Adam S. El-Mansouri, Herbert L. Hess, Kevin M. Buck, Timothy Ewers Microelectronics

The components. E3: Digital electronics. Goals:

E3: Digital electronics Goals: Basic understanding of logic circuits. Become familiar with the most common digital components and their use. Equipment: 1 st. LED bridge 1 st. 7-segment display. 2 st. IC

Modeling Latches and Flip-flops

Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,

Seven-Segment LED Displays

Seven-Segment LED Displays Nicholas Neumann 11/19/2010 Abstract Seven-segment displays are electronic display devices used as an easy way to display decimal numerals and an alterative to the more complex

Interfacing To Alphanumeric Displays

Interfacing To Alphanumeric Displays To give directions or data values to users, many microprocessor-controlled instruments and machines need to display letters of the alphabet and numbers. In systems

Lab 11 Digital Dice. Figure 11.0. Digital Dice Circuit on NI ELVIS II Workstation

Lab 11 Digital Dice Figure 11.0. Digital Dice Circuit on NI ELVIS II Workstation From the beginning of time, dice have been used for games of chance. Cubic dice similar to modern dice date back to before

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation

Finite State Machine Design A Vending Machine

LAB 6 Finite State Machine Design A Vending Machine You will learn how turn an informal sequential circuit description into a formal finite-state machine model, how to express it using ABEL, how to simulate

A Verilog HDL Test Bench Primer Application Note

A Verilog HDL Test Bench Primer Application Note Table of Contents Introduction...1 Overview...1 The Device Under Test (D.U.T.)...1 The Test Bench...1 Instantiations...2 Figure 1- DUT Instantiation...2

Digital Electronics Detailed Outline

Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept

Lab 1: Full Adder 0.0 Introduction In this lab you will design a simple digital circuit called a full adder. You will then use logic gates to draw a schematic for the circuit. Finally, you will verify

Digital Fundamentals. Lab 8 Asynchronous Counter Applications

Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003). Horne Rev. 2 (1/2008). Bradbury Digital Fundamentals CETT 1425 Lab 8 Asynchronous Counter Applications Name: Date: Objectives:

An Integer Square Root Algorithm

An Integer Square Root Algorithm 71 Example 24 An Integer Square Root Algorithm The C algorithm shown in Fig. 2.8 performs an integer square root of the input a as shown in Table 2.1. Note from Table 2.1

Module 3: Floyd, Digital Fundamental

Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental

Digital Circuit Design Using Xilinx ISE Tools

Digital Circuit Design Using Xilinx ISE Tools Contents 1. Introduction... 1 2. Programmable Logic Device: FPGA... 2 3. Creating a New Project... 2 4. Synthesis and Implementation of the Design... 11 5.

Sequential Logic: Clocks, Registers, etc.

ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit

Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs General Description The DM9368 is a 7-segment decoder driver incorporating input latches and constant current output circuits

4 Character 5x7 LED Matrix Display

Mini project report on 4 Character 5x7 LED Matrix Display Submitted by Agarwal Vikas, MTech II, CEDT K.Sreenivasulu M.E (Micro) II, CEDT CENTRE FOR ELECTRONICS DESIGN AND TECHNOLOGY INDIAN INSTITUTE OF

ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog

ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();

DEPARTMENT OF INFORMATION TECHNLOGY

DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453

MIDECO 64-outputs MIDI note decoder USER MANUAL. Roman Sowa 2012

MIDECO 64-outputs MIDI note decoder USER MANUAL Roman Sowa 2012 www.midi-hardware.com 1.Overview Thank you for choosing MIDECO as your new MIDI-to-digital converter. This short manual will guide you through

ECE 451 Verilog Exercises. Sept 14, 2007. James Barnes (James.Barnes@colostate.edu)

ECE 451 Verilog Exercises Sept 14, 2007 James Barnes (James.Barnes@colostate.edu) Organization These slides give a series of self-paced exercises. Read the specification of each exercise and write your

RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition

RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston

Controlling a Dot Matrix LED Display with a Microcontroller

Controlling a Dot Matrix LED Display with a Microcontroller By Matt Stabile and programming will be explained in general terms as well to allow for adaptation to any comparable microcontroller or LED matrix.

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

Registers & Counters

Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multi-bit storage devices. Introduce counters by adding logic to registers implementing

ELEC 2210 - EXPERIMENT 1 Basic Digital Logic Circuits

Objectives ELEC - EXPERIMENT Basic Digital Logic Circuits The experiments in this laboratory exercise will provide an introduction to digital electronic circuits. You will learn how to use the IDL-00 Bit

DDS. 16-bit Direct Digital Synthesizer / Periodic waveform generator Rev. 1.4. Key Design Features. Block Diagram. Generic Parameters.

Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core 16-bit signed output samples 32-bit phase accumulator (tuning word) 32-bit phase shift feature Phase resolution of 2π/2

Pulse Width Modulation (PWM) LED Dimmer Circuit. Using a 555 Timer Chip

Pulse Width Modulation (PWM) LED Dimmer Circuit Using a 555 Timer Chip Goals of Experiment Demonstrate the operation of a simple PWM circuit that can be used to adjust the intensity of a green LED by varying

Figure 8-1 Four Possible Results of Adding Two Bits

CHPTER EIGHT Combinational Logic pplications Thus far, our discussion has focused on the theoretical design issues of computer systems. We have not yet addressed any of the actual hardware you might find

A Digital Timer Implementation using 7 Segment Displays

A Digital Timer Implementation using 7 Segment Displays Group Members: Tiffany Sham u2548168 Michael Couchman u4111670 Simon Oseineks u2566139 Caitlyn Young u4233209 Subject: ENGN3227 - Analogue Electronics

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting

DIGITAL-TO-ANALOGUE AND ANALOGUE-TO-DIGITAL CONVERSION

DIGITAL-TO-ANALOGUE AND ANALOGUE-TO-DIGITAL CONVERSION Introduction The outputs from sensors and communications receivers are analogue signals that have continuously varying amplitudes. In many systems

Lab 1: Introduction to Xilinx ISE Tutorial

Lab 1: Introduction to Xilinx ISE Tutorial This tutorial will introduce the reader to the Xilinx ISE software. Stepby-step instructions will be given to guide the reader through generating a project, creating

Upon completion of unit 1.1, students will be able to

Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation

(Refer Slide Time: 00:01:16 min)

Digital Computer Organization Prof. P. K. Biswas Department of Electronic & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Lecture No. # 04 CPU Design: Tirning & Control

MAX II ISP Update with I/O Control & Register Data Retention

MAX II ISP Update with I/O Control & Register Data Retention March 2006, ver 1.0 Application Note 410 Introduction MAX II devices support the real-time in-system mability (ISP) feature that allows you

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits

RUTGERS UNIVERSITY Department of Electrical and Computer Engineering 14:332:233 DIGITAL LOGIC DESIGN LABORATORY

RUTGERS UNIVERSITY Department of Electrical and Computer Engineering 14:332:233 DIGITAL LOGIC DESIGN LABORATORY Fall 2012 Contents 1 LABORATORY No 1 3 11 Equipment 3 12 Protoboard 4 13 The Input-Control/Output-Display

CHAPTER 3 Boolean Algebra and Digital Logic

CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits

Below is a diagram explaining the data packet and the timing related to the mouse clock while receiving a byte from the PS-2 mouse:

PS-2 Mouse: The Protocol: For out mini project we designed a serial port transmitter receiver, which uses the Baud rate protocol. The PS-2 port is similar to the serial port (performs the function of transmitting

Karnaugh Maps (K-map) Alternate representation of a truth table

Karnaugh Maps (K-map) lternate representation of a truth table Red decimal = minterm value Note that is the MS for this minterm numbering djacent squares have distance = 1 Valuable tool for logic minimization

16-bit ALU, Register File and Memory Write Interface

CS M152B Fall 2002 Project 2 16-bit ALU, Register File and Memory Write Interface Suggested Due Date: Monday, October 21, 2002 Actual Due Date determined by your Lab TA This project will take much longer

A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital

Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas

Take-Home Exercise Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count

LAB4: Audio Synthesizer

UC Berkeley, EECS 100 Lab LAB4: Audio Synthesizer B. Boser NAME 1: NAME 2: The 555 Timer IC SID: SID: Inductors and capacitors add a host of new circuit possibilities that exploit the memory realized by

VHDL Test Bench Tutorial

University of Pennsylvania Department of Electrical and Systems Engineering ESE171 - Digital Design Laboratory VHDL Test Bench Tutorial Purpose The goal of this tutorial is to demonstrate how to automate

ASYNCHRONOUS COUNTERS

LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

Traffic Light Controller. Digital Systems Design. Dr. Ted Shaneyfelt

Traffic Light Controller Digital Systems Design Dr. Ted Shaneyfelt December 3, 2008 Table of Contents I. Introduction 3 A. Problem Statement 3 B. Illustration 3 C. State Machine 3 II. Procedure 4 A. State

Digital Fundamentals

Digital Fundamentals Tenth Edition Floyd Chapter 1 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved Analog Quantities Most natural quantities that we see

AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD)

AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD) Samuel Lakeou, University of the District of Columbia Samuel Lakeou received a BSEE (1974) and a MSEE (1976)

Digital Systems Laboratory

Eskişehir Osmangazi University Digital Systems Laboratory Rev 3.01 February 2011 LIST OF EXPERIMENTS 1. BINARY AND DECIMAL NUMBERS 2. DIGITAL LOGIC GATES 3. INTRODUCTION TO LOGICWORKS 4. BOOLEAN ALGEBRA

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.

Cascaded Counters Page 1 Mod-N Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A mod-n counter has N states Counts from 0 to N-1 then rolls

Digital Fundamentals

Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence

Step Response of RC Circuits

Step Response of RC Circuits 1. OBJECTIVES...2 2. REFERENCE...2 3. CIRCUITS...2 4. COMPONENTS AND SPECIFICATIONS...3 QUANTITY...3 DESCRIPTION...3 COMMENTS...3 5. DISCUSSION...3 5.1 SOURCE RESISTANCE...3

Jianjian Song LogicWorks 4 Tutorials (5/15/03) Page 1 of 14

LogicWorks 4 Tutorials Jianjian Song Department of Electrical and Computer Engineering Rose-Hulman Institute of Technology March 23 Table of Contents LogicWorks 4 Installation and update...2 2 Tutorial

More Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset.

More Verilog 8-bit Register with Synchronous Reset module reg8 (reset, CLK, D, Q); input reset; input [7:0] D; output [7:0] Q; reg [7:0] Q; if (reset) Q = 0; else Q = D; module // reg8 Verilog - 1 Verilog

PLL frequency synthesizer

ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 4 Lab 4: PLL frequency synthesizer 1.1 Goal The goals of this lab exercise are: - Verify the behavior of a and of a complete PLL - Find capture

Life Cycle of a Memory Request. Ring Example: 2 requests for lock 17

Life Cycle of a Memory Request (1) Use AQR or AQW to place address in AQ (2) If A[31]==0, check for hit in DCache Ring (3) Read Hit: place cache word in RQ; Write Hit: replace cache word with WQ RDDest/RDreturn

Objectives: Part 1: Build a simple power supply. CS99S Laboratory 1

CS99S Laboratory 1 Objectives: 1. Become familiar with the breadboard 2. Build a logic power supply 3. Use switches to make 1s and 0s 4. Use LEDs to observe 1s and 0s 5. Make a simple oscillator 6. Use

The 104 Duke_ACC Machine

The 104 Duke_ACC Machine The goal of the next two lessons is to design and simulate a simple accumulator-based processor. The specifications for this processor and some of the QuartusII design components

EMERGING DISPLAY CUSTOMER ACCEPTANCE SPECIFICATIONS 16290(LED TYPES) EXAMINED BY : FILE NO. CAS-10251 ISSUE : JUL.03,2001 TOTAL PAGE : 7

EXAMINED BY : FILE NO. CAS-10251 EMERGING DISPLAY ISSUE : JUL.03,2001 APPROVED BY: TECHNOLOGIES CORPORATION TOTAL PAGE : 7 VERSION : 1 CUSTOMER ACCEPTANCE SPECIFICATIONS MODEL NO. : 16290(LED TYPES) FOR

Hexadecimal and Numeric Indicators. Technical Data 5082-7300 5082-7302 5082-7304 5082-7340

H Hexadecimal and Numeric Indicators Technical Data 5082-7300 5082-7302 5082-7304 5082-7340 Features Numeric 5082-7300/-7302 0-9, Test State, Minus Sign, Blank States Decimal Point 7300 Right Hand D.P.

Flip-Flops, Registers, Counters, and a Simple Processor

June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number

A Lesson on Digital Clocks, One Shots and Counters

A Lesson on Digital Clocks, One Shots and Counters Topics Clocks & Oscillators LM 555 Timer IC Crystal Oscillators Selection of Variable Resistors Schmitt Gates Power-On Reset Circuits One Shots Counters

BINARY CODED DECIMAL: B.C.D.

BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.

A Lesson on Digital Clocks, One Shots and Counters

A Lesson on Digital Clocks, One Shots and Counters Topics Clocks & Oscillators LM 555 Timer IC Crystal Oscillators Selection of Variable Resistors Schmitt Gates Power-On Reset Circuits One Shots Counters

FORDHAM UNIVERSITY CISC 3593. Dept. of Computer and Info. Science Spring, 2011. Lab 2. The Full-Adder

FORDHAM UNIVERSITY CISC 3593 Fordham College Lincoln Center Computer Organization Dept. of Computer and Info. Science Spring, 2011 Lab 2 The Full-Adder 1 Introduction In this lab, the student will construct

Basic Pulse Width Modulation

EAS 199 Fall 211 Basic Pulse Width Modulation Gerald Recktenwald v: September 16, 211 gerry@me.pdx.edu 1 Basic PWM Properties Pulse Width Modulation or PWM is a technique for supplying electrical power

GLOLAB Universal Telephone Hold

GLOLAB Universal Telephone Hold 1 UNIVERSAL HOLD CIRCUIT If you have touch tone telephone service, you can now put a call on hold from any phone in the house, even from cordless phones and phones without

SOLID-STATE HEXADECIMAL DISPLAY WITH INTEGRAL TTL CIRCUIT TO ACCEPT, STORE, AND DISPLAY 4-BIT BINARY DATA 0.300-Inch (7,62-mm) Character Height Internal TTL MSI Chip With Latch, Decoder, High Brightness

Timer A (0 and 1) and PWM EE3376

Timer A (0 and 1) and PWM EE3376 General Peripheral Programming Model Each peripheral has a range of addresses in the memory map peripheral has base address (i.e. 0x00A0) each register used in the peripheral

Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots

Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots Registers As you probably know (if you don t then you should consider changing your course), data processing is usually

EC313 - VHDL State Machine Example

EC313 - VHDL State Machine Example One of the best ways to learn how to code is seeing a working example. Below is an example of a Roulette Table Wheel. Essentially Roulette is a game that selects a random

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science. 6.002 Electronic Circuits Spring 2007

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.002 Electronic Circuits Spring 2007 Lab 4: Audio Playback System Introduction In this lab, you will construct,

Table 1 Comparison of DC, Uni-Polar and Bi-polar Stepper Motors

Electronics Exercise 3: Uni-Polar Stepper Motor Controller / Driver Mechatronics Instructional Laboratory Woodruff School of Mechanical Engineering Georgia Institute of Technology Lab Director: I. Charles

Robot Board Sub-System Testing. Abstract. Introduction and Theory. Equipment. Procedures. EE 101 Spring 2006 Date: Lab Section # Lab #6

EE 101 Spring 2006 Date: Lab Section # Lab #6 Name: Robot Board Sub-System Testing Partner: No Lab partners this time! Abstract The ECEbot robots have a printed circuit board (PCB) containing most of the

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013

DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,

Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

TV Remote Controller Decoder

TV Remote Controller Decoder The TV Remote Controller Decoder kit is available, free to schools, to use in their Wireless Technology Curriculum. Former ARRL Education & Technology Program Coordinator,

Gates, Circuits, and Boolean Algebra

Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks

3.Basic Gate Combinations

3.Basic Gate Combinations 3.1 TTL NAND Gate In logic circuits transistors play the role of switches. For those in the TTL gate the conducting state (on) occurs when the baseemmiter signal is high, and