S6A SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

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1 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD June 2 Ver Contents in this document are subject to change without notice No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team

2 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD INTRODUCTION S6A69 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology It can display, 2-line with 5 x 8 or 5 x dots format FUNCTIONS Character type dot matrix LCD driver & controller Internal driver: 6 common and 4 segment signal output Easy interface with 4-bit or 8-bit MPU Display character pattern : 5 x 8 dots format (24 kinds), 5 x dots format (32 kinds) The special character pattern can be programmable by Character Generator RAM directly A customer character pattern can be programmable by mask option It can drive a maximum 8 characters by using the S6A65 or S6A267 externally Various instruction functions Automatic power on reset FEATURES Internal Memory - Character Generator ROM (CGROM):,8 bits (24 characters x 5 x 8 dot) & ( 32 characters x 5 x dot) - Character Generator RAM (CGRAM): 64 8 bits (8 characters 5 8 dot) - Display Data RAM (DDRAM): 8 x 8 bits (8 characters max) Low Power Operation - Power supply voltage range: 27 to 55V (V DD ) - LCD drive voltage range: 3 to 3V (V DD - V5) CMOS process Programmable duty cycle: /8, /, /6 Internal oscillator with an external resistor Low power consumption Bare chip available 2

3 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 BLOCK DIAGRAM VDD GND V V2 V3 V4 V5 Busy Flag Character Generator ROM (CGROM) 8 bits Parallel to Serial Data Conversion Circuit 5 5 Character Generator RAM (CGRAM) 52 bits Cursor & Blink Controller R/W RS E DB- DB3 DB4- DB7 Input/ Output Buffer 8 8 Data Register (DR) Instruction Register (IR) Instruction Decoder (ID) Display Data RAM (DDRAM) 8x8 bits 4-bit Shift Register 4-bit Latch Circuit Segment Driver 4 S-S4 D OSC OSC2 Timing Generator Circuit 7 Address Counter 6-bit 7 Common 6 Shift Driver Register C-C6 CLK CLK2 M 3

4 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD CONFIGURATION S22 S2 S2 S9 S8 S7 S6 S5 S4 S3 S2 S S S9 S8 S7 S6 S5 S4 S3 S2 S GND OSC Y (, ) X Chip size: Pad size: Unit: µm S6A OSC2 V V2 V3 V4 V5 CLK CLK2 VDD M D RS R/W E DB DB S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 C6 C5 C4 C3 C2 C C C9 C8 C7 C6 C5 C4 C3 C2 C DB7 DB6 DB5 DB4 DB3 DB2 4

5 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 PAD CENTER COORDINATES Unit: um PAD PAD COORDINATE PAD PAD COORDINATE PAD PAD COORDINATE NUM NAME X Y NUM NAME X Y NUM NAME X Y S V C S V C S V C S CLK C S CLK C S VDD C S M C S D C S RS S S R/W S S E S S DB S S DB S S DB S S DB S S DB S S DB S S DB S S DB S S C S S C S S C S GND C S OSC C S OSC C S V C S V C

6 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD PIN DESCRIPTION PIN No I/O NAME DESCRIPTION INTERFACE VDD GND V - V5 S - S , Supply Voltage Supply Voltage for logical circuit (+3V ± %,+5V ±%) V (GND) Bias voltage level for LCD driving Power Supply O Segment output Segment signal output for LCD drive LCD C - C O Common output Common signal output for LCD drive LCD OSC 24 I Oscillator OSC2 25 O Oscillator CLK 3 O CLK2 32 O M 34 O D 35 O Extension driver Latch clock Extension driver Shift clock Alternated signal for LCD driver output Display data interface RS 36 I Register select R/W 37 I Read/Write When use internal oscillator, connect external Rf resistor If external clock is used, connect it to OSC extension driver latch clock extension driver shift clock Outputs the alternating signal to convert LCD driver waveform to AC Outputs extension driver data (the 4th dot's data) Used as register selection input When RS = "High", Data register is selected When RS = "Low", Instruction register is selected Used as read/write selection input When R/W = "High", read operation When R/W = "Low", write operation External Resistor/ Oscillator OSC Extension driver Extension driver Extension driver E 38 I Read/write enable Read/write enable signal MPU DB- DB DB4- DB When 8-bit bus mode, used as low order bidirectional data bus In 4-bit bus mode open these pins I/O Data bus -7 When 8-bit bus mode, used as high order bidirectional data bus In case of 4- bit bus mode, used as both high and low order DB7 is used for Busy Flag output MPU MPU MPU MPU 6

7 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 FUNCTION DESCRIPTION System Interface This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus 4-bit bus and 8-bit bus is selected by DL bit in the instruction register During read or write operation, two 8-bit registers are used one is data register (DR), the other is instruction register(ir) The data register(dr) is used as temporary data storage place for being written into or read from DDRAM/CGRAM The target RAM is selected by RAM address setting instruction Each internal operation, reading from or writing into RAM, is done automatically So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically The instruction register (IR) is used only to store instruction code transferred from MPU MPU cannot use it to read instruction data To select register, use RS input pin in 4-bit/8-bit bus mode Table Various Kinds of Operations according to RS and R/W Bits RS R/W Operation L L Instruction Write operation (MPU writes Instruction code into IR) L H Read Busy Flag (DB7) and address counter (DB - DB6) H L Data Write operation (MPU writes data into DR) H H Data Read operation (MPU reads data from DR) Busy Flag (BF) When BF = "High", it indicates that the internal operation is being processed So during this time the next instruction cannot be accepted BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port Before executing the next instruction, be sure that BF is not High Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by When RS = "Low" and R/W = "High", AC can be read through DB - DB6 ports 7

8 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD Display Data RAM (DDRAM) DDRAM stores display data of maximum 8 x 8 bits (8 characters) DDRAM address is set in the address counter (AC) as a hexadecimal number (refer to Figure) MSB AC6 AC5 AC4 AC3 AC2 AC AC LSB Figure DDRAM Address ) -line Display In case of line display, the address range of DDRAM is H - 4FH Extension driver will be used Fig-2 shows the example that 4 segment extension driver is added Display position COM COM SEG S6A69 SEG A B C D E F SEG Extension driver (4 SEG) SEG4 SEG Extension driver (4 SEG) SEG4 DDRAM Address COM COM SEG S6A69 SEG A B C D E F SEG Extension driver (4 SEG) SEG4 SEG Extension driver (4 SEG) SEG4 (After Shift Left) COM COM8 4F A B C D E F SEG S6A69 SEG4 SEG Extension driver (4 SEG) SEG4 SEG Extension driver (4 SEG) SEG4 (After Shift Right) Figure 2 -line x 24 Character Display with 4 Segment Extension Driver 8

9 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 2) 2-line Display In case of 2 line display, the address range of DDRAM is H - 27H, 4H - 67H Extension driver will be used Figure 3 shows the example that 4 segment extension driver is added Display position A B C D E F DDRAM Address A 4B 4C 4D 4E 4F SEG S6A69 SEG4 SEG Extension driver (4 SEG) SEG4 SEG Extension driver (4 SEG) SEG A B C D E F A 4B 4C 4D 4E 4F SEG S6A69 SEG4 SEG Extension driver (4 SEG) SEG4 SEG Extension driver (4 SEG) SEG4 (After Shift Left) A B C D E F A 4B 4C 4D 4E 4F SEG S6A69 SEG4 SEG Extension driver (4 SEG) SEG4 SEG Extension driver (4 SEG) SEG4 Figure 3 2-line x 24 Character Display with 4 Segment Extension Driver 9

10 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD CGROM (Character Generator ROM) CGROM has a 5 x 8 dots 24 characters pattern and a 5 x dots 32 characters pattern CGROM has 24 character patterns of 5 x 8 dots, and 32 character patterns of 5 x dots CGRAM (Character Generator RAM) CGRAM has up to 5 8 dot, 8 characters By writing font data to CGRAM, user defined characters can be used (refer to Table 5) Timing Generation Circuit Timing generation circuit generates clock signals for the internal operations LCD Driver Circuit LCD Driver circuit has 6 common and 4 segment signals for LCD driving Data from CGRAM/CGROM is transferred to 4 bit segment latch serially, and then it is stored to 4 bit shift latch When each common is selected by 6 bit common register, segment data also output through segment driver from 4 bit segment latch In case of -line display mode, COM- COM8 have /8 duty or COM COM have /duty, and in 2-line mode, COM - COM6 have /6 duty ratio Cursor / Blink Control Circuit It controls cursor/blink ON / OFF at cursor position

11 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 Table 5 Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) Character Code (DDRAM data) CGRAM Address CGRAM Data Pattern D7 D6 D5 D4 D3 D2 D D A5 A4 A3 A2 A A P7 P6 P5 P4 P3 P2 P P number x x x x x x x x Pattern Pattern 8

12 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD INSTRUCTION DESCRIPTION Outline To overcome the speed difference between internal clock of S6A69 and MPU clock, S6A69 performs internal operation by storing control information to IR or DR The internal operation is determined according to the signal from MPU, composed of read/write and data bus (refer to Table 5 ) Instruction can be divided largely four kinds, () S6A69 function set instructions ( set display methods, set data length, etc) (2) Address set instructions to internal RAM (3) Data transfer instructions with internal RAM (4) Others The address of internal RAM is automatically increased or decreased by NOTE: During internal operation, Busy Flag (DB7) is read High Busy Flag check must precede the next instruction When an MPU program with checking the Busy Flag (DB7) is made, it must be necessary /2 fosc for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW" Contents ) Clear Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Clear all the display data by writing "2H" (space code) to all DDRAM address, and set DDRAM address to "H" into AC (address counter) Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display Make entry mode increment (I/D = "") 2) Return Home RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB - Return Home is cursor return home instruction Set DDRAM address to "H" into the address counter Return cursor to its original site and return display to its original status, if shifted Contents of DDRAM does not change 2

13 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 3) Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB I/D SH Set the moving direction of cursor and display I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by * CGRAM operates the same as DDRAM, when read from or write to CGRAM SH: Shift of entire display When DDRAM read (CGRAM read/write) operation or SH = "Low", shift of entire display is not performed If SH = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "" : shift left, I/D = "" : shift right) 4) Display ON / OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB D C B Control display/cursor/blink ON/OFF bit register D : Display ON/OFF Control Bit When D = "High", entire display is turned on When D = "Low", display is turned off, but display data is remained in DDRAM C : Cursor ON/OFF Control Bit When C = "High", cursor is turned on When C = "Low", cursor is disappeared in current display, but I/D register remains its data B : Cursor Blink ON/OFF Control Bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position When B = "Low", blink is off 5) Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB S/C R/L - - Shifting of right/left cursor position or display without writing or reading of display data This instruction is used to correct or search display data (Refer to table 6) During 2-line mode display, cursor moves to the 2nd line after the 4th digit of the st line Note that display shift is performed simultaneously in all the lines When displayed data is shifted repeatedly, each line is shifted individually When display shift is performed, the contents of the address counter are not changed 3

14 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD Table 6 Shift Patterns According to S/C and R/L Bits S/C R/L Operation Shift cursor to the left, AC is decreased by Shift cursor to the right, AC is increased by Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display 6) Function Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB DL N F - - DL : Interface Data Length Control Bit When DL = "High", it means 8-bit bus mode with MPU When DL = "Low", it means 4-bit bus mode with MPU So to speak, DL is a signal to select 8-bit or 4-bit bus mode When 4-bit bus mode, it needs to transfer 4-bit data by two times N : Display Line Number Control Bit When N = "Low", it means -line display mode When N = "High", 2-line display mode is set F : Display Font Type Control Bit When F = "Low", it means 5 8 dots format display mode When F = "High", 5 dots format display mode 7) Set CGRAM Address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB AC5 AC4 AC3 AC2 AC AC Set CGRAM address to AC This instruction makes CGRAM data available from MPU 8) Set DDRAM Address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB AC6 AC5 AC4 AC3 AC2 AC AC Set DDRAM address to AC This instruction makes DDRAM data available from MPU When -line display mode (N = ), DDRAM address is from "H" to "4FH" In 2-line display mode (N = ), DDRAM address in the st line is from "H" to "27H", and DDRAM address in the 2nd line is from "4H" to "67H" 9) Read Busy Flag & Address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB BF AC6 AC5 AC4 AC3 AC2 AC AC This instruction shows whether S6A69 is in internal operation or not If the resultant BF is High, it means the internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be performed In this instruction you can read also the value of address counter 4

15 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 ) Write Data to RAM RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB D7 D6 D5 D4 D3 D2 D D Write binary 8-bit data to DDRAM/CGRAM The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction (DDRAM address set, CGRAM address set) RAM set instruction can also determine the AC direction to RAM After write operation, the address is automatically increased/decreased by, according to the entry mode ) Read Data from RAM RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB D7 D6 D5 D4 D3 D2 D D Read binary 8-bit data from DDRAM/CGRAM The selection of RAM is set by the previous address set instruction If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register After read operation address counter is automatically increased/decreased by according to the entry mode After CGRAM read operation, display shift may not be executed correctly NOTE: In case of RAM write operation, after this AC is increased/decreased by like read operation In this time, AC indicates the next address position, but you can read only the previous data by read instruction 5

16 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD Table 7 Instruction Table Instruction Instruction Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Description Instruction Code Execution time (fsoc=27khz) Clear Display Return Home X Write "2H" to DDRAM and set DDRAM address to "H" from AC Set DDRAM address to "H" from AC and return cursor to its original position if shifted The contents of DDRAM are not changed 53ms 53ms Entry Mode Set I/D SH Assign cursor moving direction and make shift of entire display enable 39µs Display ON/OFF Control D C B Set display(d), cursor(c), and blinking of cursor(b) on/off control bit 39µs Cursor or Display Shift S/C R/L X X Set cursor moving and display shift control bit, and the direction, without changing DDRAM data 39µs Function Set DL N F X X Set interface data length (DL : 4- bit/8-bit), numbers of display line (N : -line/2-line), display font type(f : 5 X 8 dots/ 5 X dots) 39µs Set CGRAM Address AC5 AC4 AC3 AC2 AC AC Set CGRAM address in address counter 39µs Set DDRAM Address AC6 AC5 AC4 AC3 AC2 AC AC Set DDRAM address in address counter 39µs Read Busy Flag and Address BF AC6 AC5 AC4 AC3 AC2 AC AC Whether during internal operation or not can be known by reading BF The contents of address counter can also be read µs Write Data to RAM D7 D6 D5 D4 D3 D2 D D Write data into internal RAM (DDRAM/CGRAM) 43µs Read Data from RAM D7 D6 D5 D4 D3 D2 D D Read data from internal RAM (DDRAM/CGRAM) 43µs NOTE: When an MPU program with checking the Busy Flag (DB7) is made, it must be necessary /2 fosc is necessary for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW" 6

17 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 INTERFACE WITH MPU ) Interface with 8-bit MPU When interfacing data length is 8-bit, transfer is performed at a time through 8 ports, from DB to DB7 Example of timing sequence is shown below RS R/W E Internal signal Internal Operation DB7 DATA Busy Busy No Busy DATA Instruction Busy Flag Check Busy Flag Check Busy Flag Check Instruction Figure 4 Example of 8-bit Bus Mode Timing Diagram 7

18 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) Interface with 4-bit MPU When interfacing data length is 4-bit, only 4 ports, from DB4 to DB7, are used as data bus At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-bit (in case of 8-bit bus mode, the contents of DB - DB3) are transferred So transfer is performed by two times Busy Flag outputs "High" after the second transfer are ended Example of timing sequence is shown below RS R/W E Internal signal DB7 D7 Internal Operation No D3 AC3 Busy AC3 D7 D3 Busy Instruction Busy Flag Check Busy Flag Check Instruction Figure 5 Example of 4-bit Bus Mode Timing Diagram 8

19 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 APPLICATION INFORMATION ACCORDING TO LCD PANEL ) LCD Panel: 8 Character -line Character Format; 5 7 dots + -cursor line (/4 Bias, /8 Duty) C C7 C8 S6A69 S S S38 S39 S4 2) LCD Panel: 8 Character -line Character Format; 5 dots + cursor line (/4 Bias, / Duty) C C C S6A69 S S S38 S39 S4 9

20 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD 3) LCD Panel: 8 Character 2-line Character Format; 5 7 dots + -cursor line (/5 Bias, /6 Duty) C C7 C8 S6A69 C9 C5 C6 S S S38 S39 S4 2

21 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 4) LCD Panel: 6 Character -line Character Format; 5 7 dots + -cursor line (/5 Bias, /6 Duty) C C7 C8 S S6A69 S S39 S4 C9 C6 2

22 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD 5) LCD Panel: 4 Character 2-line Character Format; 5 7 dots + -cursor line (/4 Bias, /8 Duty) S S S8 S9 S2 C C7 S6A69 C8 S2 S3 S38 S39 S4 22

23 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 6) APPLICATION CIRCUIT LCD Panel C-C6 S-S4 D OSC OSC2 S6A69 DL FCS SHL SHL2 VSS VDD SC-S4C S6A65 DL2 DL DR2 CL CL2 M V6 V5 V4 V3 V2 V VEE DL FCS SHL SHL2 VSS VDD SC-S4C S6A65 DL2 DL DR2 CL CL2 M V6 V5 V4 V3 V2 V VEE DL FCS SHL SHL2 VSS VDD SC-S4C S6A65 DL2 DL DR2 CL CL2 M V6 V5 V4 V3 V2 V VEE VSS M CLK CLK2 VDD V V2 V3 V4 V5 DB-DB7 To MPU GND or Other voltage V V2 V3 V4 V5 VD VLCD (/5 bias) NOTE: When S6A65 is externally connected to the S6A69, you can increase the number of display digits up to 8 characteristics 23

24 S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD BIAS VOLTAGE DIVIDE CIRCUIT ) /4 bias, /8 or / duty 2) /5 bias, /6 duty VDD R R R R GND or Other voltage VDD V V2 S6A69 V3 V4 V5 VDD R R R R R GND or Other voltage VDD V V2 S6A69 V3 V4 V5 24

25 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 INITIALIZING When the power is turned on, S6A69 is initialized automatically by power on reset circuit During the initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of initialization () Display Clear instruction: Write "2H" to all DDRAM (2) Set Functions instruction DL = : 8-bit bus mode N = : 2-line display mode F = : 5 X 8 font type (3) Control Display ON/OFF instruction D = : Display OFF C = : Cursor OFF B = : Blink OFF (4) Set Entry Mode instruction I/D = : Increment by SH = : No entire display shift FRAME FREQUENCY Programmable Driving Method by the same font mask option: Display waveform A-Type, B-Type ) /8 Duty Cycle A) A-Type Waveform -line selection period VDD V COM V4 V5 B) B-Type Waveform VDD V COM V4 V5 Frame Frame Line selection period One Frame Frame frequency = 4 clocks = 4 x 8 x 37µs = 85 µs = 9 ms ( clock = 37 µs, fosc = 27kHz) = / 9ms = 843Hz 25

26 S6A69 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) / duty cycle A) A-type Waveform -line selection period VDD V COM V4 V5 B) B-type Waveform VDD V COM V4 V5 Frame Frame Line selection period One Frame Frame frequency = 4 clocks = 4 x x 37µs = 63µs = 63ms ( clock = 37µs, fosc = 27kHz) = / 63 ms = 64 Hz 26

27 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 3) /6 duty cycle A) A-type Waveform -line selection period VDD V COM V4 V5 B) B-type Waveform VDD V COM V4 V5 Frame Frame Line selection period One Frame Frame frequency = 2 clocks = 2 x 6 x 37µs = 85 µs = 9 ms ( clock = 37µs, fosc = 27kHz) = / 9ms = 843Hz 27

28 S6A69 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INITIALIZING BY INSTRUCTION ) 8-bit Interface Mode (Condition: fosc = 27kHz) Power On Wait for more than 3ms after VDD rises to 45 V Wait for more than 4ms after VDD rises to 27 V Function Set N -line mode 2-line mode RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB N F X X F Display OFF Display ON Wait for more than 39µs Display ON/OFF Control D Display OFF Display ON RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB D C B C Cursor OFF Cursor ON Wait for more than 39µs B Blink OFF Blink ON Display Clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Wait for more than 53sms Entry Mode Set I/D Decrement mode Increment mode RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB I/D SH SH Entire shift off Entire shift on Initialization End 28

29 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 2) 4-bit Interface Mode (Condition: fosc = 27kHz) Power On Wait for more than 3ms after VDD rises to 45 V Wait for more than 4ms after VDD rises to 27 V D/L 4-bit mode 8-bit mode Function Set N -line mode 2-line mode RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB DL X X X X X X X X F Display off Display on N F X X X X X X Wait for more than 39µs D Display off Display on Display ON/OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X C Cursor off Cursor on D C B X X X X B Blink off Blink on Wait for more than 39µs Display Clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X X X X X Wait for more than 53ms Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB I/D Decrement mode Increment mode X X X X SH Entire shift off I/D SH X X X X Entire shift on Initialization End 29

30 S6A69 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD MAXIMUM ABSOLUTE LIMIT Maximum Absolute Power Ratings Characteristic Symbol Unit Value Power Supply Voltage V DD V -3 to +7 LCD Drive Voltage V LCD V V DD -5 to V DD +3 Input Voltage V IN V -3 to V DD + 3 Voltage greater than above may damage the circuit (V DD V V2 V3 V4 V5) Temperature Characteristics Characteristic Symbol Unit Value Operating Temperature T OPR C -3 to +85 Storage Temperature T STG C -55 to +25 3

31 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 ELECTRICAL CHARACTERISTICS DC Characteristics (V DD = 45V to 55V, Ta = -3 to +85 C) Characteristic Symbol Condition Min Typ Max Unit Operating Voltage V DD V Operating Current I DD external clock (V DD = 5V, Internal oscillation or fosc = 27kHz) Input Voltage () ma V IH V DD (except OSC) V IL V Input Voltage (2) V IH2 - V DD - - V DD (OSC) V IL V Output Voltage () V OH I OH = -25mA (DB to DB7) V OL I OL = 2mA Output Voltage (2) V OH2 I O = -4µA 9V DD - - (except DB to DB7) V OL2 I O = 4µA - - V DD V Voltage Drop Vd COM - - I O = ±ma - - Vd SEG Input Leakage Current I LKG V IN = V to V DD - - Input Low Current I IL V IN = V, V DD = 5V (pull up) Internal Clock (external Rf) External Clock f OSC Rf = 9kΩ ±2% (V DD = 5V) khz f OSC khz t R, t F µa duty % LCD Driving Voltage V LCD V DD -V5 (/5, /4 bias) 3-3 V V V µa 3

32 S6A69 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD DC Characteristics (V DD = 27V to 45V, Ta = -3 to +85 C) Characteristic Symbol Condition Min Typ Max Unit Operating Voltage V DD V Operating Current I DD external clock (V DD = 3V, Internal oscillation or fosc = 27kHz) ma Input Voltage () V IH - 7 V DD - V DD (except OSC) V IL V Input Voltage (2) V IH2-7V DD - V DD (OSC) V IL V DD V Output Voltage () V OH I OH = -ma 75 V DD - - (DB to DB7) V OL I OL = ma V DD V Output Voltage (2) (except DB to DB7) Voltage Drop V OH2 I O = -4µA 8V DD - - V OL2 I O = 4µA - - 2V DD V Vd COM - - I O = ± ma - - Vd SEG Input Leakage Current I LKG V IN = V V DD - - Input Low Current I IL V IN = V, V DD = 3V (pull up) Internal Clock (external Rf) External Clock f OSC Rf = 75kΩ ±2% (V DD = 3V) khz f OSC khz t R, t F µs duty % LCD Driving Voltage V LCD V DD -V5 (/5, /4 bias) 3-3 V V µa NOTE: LCD Driving Voltage Power Duty /8, / Duty /6 Duty Bias /4 Bias /5 Bias V DD V DD V DD V V DD - V LCD /4 V DD - V LCD /5 V 2 V DD - V LCD /2 V DD - 2V LCD /5 V 3 V DD - V LCD /2 V DD - 3V LCD /5 V 4 V DD - 3V LCD /4 V DD - 4V LCD /5 V 5 V DD - V LCD V DD - V LCD 32

33 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 AC Characteristics (V DD = 45 to 55V, Ta = -3 to +85 C) Mode Characteristics Symbol Min Typ Max Unit E Cycle Time tc E Rise / Fall Time t R, t F E Pulse Width (High, Low) tw Write Mode R/W and RS Setup Time tsu (refer to Figure-6) R/W and RS Hold Time t H - - ns Data Setup Time tsu Data Hold Time t H2 - - E Cycle Time tc E Rise / Fall Time t R, t F E Pulse Width (High, Low) tw Read Mode R/W and RS Setup Time tsu (refer to Figure-7) R/W and RS Hold Time t H - - ns Data Output Delay Time td Data Hold Time tdh (V DD = 27 to 45V, Ta = -3 to +85 C) Mode Characteristic Symbol Min Typ Max Unit E Cycle Time tc - - E Rise / Fall Time t R, t F E Pulse Width (High, Low) tw Write Mode R/W and RS Setup Time tsu (refer to Figure-6) R/W and RS Hold Time t H ns Data Setup Time tsu Data Hold Time t H2 - - E Cycle Time tc - - E Rise / Fall Time t R, t F E Pulse Width (High, Low) tw Read Mode R/W and RS Setup Time tsu (refer to Figure-7) R/W and RS Hold Time t H ns Data Output Delay Time t D Data Hold Time t DH

34 S6A69 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD (V DD = 27 to 45V, Ta = -3 to +85 C) Mode Characteristic Symbol Min Typ Max Unit Interface Mode with Extension Driver (refer to Figure-8) Clock Pulse Width (High, Low) tw 8 - Clock Rise / Fall Time t R, t F Clock Setup Time tsu Data Setup Time tsu Data Hold Time t DH M Delay Time t DM ns RS VIH VIL tsu th R/W VIL VIL tw th E DB-DB7 tr VIH VIL VIH VIL tf tsu2 th2 Valid Data tc VIH VIL VIL Figure 6 Write Mode Timing Diagram RS VIH VIL tsu th R/W VIH VIH tw th E tr VIH VIL td tdh tf VIL DB-DB7 VOH VOL Valid Data tc VOH VOL Figure 7 Read Mode Timing Diagram 34

35 6COM/4SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 tf CLK CLK2 tr VOL2 VOH2 VOH2 tw VOH2 tsu VOL2 tw VOH2 VOL2 tw D tsu2 tdh VOH2 VOL2 M VOL2 tdm Figure 8 Interface Mode with Extension Driver Timing Diagram 35

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