Quick Reference Card. Timing and Stack Verifier Supported Platforms. SCADE Suite 6.2.1
|
|
- Kenneth Garrison
- 7 years ago
- Views:
Transcription
1 Timing and Stack Verifier Supported Platforms SCADE Suite 6.2.1
2 About Timing and Stack Verifier supported platforms Timing and Stack Verifier Supported Platforms SCADE Suite Timing Verifier and SCADE Suite Stack Verifier are powered by AbsInt s ait/stackanalyzer. This reference card provides information on the main characteristics of the SCADE Suite Timing and Stack Verifiers for supported processor platforms. Contents 1. Timing Verifier Supported Platforms 3 PowerPC MPC5xx 3 PowerPC MPC55xx 3 PowerPC MPC603e 4 PowerPC MPC755s 5 TriCore 5 NEC V850 6 LEON2/ Stack Verifier Supported Platforms 7 All PowerPC (PPC) Family 7 TriCore 1766/1796/ NEC V850 Family 7 LEON2/3 7 Esterel Technologies - SCADE Suite 1-2
3 1. Timing Verifier Supported Platforms Timing Verifier supports the following platforms: PowerPC 1 MPC5xx 32-bit pipelined processor Supports single and double precision floating point operations Supports External Memory (up to 4 GB) Out-of-order execution, in-order completion MPC555: Core clock up to 40 MHz 448 KB Flash EEPROM Memory 26 KB of Static RAM MPC565: Core clock up to 56 MHz 1 MB of internal FLASH memory (divided into 2 blocks of 512 KB) 36 KB Static RAM PowerPC MPC55xx 32-bit pipelined processor In-order execution, in-order completion Supports scalar and vector single precision floating point operations Supports External Memory (up to 512 MB) MPC5553: Core clock up to 132 MHz 8 KB Unified Cache 1536 KB internal FLASH Memory 64 KB internal SRAM No support for external memory in 208 pin package Only 16-bit external memory bus in 324 pin package MPC5554: Core clock up to 132 MHz 32 KB Unified Cache 2 MB internal FLASH Memory 64 KB internal SRAM 1. IBM PowerPC (PPC) family Esterel Technologies - SCADE Suite 1-3
4 MPC5561: Core clock up to 132 MHz Supports VLE (16-bit Instructions) 32 KB Unified Cache 1 MB internal FLASH Memory 192 KB internal SRAM MPC5566: Core clock up to 144 MHz Supports VLE (16-bit Instructions) 32 KB Unified Cache 3 MB internal FLASH Memory 128 KB internal SRAM PowerPC MPC603e PowerPC603e core supporting external statically timed memory accessed via one of the three UPMs of the integrated memory controller operating in 60x bus compatible mode (as, e.g., present in the MPC8260, MPC8270 and MPC8280) 32bit pipelined processor out-of-order execution, in-order completion Supports single and double precision floating point operations Supports External Memory (up to 4 GB) 16 KB Instruction Cache (LRU replacement algorithm) 16 KB Data Cache (LRU replacement algorithm) 5 independent execution units (Integer unit, Load/Store unit, Floating-point unit, System register unit, Branch processing unit) 64-bit data bus and 32-bit address bus 1 level of speculative execution Esterel Technologies - SCADE Suite 1-4
5 PowerPC MPC755s PowerPC755 core supporting statically timed memory 32bit pipelined processor out-of-order execution, in-order completion Supports single and double precision floating point operations Supports External Memory (up to 4 GB) 32 KB Instruction Cache (PLRU(!) replacement algorithm) 32 KB Data Cache (PLRU(!) replacement algorithm) 6 independent execution units (2 Integer units, Load/Store unit, Floating-point unit, System register unit, Branch processing unit) 64-bit data bus and 32-bit address bus 2 levels of speculation, first level supports speculative execution, second level for branch prediction TriCore 32-bit microcontroller Supports single-precision floating point arithmetic TriCore 1796 Core clock up to 150 MHz 16 KB instruction cache (LRU replacement policy) 48 KB code scratch-pad RAM 136 KB internal SRAM 2 MB internal program FLASH 128 KB internal data FLASH Supports external memory (up to 246 MB) TriCore 1797 Core clock up to 180 MHz 16 KB instruction cache (LRU replacement policy) 8 KB data cache (LRU replacement policy) 24 KB code scratch-pad RAM 124 KB internal SRAM 2 MB internal program FLASH 64 KB internal data FLASH Supports external memory (up to 246 MB) TriCore 1766 Core clock up to 80 MHz 8 KB instruction cache (LRU replacement policy) 16 KB code scratch-pad RAM 56 KB internal SRAM 1504 KB internal program FLASH 32 KB internal data FLASH Esterel Technologies - SCADE Suite 1-5
6 NEC V850 NEC V850E1 Family 32-bit RISC architecture 5-stage pipeline on-chip flash memory for code and data, internal RAM external memory controller various periphery (e.g., DMA, CAN, FlexRay, timer, CRC), depending on actual device single precision floating point unit, depending on actual device devices supported by a³: V850E/PHO3 (µpd70f3441, µpd70f3483), V850E1/FK3 (µpd70f3469) NEC V850E2[R,M] Family 32-bit RISC architecture 7-stage superscalar E2 pipeline with three independent sub units dual core architecture, depending on actual device; only singlecore mode is supported by a³ on-chip code flash memory, internal RAM external memory controller, depending on actual device various periphery (e.g., DMA, CAN, Ethernet, FlexRay, timer, CRC), depending on actual device floating point unit with single and double precision operation processor protection functionality (e.g., memory access protection, peripheral devices protection) devices supported by a³: umbrella chip (µpd70f3501f1), VFOREST (μpd76f0134, μpd76f0197, μpd76f0198, μpd76f0199) LEON 32-bit pipelined SPARC v8 compliant processor Separate instruction and data caches (1 KB to 64 KB, LRU replacement policy) Supports single- and double-precision floating point arithmetic LEON2 Core clock up to 165 MHz 8/16/32-bit memory controller for external PROM and SRAM 32-bit PC133 SDRAM controller LEON3 Core clock up to 400 MHz Supports SPARC v8e extensions 8/16/32-bit memory controller for external PROM and SRAM 32-bit PC133 SDRAM controller Esterel Technologies - SCADE Suite 1-6
7 2. Stack Verifier Supported Platforms Stack Verifier supports the following platforms: All PowerPC (PPC) Family PPC is valid for Stack analysis with all PowerPC targets The following instruction sets are supported: Common Book E Embedded environment Variable length encoding (VLE) Signal Processing Engine (SPE) TriCore 1766/1796/1797 TriCore instruction set NEC V850 Family Stack analysis is supported for V850E1 (without FPU) and V850E2[M,R] targets LEON2/3 SPARC v8 instruction set Esterel Technologies - SCADE Suite 1-7
8 Contact Information Submit questions to Technical Support at Contact one of our Sales representatives at Direct general questions about Esterel Technologies to Discover the latest news on our products and technology at Copyright 2011 Esterel Technologies SA. All rights reserved. SCADE,SCADE Suite, SCADE Suite Timing Verifier, and SCADE Suite Stack Verifier are trademarks or registered trademarks of Esterel Technologies. ait/stackanalyzer is a copyright of AbsInt Angewandte Informatik. All other trademarks and tradenames are the property of their respective owners. Esterel Technologies releases this information with full intent to be 100% accurate however information contained herein is subject to change without notice and Esterel Technologies assumes no responsibility or liability as a result of any inaccuracies. Revision: SC-aiT-TSV-QRC /04/11
BEAGLEBONE BLACK ARCHITECTURE MADELEINE DAIGNEAU MICHELLE ADVENA
BEAGLEBONE BLACK ARCHITECTURE MADELEINE DAIGNEAU MICHELLE ADVENA AGENDA INTRO TO BEAGLEBONE BLACK HARDWARE & SPECS CORTEX-A8 ARMV7 PROCESSOR PROS & CONS VS RASPBERRY PI WHEN TO USE BEAGLEBONE BLACK Single
More informationOverview. CISC Developments. RISC Designs. CISC Designs. VAX: Addressing Modes. Digital VAX
Overview CISC Developments Over Twenty Years Classic CISC design: Digital VAX VAXÕs RISC successor: PRISM/Alpha IntelÕs ubiquitous 80x86 architecture Ð 8086 through the Pentium Pro (P6) RJS 2/3/97 Philosophy
More informationChapter 13. PIC Family Microcontroller
Chapter 13 PIC Family Microcontroller Lesson 01 PIC Characteristics and Examples PIC microcontroller characteristics Power-on reset Brown out reset Simplified instruction set High speed execution Up to
More informationGenerations of the computer. processors.
. Piotr Gwizdała 1 Contents 1 st Generation 2 nd Generation 3 rd Generation 4 th Generation 5 th Generation 6 th Generation 7 th Generation 8 th Generation Dual Core generation Improves and actualizations
More informationPentium vs. Power PC Computer Architecture and PCI Bus Interface
Pentium vs. Power PC Computer Architecture and PCI Bus Interface CSE 3322 1 Pentium vs. Power PC Computer Architecture and PCI Bus Interface Nowadays, there are two major types of microprocessors in the
More informationADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM
ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM 1 The ARM architecture processors popular in Mobile phone systems 2 ARM Features ARM has 32-bit architecture but supports 16 bit
More informationOpenSPARC T1 Processor
OpenSPARC T1 Processor The OpenSPARC T1 processor is the first chip multiprocessor that fully implements the Sun Throughput Computing Initiative. Each of the eight SPARC processor cores has full hardware
More informationThis Unit: Putting It All Together. CIS 501 Computer Architecture. Sources. What is Computer Architecture?
This Unit: Putting It All Together CIS 501 Computer Architecture Unit 11: Putting It All Together: Anatomy of the XBox 360 Game Console Slides originally developed by Amir Roth with contributions by Milo
More informationAm186ER/Am188ER AMD Continues 16-bit Innovation
Am186ER/Am188ER AMD Continues 16-bit Innovation 386-Class Performance, Enhanced System Integration, and Built-in SRAM Problem with External RAM All embedded systems require RAM Low density SRAM moving
More informationLecture 3: Modern GPUs A Hardware Perspective Mohamed Zahran (aka Z) mzahran@cs.nyu.edu http://www.mzahran.com
CSCI-GA.3033-012 Graphics Processing Units (GPUs): Architecture and Programming Lecture 3: Modern GPUs A Hardware Perspective Mohamed Zahran (aka Z) mzahran@cs.nyu.edu http://www.mzahran.com Modern GPU
More informationComputers. Hardware. The Central Processing Unit (CPU) CMPT 125: Lecture 1: Understanding the Computer
Computers CMPT 125: Lecture 1: Understanding the Computer Tamara Smyth, tamaras@cs.sfu.ca School of Computing Science, Simon Fraser University January 3, 2009 A computer performs 2 basic functions: 1.
More informationCHAPTER 7: The CPU and Memory
CHAPTER 7: The CPU and Memory The Architecture of Computer Hardware, Systems Software & Networking: An Information Technology Approach 4th Edition, Irv Englander John Wiley and Sons 2010 PowerPoint slides
More informationComputer Architecture TDTS10
why parallelism? Performance gain from increasing clock frequency is no longer an option. Outline Computer Architecture TDTS10 Superscalar Processors Very Long Instruction Word Processors Parallel computers
More informationMigrating Application Code from ARM Cortex-M4 to Cortex-M7 Processors
Migrating Application Code from ARM Cortex-M4 to Cortex-M7 Processors Joseph Yiu and Robert Boys January 2015 Version 1.1 The latest version of this document is here: /appnotes/docs/apnt_270.asp 1 Cortex
More informationADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-17: Memory organisation, and types of memory
ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-17: Memory organisation, and types of memory 1 1. Memory Organisation 2 Random access model A memory-, a data byte, or a word, or a double
More informationDesign Cycle for Microprocessors
Cycle for Microprocessors Raúl Martínez Intel Barcelona Research Center Cursos de Verano 2010 UCLM Intel Corporation, 2010 Agenda Introduction plan Architecture Microarchitecture Logic Silicon ramp Types
More information7a. System-on-chip design and prototyping platforms
7a. System-on-chip design and prototyping platforms Labros Bisdounis, Ph.D. Department of Computer and Communication Engineering 1 What is System-on-Chip (SoC)? System-on-chip is an integrated circuit
More information1. Memory technology & Hierarchy
1. Memory technology & Hierarchy RAM types Advances in Computer Architecture Andy D. Pimentel Memory wall Memory wall = divergence between CPU and RAM speed We can increase bandwidth by introducing concurrency
More informationIBM CELL CELL INTRODUCTION. Project made by: Origgi Alessandro matr. 682197 Teruzzi Roberto matr. 682552 IBM CELL. Politecnico di Milano Como Campus
Project made by: Origgi Alessandro matr. 682197 Teruzzi Roberto matr. 682552 CELL INTRODUCTION 2 1 CELL SYNERGY Cell is not a collection of different processors, but a synergistic whole Operation paradigms,
More informationDigitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah
(DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de NIOS II 1 1 What is Nios II? Altera s Second Generation
More informationThe ARM Cortex-A9 Processors
The ARM Cortex-A9 Processors This whitepaper describes the details of a newly developed processor design within the common ARM Cortex applications profile ARM Cortex-A9 MPCore processor: A multicore processor
More informationVon der Hardware zur Software in FPGAs mit Embedded Prozessoren. Alexander Hahn Senior Field Application Engineer Lattice Semiconductor
Von der Hardware zur Software in FPGAs mit Embedded Prozessoren Alexander Hahn Senior Field Application Engineer Lattice Semiconductor AGENDA Overview Mico32 Embedded Processor Development Tool Chain HW/SW
More informationDS1104 R&D Controller Board
DS1104 R&D Controller Board Cost-effective system for controller development Highlights Single-board system with real-time hardware and comprehensive I/O Cost-effective PCI hardware for use in PCs Application
More informationIntroduction to Microprocessors
Introduction to Microprocessors Yuri Baida yuri.baida@gmail.com yuriy.v.baida@intel.com October 2, 2010 Moscow Institute of Physics and Technology Agenda Background and History What is a microprocessor?
More informationPowerPC 405 GP Overview
PowerPC 405 GP Overview Marcelo T Pereira LISHA/UFSC trier@lisha.ufsc.br http://www.lisha.ufsc.br/~trier October 1, 2002 October 1, 2002 Marcelo T Pereira (http://www lisha ufsc br) 1 Khomp Plataform Software/Hardware
More informationLogical Operations. Control Unit. Contents. Arithmetic Operations. Objectives. The Central Processing Unit: Arithmetic / Logic Unit.
Objectives The Central Processing Unit: What Goes on Inside the Computer Chapter 4 Identify the components of the central processing unit and how they work together and interact with memory Describe how
More informationChapter 4 System Unit Components. Discovering Computers 2012. Your Interactive Guide to the Digital World
Chapter 4 System Unit Components Discovering Computers 2012 Your Interactive Guide to the Digital World Objectives Overview Differentiate among various styles of system units on desktop computers, notebook
More informationCHAPTER 4 MARIE: An Introduction to a Simple Computer
CHAPTER 4 MARIE: An Introduction to a Simple Computer 4.1 Introduction 195 4.2 CPU Basics and Organization 195 4.2.1 The Registers 196 4.2.2 The ALU 197 4.2.3 The Control Unit 197 4.3 The Bus 197 4.4 Clocks
More informationConsole Architecture. By: Peter Hood & Adelia Wong
Console Architecture By: Peter Hood & Adelia Wong Overview Gaming console timeline and evolution Overview of the original xbox architecture Console architecture of the xbox360 Future of the xbox series
More informationInstruction Set Architecture (ISA)
Instruction Set Architecture (ISA) * Instruction set architecture of a machine fills the semantic gap between the user and the machine. * ISA serves as the starting point for the design of a new machine
More informationCISC, RISC, and DSP Microprocessors
CISC, RISC, and DSP Microprocessors Douglas L. Jones ECE 497 Spring 2000 4/6/00 CISC, RISC, and DSP D.L. Jones 1 Outline Microprocessors circa 1984 RISC vs. CISC Microprocessors circa 1999 Perspective:
More informationIntroduction to RISC Processor. ni logic Pvt. Ltd., Pune
Introduction to RISC Processor ni logic Pvt. Ltd., Pune AGENDA What is RISC & its History What is meant by RISC Architecture of MIPS-R4000 Processor Difference Between RISC and CISC Pros and Cons of RISC
More informationFLOATING-POINT ARITHMETIC IN AMD PROCESSORS MICHAEL SCHULTE AMD RESEARCH JUNE 2015
FLOATING-POINT ARITHMETIC IN AMD PROCESSORS MICHAEL SCHULTE AMD RESEARCH JUNE 2015 AGENDA The Kaveri Accelerated Processing Unit (APU) The Graphics Core Next Architecture and its Floating-Point Arithmetic
More informationProducts. CM-i586 Highlights. Página Web 1 de 5. file://c:\documents and Settings\Daniel\Os meus documentos\humanoid\material_o...
Página Web 1 de 5 The Home of the World's Best Computer-On-Module's Products Computer- On-Module's CM-X270 CM-X255 CM-iGLX CM-F82 CM-i686M CM-i686B CM-iVCF CM-i886 CM-i586 PC/104+ & ATX boards SBC-X270
More informationSDRAM and DRAM Memory Systems Overview
CHAPTER SDRAM and DRAM Memory Systems Overview Product Numbers: MEM-NPE-32MB=, MEM-NPE-64MB=, MEM-NPE-128MB=, MEM-SD-NPE-32MB=, MEM-SD-NPE-64MB=, MEM-SD-NPE-128MB=, MEM-SD-NSE-256MB=, MEM-NPE-400-128MB=,
More informationFamily 10h AMD Phenom II Processor Product Data Sheet
Family 10h AMD Phenom II Processor Product Data Sheet Publication # 46878 Revision: 3.05 Issue Date: April 2010 Advanced Micro Devices 2009, 2010 Advanced Micro Devices, Inc. All rights reserved. The contents
More informationA Survey on ARM Cortex A Processors. Wei Wang Tanima Dey
A Survey on ARM Cortex A Processors Wei Wang Tanima Dey 1 Overview of ARM Processors Focusing on Cortex A9 & Cortex A15 ARM ships no processors but only IP cores For SoC integration Targeting markets:
More informationSTM32 F-2 series High-performance Cortex-M3 MCUs
STM32 F-2 series High-performance Cortex-M3 MCUs STMicroelectronics 32-bit microcontrollers, 120 MHz/150 DMIPS with ART Accelerator TM and advanced peripherals www.st.com/mcu STM32 F-2 series The STM32
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationA New, High-Performance, Low-Power, Floating-Point Embedded Processor for Scientific Computing and DSP Applications
1 A New, High-Performance, Low-Power, Floating-Point Embedded Processor for Scientific Computing and DSP Applications Simon McIntosh-Smith Director of Architecture 2 Multi-Threaded Array Processing Architecture
More informationTrend Micro Control Manager 6.0 Service Pack 2 System Requirements
Trend Micro Incorporated reserves the right to make changes to this document and to the products described herein without notice. Before installing and using the software, please review the readme files,
More information<Insert Picture Here> T4: A Highly Threaded Server-on-a-Chip with Native Support for Heterogeneous Computing
T4: A Highly Threaded Server-on-a-Chip with Native Support for Heterogeneous Computing Robert Golla Senior Hardware Architect Paul Jordan Senior Principal Hardware Engineer Oracle
More informationMPC603/MPC604 Evaluation System
nc. MPC105EVB/D (Motorola Order Number) 7/94 Advance Information MPC603/MPC604 Evaluation System Big Bend Technical Summary This document describes an evaluation system that demonstrates the capabilities
More informationDiscovering Computers 2011. Living in a Digital World
Discovering Computers 2011 Living in a Digital World Objectives Overview Differentiate among various styles of system units on desktop computers, notebook computers, and mobile devices Identify chips,
More information_ v1.0. EVB-56x Evaluation & Development Kit for Motorola PowerPC MPC56x Microcontrollers USERS MANUAL. isystem, February 2003 1/8.
_ v1.0 USERS MANUAL EVB-56x Evaluation & Development Kit for Motorola PowerPC MPC56x Microcontrollers EVB-563 EVB-565 Ordering code ITMPC563 ITMPC565 Copyright 2003 isystem, GmbH. All rights reserved.
More informationFreescale Semiconductor, Inc. Product Brief Integrated Portable System Processor DragonBall ΤΜ
nc. Order this document by MC68328/D Microprocessor and Memory Technologies Group MC68328 MC68328V Product Brief Integrated Portable System Processor DragonBall ΤΜ As the portable consumer market grows
More informationSerial port interface for microcontroller embedded into integrated power meter
Serial port interface for microcontroller embedded into integrated power meter Mr. Borisav Jovanović, Prof. dr. Predrag Petković, Prof. dr. Milunka Damnjanović, Faculty of Electronic Engineering Nis, Serbia
More informationMicroprocessor and Microcontroller Architecture
Microprocessor and Microcontroller Architecture 1 Von Neumann Architecture Stored-Program Digital Computer Digital computation in ALU Programmable via set of standard instructions input memory output Internal
More information760 Veterans Circle, Warminster, PA 18974 215-956-1200. Technical Proposal. Submitted by: ACT/Technico 760 Veterans Circle Warminster, PA 18974.
760 Veterans Circle, Warminster, PA 18974 215-956-1200 Technical Proposal Submitted by: ACT/Technico 760 Veterans Circle Warminster, PA 18974 for Conduction Cooled NAS Revision 4/3/07 CC/RAIDStor: Conduction
More informationDDR4 Memory Technology on HP Z Workstations
Technical white paper DDR4 Memory Technology on HP Z Workstations DDR4 is the latest memory technology available for main memory on mobile, desktops, workstations, and server computers. DDR stands for
More informationConfiguring Memory on the HP Business Desktop dx5150
Configuring Memory on the HP Business Desktop dx5150 Abstract... 2 Glossary of Terms... 2 Introduction... 2 Main Memory Configuration... 3 Single-channel vs. Dual-channel... 3 Memory Type and Speed...
More informationNotes and terms of conditions. Vendor shall note the following terms and conditions/ information before they submit their quote.
Specifications for ARINC 653 compliant RTOS & Development Environment Notes and terms of conditions Vendor shall note the following terms and conditions/ information before they submit their quote. 1.
More informationFreescale Semiconductor, I
nc. Application Note 6/2002 8-Bit Software Development Kit By Jiri Ryba Introduction 8-Bit SDK Overview This application note describes the features and advantages of the 8-bit SDK (software development
More informationMore on Pipelining and Pipelines in Real Machines CS 333 Fall 2006 Main Ideas Data Hazards RAW WAR WAW More pipeline stall reduction techniques Branch prediction» static» dynamic bimodal branch prediction
More informationBlock 3 Size 0 KB 0 KB 16KB 32KB. Start Address N/A N/A F4000H F0000H. Start Address FA000H F8000H F8000H F8000H. Block 2 Size 8KB 16KB 16KB 16KB
APPLICATION NOTE M16C/26 1.0 Abstract The following article describes using a synchronous serial port and the FoUSB (Flash-over-USB ) Programmer application to program the user flash memory of the M16C/26
More informationArchitecture and Implementation of the ARM Cortex -A8 Microprocessor
Architecture and Implementation of the ARM Cortex -A8 Microprocessor October 2005 Introduction The ARM Cortex -A8 microprocessor is the first applications microprocessor in ARM s new Cortex family. With
More informationAdapting the PowerPC 403 ROM Monitor Software for a 512Kb Flash Device
Adapting the PowerPC 403 ROM Monitor Software for a 512Kb Flash Device IBM Microelectronics Dept D95/Bldg 060 3039 Cornwallis Road Research Triangle Park, NC 27709 Version: 1 December 15, 1997 Abstract
More informationReconfigurable System-on-Chip Design
Reconfigurable System-on-Chip Design MITCHELL MYJAK Senior Research Engineer Pacific Northwest National Laboratory PNNL-SA-93202 31 January 2013 1 About Me Biography BSEE, University of Portland, 2002
More informationARM Cortex STM series
ARM Cortex board 1 ARM Cortex STM series 2 STM32 Series 3 Abbreviation FS full speed HS high speed MC motor controller MSI multi speed internal oscillator RNG random number generator SDIO secure digital
More informationNetwork connectivity controllers
Network connectivity controllers High performance connectivity solutions Factory Automation The hostile environment of many factories can have a significant impact on the life expectancy of PCs, and industrially
More informationThe Central Processing Unit:
The Central Processing Unit: What Goes on Inside the Computer Chapter 4 Objectives Identify the components of the central processing unit and how they work together and interact with memory Describe how
More informationEmbedded Systems on ARM Cortex-M3 (4weeks/45hrs)
Embedded Systems on ARM Cortex-M3 (4weeks/45hrs) Course & Kit Contents LEARN HOW TO: Use of Keil Real View for ARM Use ARM Cortex-M3 MCU for professional embedded application development Understanding
More informationAll Programmable Logic. Hans-Joachim Gelke Institute of Embedded Systems. Zürcher Fachhochschule
All Programmable Logic Hans-Joachim Gelke Institute of Embedded Systems Institute of Embedded Systems 31 Assistants 10 Professors 7 Technical Employees 2 Secretaries www.ines.zhaw.ch Research: Education:
More informationOC By Arsene Fansi T. POLIMI 2008 1
IBM POWER 6 MICROPROCESSOR OC By Arsene Fansi T. POLIMI 2008 1 WHAT S IBM POWER 6 MICROPOCESSOR The IBM POWER6 microprocessor powers the new IBM i-series* and p-series* systems. It s based on IBM POWER5
More informationVideo Conference System
CSEE 4840: Embedded Systems Spring 2009 Video Conference System Manish Sinha Srikanth Vemula Project Overview Top frame of screen will contain the local video Bottom frame will contain the network video
More informationIntel 8086 architecture
Intel 8086 architecture Today we ll take a look at Intel s 8086, which is one of the oldest and yet most prevalent processor architectures around. We ll make many comparisons between the MIPS and 8086
More informationArchitectures, Processors, and Devices
Architectures, Processors, and Devices Development Article Copyright 2009 ARM Limited. All rights reserved. ARM DHT 0001A Development Article Copyright 2009 ARM Limited. All rights reserved. Release Information
More informationFamily 12h AMD Athlon II Processor Product Data Sheet
Family 12h AMD Athlon II Processor Publication # 50322 Revision: 3.00 Issue Date: December 2011 Advanced Micro Devices 2011 Advanced Micro Devices, Inc. All rights reserved. The contents of this document
More informationPerformance Counter Monitoring for the Blue Gene/Q Architecture
Performance Counter Monitoring for the Blue Gene/Q Architecture Heike McCraw Innovative Computing Laboratory University of Tennessee, Knoxville 1 Introduction and Motivation With the increasing scale and
More informationAlgorithms and Methods for Distributed Storage Networks 3. Solid State Disks Christian Schindelhauer
Algorithms and Methods for Distributed Storage Networks 3. Solid State Disks Institut für Informatik Wintersemester 2007/08 Solid State Disks Motivation 2 10 5 1980 1985 1990 1995 2000 2005 2010 PRODUCTION
More informationBuilding Blocks for PRU Development
Building Blocks for PRU Development Module 1 PRU Hardware Overview This session covers a hardware overview of the PRU-ICSS Subsystem. Author: Texas Instruments, Sitara ARM Processors Oct 2014 2 ARM SoC
More informationVHDL DESIGN OF EDUCATIONAL, MODERN AND OPEN- ARCHITECTURE CPU
VHDL DESIGN OF EDUCATIONAL, MODERN AND OPEN- ARCHITECTURE CPU Martin Straka Doctoral Degree Programme (1), FIT BUT E-mail: strakam@fit.vutbr.cz Supervised by: Zdeněk Kotásek E-mail: kotasek@fit.vutbr.cz
More informationAN10850. LPC1700 timer triggered memory to GPIO data transfer. Document information. LPC1700, GPIO, DMA, Timer0, Sleep Mode
LPC1700 timer triggered memory to GPIO data transfer Rev. 01 16 July 2009 Application note Document information Info Keywords Abstract Content LPC1700, GPIO, DMA, Timer0, Sleep Mode This application note
More informationMVME162P2. VME Embedded Controller with Two IP Slots
MVME162P2 VME Embedded Controller with Two IP Slots [Advantages] [Details] [Specifications] [Ordering Info] [.pdf version ] 25 MHz MC68040 with floating point coprocessor or 25 MHz MC68LC040 High-performance
More informationBasic Computer Organization
Chapter 2 Basic Computer Organization Objectives To provide a high-level view of computer organization To describe processor organization details To discuss memory organization and structure To introduce
More informationMaritime HMI - S Line.
Maritime HMI - S Line. 9,65 cm (3,8 II ) FSTN (Mono) / LED (white) 14,48 cm (5,7 II ) FSTN (Mono) / LED (white) 14,48 cm (5,7 II ) TFT (colour) / LED (white) 5 Shades of grey 5 Shades of grey 256 320 x
More informationArchitekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen. Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik
Architekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik Contents Überblick: Aufbau moderner FPGA Einblick: Eigenschaften
More information13. Publishing Component Information to Embedded Software
February 2011 NII52018-10.1.0 13. Publishing Component Information to Embedded Software NII52018-10.1.0 This document describes how to publish SOPC Builder component information for embedded software tools.
More informationIntroduction to GP-GPUs. Advanced Computer Architectures, Cristina Silvano, Politecnico di Milano 1
Introduction to GP-GPUs Advanced Computer Architectures, Cristina Silvano, Politecnico di Milano 1 GPU Architectures: How do we reach here? NVIDIA Fermi, 512 Processing Elements (PEs) 2 What Can It Do?
More informationELE 356 Computer Engineering II. Section 1 Foundations Class 6 Architecture
ELE 356 Computer Engineering II Section 1 Foundations Class 6 Architecture History ENIAC Video 2 tj History Mechanical Devices Abacus 3 tj History Mechanical Devices The Antikythera Mechanism Oldest known
More informationTable 1: Address Table
DDR SDRAM DIMM D32PB12C 512MB D32PB1GJ 1GB For the latest data sheet, please visit the Super Talent Electronics web site: www.supertalentmemory.com Features 184-pin, dual in-line memory module (DIMM) Fast
More informationMemory Basics. SRAM/DRAM Basics
Memory Basics RAM: Random Access Memory historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities ROM: Read Only Memory no capabilities for
More informationVLIW Processors. VLIW Processors
1 VLIW Processors VLIW ( very long instruction word ) processors instructions are scheduled by the compiler a fixed number of operations are formatted as one big instruction (called a bundle) usually LIW
More informationChapter 6. Inside the System Unit. What You Will Learn... Computers Are Your Future. What You Will Learn... Describing Hardware Performance
What You Will Learn... Computers Are Your Future Chapter 6 Understand how computers represent data Understand the measurements used to describe data transfer rates and data storage capacity List the components
More informationTechnical Data Sheet SCADE R17 Solutions for ARINC 661 Compliant Systems Design Environment for Aircraft Manufacturers, CDS and UA Suppliers
661 Solutions for ARINC 661 Compliant Systems SCADE R17 Solutions for ARINC 661 Compliant Systems Design Environment for Aircraft Manufacturers, CDS and UA Suppliers SCADE Solutions for ARINC 661 Compliant
More informationARM Microprocessor and ARM-Based Microcontrollers
ARM Microprocessor and ARM-Based Microcontrollers Nguatem William 24th May 2006 A Microcontroller-Based Embedded System Roadmap 1 Introduction ARM ARM Basics 2 ARM Extensions Thumb Jazelle NEON & DSP Enhancement
More informationComparative Performance Review of SHA-3 Candidates
Comparative Performance Review of the SHA-3 Second-Round Candidates Cryptolog International Second SHA-3 Candidate Conference Outline sphlib sphlib sphlib is an open-source implementation of many hash
More informationComputer Architectures
Computer Architectures 2. Instruction Set Architectures 2015. február 12. Budapest Gábor Horváth associate professor BUTE Dept. of Networked Systems and Services ghorvath@hit.bme.hu 2 Instruction set architectures
More informationIndustry First X86-based Single Board Computer JaguarBoard Released
Industry First X86-based Single Board Computer JaguarBoard Released HongKong, China (May 12th, 2015) Jaguar Electronic HK Co., Ltd officially launched the first X86-based single board computer called JaguarBoard.
More informationAtmel Norway 2005. XMEGA Introduction
Atmel Norway 005 XMEGA Introduction XMEGA XMEGA targets Leadership on Peripheral Performance Leadership in Low Power Consumption Extending AVR market reach XMEGA AVR family 44-100 pin packages 16K 51K
More informationINSTRUCTION LEVEL PARALLELISM PART VII: REORDER BUFFER
Course on: Advanced Computer Architectures INSTRUCTION LEVEL PARALLELISM PART VII: REORDER BUFFER Prof. Cristina Silvano Politecnico di Milano cristina.silvano@polimi.it Prof. Silvano, Politecnico di Milano
More informationSPARC64 VIIIfx: CPU for the K computer
SPARC64 VIIIfx: CPU for the K computer Toshio Yoshida Mikio Hondo Ryuji Kan Go Sugizaki SPARC64 VIIIfx, which was developed as a processor for the K computer, uses Fujitsu Semiconductor Ltd. s 45-nm CMOS
More informationComputer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.
Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.tw Review Computers in mid 50 s Hardware was expensive
More information85MIV2 / 85MIV2-L -- Components Locations
Chapter Specification 85MIV2 / 85MIV2-L -- Components Locations RJ45 LAN Connector for 85MIV2-L only PS/2 Peripheral Mouse (on top) Power PS/2 K/B(underside) RJ45 (on top) +2V Power USB0 (middle) USB(underside)
More informationAN4664 Application note
Application note SPC56ELxx Automotive MCU multicore architectures and getting started Introduction This document provides an introduction to the world of multi-core MCU architectures and programming and
More informationUsing Nios II Floating-Point Custom Instructions Tutorial
Using Nios II Floating-Point Custom Instructions Tutorial 101 Innovation Drive San Jose, CA 95134 www.altera.com TU-N2FLTNGPNT-2.0 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable
More informationMotor Control using NXP s LPC2900
Motor Control using NXP s LPC2900 Agenda LPC2900 Overview and Development tools Control of BLDC Motors using the LPC2900 CPU Load of BLDCM and PMSM Enhancing performance LPC2900 Demo BLDC motor 2 LPC2900
More informationHow To Compare Two Servers For A Test On A Poweredge R710 And Poweredge G5P (Poweredge) (Power Edge) (Dell) Poweredge Poweredge And Powerpowerpoweredge (Powerpower) G5I (
TEST REPORT MARCH 2009 Server management solution comparison on Dell PowerEdge R710 and HP Executive summary Dell Inc. (Dell) commissioned Principled Technologies (PT) to compare server management solutions
More information21152 PCI-to-PCI Bridge
Product Features Brief Datasheet Intel s second-generation 21152 PCI-to-PCI Bridge is fully compliant with PCI Local Bus Specification, Revision 2.1. The 21152 is pin-to-pin compatible with Intel s 21052,
More information