3D Effect Audio Processor IC

Transcription

1 DESCRIPTION is a utilizing CMOS Technology. It eatures a specially designed PTC HRTFs Filter and space-enhanced circuit, thereby, guaranteeing excellent audio quality and perormance. Least external components, excellent 3D eect audio output, built-in LED display driver add to the enhanced quality o. Pin assignments and application circuit are optimized or easy PCB Layout and cost saving beneits. FEATURES CMOS technology Operating voltage range: 5V to 9 V THD=N<0.01%, S/N>95dB Specially designed PTC HRTFs ilter technology and 3D space-enhanced circuit Least external components Built-in LED display driver Available in 8 Pins, DIP or SOP APPLICATIONS Multi-media audio Car audio Walkman Home stereo TV PC speakers Notebook Computer/Laptop Other audio equipment V March, 2006

2 BLOCK DIAGRAM By Pass Sw1 To 3D Control RIN -1 PTC'HRTFs -1 3D ROUT LIN +1 PTC'HRTFs 3D LOUT By Pass Sw2 3D Control V March, 2006

3 PIN CONFIGURATION VREF 1 8 VCC GND 3D LOUT LIN ROUT 4 5 RIN PIN DESCRIPTION Pin Name I/O Description Pin No. VREF O 1/2 VCC Connect capacitor to GND 1 GND - Ground Pin 2 3D I 3D Eect Control Pin 3 ROUT O Right Channel Output Pin 4 RIN I Right Channel Input Pin 5 LIN I Let Channel Input Pin 6 LOUT O Let Channel Output Pin 7 VCC - Positive Power Supply 8 V March, 2006

4 FUNCTION DESCRIPTION The 3D eect o is controlled by Pin No.3 (3D pin) via a TACT Switch which is triggered when connected to Vcc ( High ). Please reer to the diagram below. Power On By Pass 3D Surround Trigger On/O Cycle Press 3D key LED DISPLAY DRIVER has a built-in LED driver which is used to display the 3D activity status. Please reer to the table below. 3D/Surround Eect OFF LED Display OFF 3D/Surround Eect ON LED Display ON V March, 2006

5 ABSOLUTE MAXIMUM RATING Parameter Symbol Ratings Unit Positive power supply V CC 12 V Input voltage Vi 0.3 to V CC +0.3 V Operating temperature Topr -40 ~ +85 Storage temperature Tstg -65 ~ +150 DC ELECTRICAL CHARACTERISTICS (Unless otherwise speciied, V CC =9V, Vi=1Vrms, =1KHz, Ta=27 ) Parameter Symbol Condition Min. Typ. Max. Unit Operating voltage V CC V Operating current I CC Vcc=9V, Vi=0V, Bypass Mode ma Maximum output voltage V OM Vcc=9V Vrms Output noise voltage V ON Vcc=9V, Vi=0V, BW=20 to 20KHz, A-weighting db Total harmonic distortion THD Vcc=9V, Vi=0.2Vrms, BW=20 to 20KHz, Bypass Mode % Input impedance R IN Vcc=9V KΩ Output impedance R OUT Vcc=9V Ω High level input voltage V IN Vcc=9V V CC V Low level input voltage V IL Vcc=9V 0.3VCC - - V Maximum input voltage V IMAX Vcc=9V, Bypass Mode Vrms V March, 2006

6 APPLICATION CIRCUIT 9V 3D KEY 9V + 47µ VREF GND 3D VCC LOUT LIN µ µ LIN µ µ + RIN LED 10µ + LOUT 10µ + ROUT V March, 2006

7 ORDER INFORMATION Valid Part Number Package Type Top Code 8 Pins, DIP, 300mil -S 8 Pins, SOP, 150mil -S V March, 2006

8 PACKAGE INFORMATION 8 PINS, DIP, 300MIL V March, 2006

9 Symbol Min. Nom. Max. A A A b b b b c c D D E E e bsc. ea bsc. eb ec L Notes: 1. Controlling Dimensions: INCHES. 2. Dimensioning and tolerancing per ANSI Y14.5M Symbols are deined in the MO Series Symbol LIST in Section 2.2 o Publication No Dimension A, A1 and L are measured with the package seated in JEDEC Seating Plane Gauge GS D, D1 and E1 dimensions do not include mold lash or protrusions. Mold lash or protrusions shall not exceed inch. 6. E and ea measured with the leads constrained to be perpendicular to data -c-. 7. eb and ec are measured at the lead tips with the leads unconstrained. 8. N is the number o leads (N=8) 9. Pointed or rounded lead tips are preerred to ease insertion. 10. b2 and b3 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm) 11. Variation BA has a b3 dimension and is 1/2 lead package. 12. Distance between the leads including dambar protrusions to be inch minimum. 13. Datum plane -H- coincident with the bottom o lead, where lead exits the body. 14. Reer to JEDEC MS-001, Variation BA. JEDEC is the registered trademark o JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. V March, 2006

10 8 PINS, SOP, 150MIL V March, 2006

11 V March, 2006

12 Symbol Min. Typ. Max. A A A b b c c D 4.90 BSC. E 6.00 BSC. E BSC. e 1.27 BSC. L L REF. L BSC. R R h θ 0-8 θ θ Notes: 1. Dimensioning and tolerancing per ANSI Y 14.5M Controlling Dimension: MILLIMETERS. 3. Dimension D does not include mold lash protrusions or gate burrs. Mold lash, protrusions or gate burrs shall not exceed 0.15 mm (0.006 in) per end. Dimension E1 does not include interlead lash or protrusion. Interlead lash or protrusion shall not exceed 0.25mm per side. D and E1 dimensions are determined at datum H. 4. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes o the plastic body exclusive o mold lash, tie bar burrs, gate burrs and interlead lash, but including any mismatch between the top and bottom o the plastic body. 5. Datums A & B to be determined at datum H. 6. N is the number o terminal positions. (N=8) 7. The dimensions apply to the lat section o the lead between 0.10 to 0.25mm rom the lead tip. 8. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm total in excess o the b dimension at maximum material condition. The dambar cannot be located on the lower radius o the oot. 9. This chamer eature is optional. I it is not present, then a pin 1 identiier must be located within the index area indicated. 10. Reer to JEDEC MS-012, Variation AA. JEDEC is the registered trademark o JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. V March, 2006