NB7V32M. 1.8V / 2.5V, 10GHz 2 Clock Divider with CML Outputs. Multi Level Inputs w/ Internal Termination

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1 .8V / 2.5V, 0GHz 2 Clock Divider with CML Outputs Multi Level Inputs w/ Internal Termination Description The is a differential 2 Clock divider with asynchronous reset. The differential Clock inputs incorporate internal termination resistors and will accept LVPECL, CML and LVDS logic levels. The produces a 2 output copy of an input Clock operating up to 0 GHz with minimal jitter. The RESET Pin is asserted on the rising edge. Upon power up, the internal flip flops will attain a random state; the Reset allows for the synchronization of multiple s in a system. The 6 ma differential CML output provides matching internal termination which guarantees 400 mv output swing when externally receiver terminated with to. The is the.8 V/2.5 V version of the NB7L32M (2.5 V/3.3 V) and is offered in a low profile 3 mm x 3 mm 6 pin FN package. The is a member of the GigaComm family of high performance clock products. Application notes, models, and support documentation are available at Features Maximum Input Clock Frequency > 0 GHz, typical Random Clock Jitter < 0.8 ps RMS 200 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times Differential CML Outputs, 400 mv Peak to Peak, Typical Operating Range: =.7 V to V with = 0 V Internal Input Termination Resistors FN 6 Package, 3 mm x 3 mm 40 C to +85 C Ambient Operating Temperature These are Pb Free Devices FN 6 MN SUFFIX CASE 485G MARKING DIAGRAM* A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. VT VT VREFAC R 6 RESET 2 NB7V 32M ALYW Figure. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 200 August, 200 Rev. 5 Publication Order Number: /D

2 VCC R VCC VCC Exposed Pad (EP) Table. TRUTH TABLE R VT 2 VCC x x H L H Z W L Z = LOW to HIGH Transition W = HIGH to LOW Transition x = Don t Care VT 4 9 VCC VREFAC Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description VT Internal Termination Pin for 2 LVPECL, CML, LVDS Input 3 LVPECL, CML, LVDS Input Non inverted Differential Input. (Note ) Inverted Differential Input. (Note ) 4 VT Internal Termination Pin for 5 VREFAC Internally Generated Output Voltage Reference for Capacitor Coupled Inputs, only 6 Negative Supply Voltage 7 Negative Supply Voltage 8 Negative Supply Voltage 9 VCC Positive Supply Voltage. (Note 2) 0 CML Output Inverted Differential Output CML Output Non Inverted Differential Output 2 VCC Positive Supply Voltage. (Note 2) 3 VCC Positive Supply Voltage. (Note 2) 4 VCC Positive Supply Voltage. (Note 2) 5 R LVCMOS Input Asynchronous Reset Input. Internal 75 k pulldown to. 6 VCC Positive Supply Voltage. (Note 2) EP The Exposed Pad (EP) on the FN 6 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to on the PC board.. In the differential configuration when the input termination pins (VT, VT) are connected to a common termination voltage or left open, and if no signal is applied on / input, then the device will be susceptible to self oscillation. / outputs have internal source termination resistors. 2. VCC and pins must be externally connected to a power supply for proper operation. 2

3 Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model > 4 kv > 200 V Moisture Sensitivity 6 FN Level Flammability Rating Oxygen Index: 28 to 34 UL 94 V 0.25 in Transistor Count 64 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition Condition 2 Rating Unit Positive Power Supply = 0 V 3.0 V V IN Positive Input Voltage = 0 V 0.5 to V V V INPP Differential Input Voltage D D.89 V I IN Input Current Through R T ( Resistor) 40 ma I OUT Output Current Through R T ( Resistor) 40 ma I VREFAC VREFAC Sink/Source Current.5 ma T A Operating Temperature Range 40 to +85 C T stg Storage Temperature Range 65 to +50 C JA Thermal Resistance (Junction to Ambient) (Note 3) 0 lfpm 500 lfpm FN 6 FN C/W C/W JC Thermal Resistance (Junction to Case) (Note 3) FN 6 4 C/W T sol Wave Solder Pb Free 265 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. 3

4 Table 5. DC CHARACTERISTICS POSITIVE CML OUTPUT =.7 V to V; = 0 V; T A = 40 C to 85 C (Note 4) Symbol Characteristic Min Typ Max Unit POWER SUPPLY CURRENT I CC Power Supply Current (Inputs and Outputs Open) CML OUTPUTS = 2.5 V 5% =.8 V 5% ma V OH Output HIGH Voltage (Note 5) = 2.5 V =.8 V mv V OL Output LOW Voltage (Note 5) = 2.5 V = 2.5 V mv =.8 V =.8 V DIFFERENTIAL INPUTS DRIVEN SINGLE ENDED (Note 6) (Figures 5 and 7) Input Threshold Reference Voltage Range (Note 7) mv V IH Single Ended Input HIGH Voltage + 00 mv V IL Single Ended Input LOW Voltage 00 mv V ISE Single Ended Input Voltage (V IH V IL ) mv VREFAC V REFAC Output Reference 00 A for capacitor coupled inputs, only = 2.5 V (Note 8) =.8 V DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 9) (Note 9) V IHD Differential Input HIGH Voltage 00 mv V ILD Differential Input LOW Voltage 00 mv V ID Differential Input Voltage (V IHD V ILD ) mv V CMR Input Common Mode Range (Differential Configuration, Note 0) (Figure 9) mv mv I IH Input HIGH Current (VT/VT Open) ua I IL Input LOW Current (VT/VT Open) ua CONTROL INPUT (Reset Pin) V IH Input HIGH Voltage for Control Pin 200 mv V IL Input LOW Voltage for Control Pin 200 mv I IH Input HIGH Current ua I IL Input LOW Current ua TERMINATION RESISTORS R TIN Internal Input Termination Resistor 0 ma) R TOUT Internal Output Termination Resistor 0 ma) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary : with. 5. CML outputs loaded with to for proper operation. 6., V IH, V IL and V ISE parameters must be complied with simultaneously. 7. is applied to the complementary input when operating in single ended mode. 8. V REFAC will not be less than mv. 9. V IHD, V ILD, V ID and V CMR parameters must be complied with simultaneously. 4

5 0.V CMR min varies : with, V CMR max varies : with. The V CMR range is referenced to the most positive side of the differential input signal. Table 6. AC CHARACTERISTICS =.7 V to V; = 0 V; T A = 40 C to 85 C (Note ) Symbol Characteristic Min Typ Max Unit f MAX Maximum Input Clock Frequency 0 GHz V OUTPP Output Voltage Amplitude V INPPmin ) f in 0GHz (Note 2) (Figure 3) mv t PLH, t PHL Propagation Delay to Differential GHz, measured at differential cross point / to, R to, ps t PLH TC Propagation Delay Temperature Coefficient fs/ C t skew Duty Cycle Skew (Note 3) Device Device skew (t pdmax t pdmin ) t RR Reset Recovery (See Figure ) t PW Minimum Pulse Width R ps t DC Output Clock Duty Cycle (Reference Duty Cycle = 50%) f in 0 GHz % t JITTER RJ Output Random Jitter (Note 4) f in 0 GHz ps RMS V INPP Input Voltage Swing (Differential Configuration) (Figure 0) (Note 5) mv t r, t f Output Rise/Fall GHz (20% 80%),, ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.. Measured using a GHz, V INPP min, 50% duty cycle clock source. All output loading with external to. Input edge rates 40 ps (20% 80%). 2. Output voltage swing is a single ended measurement operating in differential mode. 3. Duty cycle skew is defined only for differential operation when the delays are measured from cross point of the inputs to the cross point of the outputs. Duty cycle skew is measured between differential outputs using the deviations of the sum of T pw and T GHz. Skew is measured between outputs under identical transitions and conditions. 4. Additive RMS jitter with 50% duty cycle clock signal. 5. Input voltage swing is a single ended measurement operating in differential mode. 500 OUTPUT VOLTAGE AMPLITUDE (mv) AMP (mv) fin, Clock Input Frequency (GHz) VT VT R C R C I Figure 3. CLOCK Output Voltage Amplitude (V OUTPP ) vs. Input Frequency (f in ) at Ambient Temperature (Typ) Figure 4. Input Structure 5

6 V IH V IL Figure 5. Differential Input Driven Single Ended Figure 6. Differential Inputs Driven Differentially max V IHmax V ILmax V IH V IL V ID = V IHD() V ILD() V IHD V ILD min V IHmin V ILmin Figure 7. Diagram Figure 8. Differential Inputs Driven Differentially V IHDmax V CMmax V ILDmax V IHDtyp V INPP = V IH () V IL () V CMR V CMmin V ID = V IHD V ILD V ILDtyp V IHDmin V OUTPP = V OH () V OL () t PHL V ILDmin t PLH Figure 9. V CMR Diagram Figure 0. AC Reference Measurement 50% 50% V OUTPP = V OH () V OL () t PLH t PHL 50% 50% V INPP = V IH () V IL () R t RR(MIN) 50% Figure. AC Reference Measurement (Timing Diagram) 6

7 Z O = Z O = LVPECL V T V T Z O = LVDS V T V T Z O = = 2 V V EE V EE Figure 2. LVPECL Interface Figure 3. LVDS Interface Z O = CML V T V T Z O = V T = V T = Figure 4. Standard Load CML Interface Z O = Z O = Differential V T V T Z O = Single Ended V T V T = V REFAC = V REFAC Figure 5. Capacitor Coupled Differential Interface (V T /V T Connected to V REFAC ; V REFAC Bypassed to Ground with 0. F Capacitor) Figure 6. Capacitor Coupled Single Ended Interface (V T /V T Connected to V REFAC ; V REFAC Bypassed to Ground with 0. F Capacitor) 7

8 Receiver (Receiver) 6 ma Figure 7. Typical CML Output Structure and Termination DUT Device Z = Z = D D Receiver Device ORDERING INFORMATION MNG MNTXG Figure 8. Typical Termination for CML Output and Device Evaluation Device Package Shipping FN 6 (Pb free) FN 6 (Pb free) 23 Units / Rail 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 8

9 PACKAGE DIMENSIONS FN6 3x3, 0.5P CASE 485G 0 ISSUE E 2X PIN LOCATION 2X NOTE C 0.05 C 0.05 C 0.0 C DETAIL A 6X L D ÇÇÇ ÇÇÇ TOP VIEW DETAIL B SIDE VIEW D2 8 (A3) A B E A A C 0.0 C A B L EXPOSED Cu SEATING PLANE L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS ÉÉ ÉÉ MOLD CMPD A DETAIL B ALTERNATE CONSTRUCTIONS PACKAGE OUTLINE L A3 NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A A A REF b D 3.00 BSC D E 3.00 BSC E e 0.50 BSC K 0.8 TYP L L RECOMMENDED SOLDERING FOOTPRINT* 6X X K E2 2X 2X e e/2 BOTTOM VIEW 6X b 0.0 C 0.05 C A B NOTE 3 6X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (), may be covered by U.S. patents including 6,362,644. There may be other patents pending. GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. /D

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