Chebyshev I Bandpass IIR Filter with 6 th Order

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1 Chebyshev I Bandpass IIR Filter with 6 th Order Study Group: IEM2 Hand in Date: Group Members: Chao Chen Bing Li Chao Wang Professor: Prof. Dr. Schwarz 1

2 Contents 1. Introduction Analysis Cascade Structure Scaling Matlab Simulation Implementation Order2_IIR.vhd Order6_IIR.vhd Mono_gen.vhd Top Entity Package Implementation Result Conclusion Reference...23 Figures Figure 1 Cascade structure for 6 th order IIR...4 Figure 2 Matlab file coef.m...6 Figure 3 code listing of dec2bin.c...8 Figure 4 Matlab calculated frequency response of structure in figure Figure 5 Simulation diagram (step response)...9 Figure 6 SOS transposed form for VHDL modeling in case of ai < Figure 7 Order2_IIR.vhd...12 Figure 8 Order6_IIR.vhd...14 Figure 9 Structure of VHDL modeling...14 Figure 10 Mono_gen.vhd...15 Figure 11 entity_iir.vhd...17 Figure 12 IIR_PKG.vhd...18 Figure 13 Measured frequency response of IIR filter (1)...19 Figure 14 Measured frequency response of IIR filter (2)...20 Figure 15 Measured frequency response of IIR filter (3)...20 Figure 16 Measured frequency response of IIR filter (4)...21 Figure 17 timing simulaton diagram of step response...21 Equations Equation 1 Sensitivity function...4 2

3 1. Introduction Digital filters are among the most significant components in digital signal processing applications. The function of a filter is to eliminate undesirable parts of the signal (random noise), or to extract signals in a particular frequency range. In this lab, a parallel IIR chebyshev type I bandpass filter which has 6 th order was developed. Comparing with FIR filter, because of the feedback mechanism, IIR filter is much efficient than FIR filter. Namely, with less order IIR can have even sharper transition bands than FIR filter. But the trade off is that, IIR doesn t have constant group delay, it may distort the output signals by change the time difference of different frequency components. The two biggest characteristics of our case are that, first the cascade parallel structure was used to realize high order filters, and each substructure represents 2 nd order filter. To realize the SOS structure, the matlab program is prepared to calculate the coefficients of each substructure; second, since fixed-point implementation was chosen*, therefore at each addition step overflow was checked carefully. The scaling using chebyshev norm was used to make output adder overflow free. This guarantees that the output y at each stage would be less than 1. Since the Q format is used, only fractional number can be represented in this form. Because the scaling of output adders does not guaranty overflow free of internal adders, one guard bit is added which is proved to be enough during the lab to avoid the internal adders overflow. The input and output signal vector width is 12 bit which is enough for precision and 11 bit vector width is used for coefficients. At first the internal signals vector width with 17 bit was used. The result of IIR filter was good, then 13 bit, even 10 bit was tried which work still good. * Because Fixed-point implementation has some benefits comparing to floating-point implementation. F.e. cost effective, better precision and less hardware complicated. 3

4 2. Analysis 2.1 Cascade Structure High order IIR filters should be represented and implemented with a cascade of second order sections (SOS). According to the sensitivity function (Which describes the influence of coefficient changes on pole location, equation 1), the nominator decreases the sensitivity with a reduced number of poles (small N). This is the main reason to implement cascaded SOSs which reduces the denominator to one factor. p a i i = N j= 1, j i p N k i ( p i p j ) Equation 1 Sensitivity function The cascade structure for 6 order IIR is shown in the following figure. G 03( z ) G 02 ( z ) G 01( z ) Y Interface Not necessary S ( 1G1 z) S 2G2 ( z) S 3G3( z) Figure 1 Cascade structure for 6 th order IIR Transposed form II was used, because it provides an advantage that input excitation is performed by attenuated x input, and supports overflow free of internal adders. 4

5 2.2 Scaling Scaling procedure based on estimation of scaling factors i = I i S 1 / which provide maximum amplitudes in nodes y i but prevent the output adders from overflow: 1. Calculate norm I 1 of G 01( z ) and scale the transfer function: S ( ) ( 1G1 z = G1s z). 2. Calculate norm I 2 of S 1G1( z) G2 ( z) and scale the transfer function: S ( 2G2 2s z z) = G ( ). 3. Calculate norm I 3 of S 1G1 ( z) S 2G2 ( z) G3 ( z) and scale the transfer function: S ( 3G3 3s z z) = G ( ). 4. The transfer function of the secaled cascade of SOS will become: S 1G1 ( z) S 2G2 ( z) S3G3 ( z) 2.3 Matlab Simulation The following figure shows the Matlab calculations with equations. Passband edge frequency with -3dB Scaling factor result 5

6 b i = 0 no dc gain, no low pass After scaling all coefficients are less than 1 b0=b2, b1=2b0 lowpass Scaled coefficients results of binary representation Figure 2 Matlab file coef.m The scaled coefficients are shown between line 33 to line 35 in decimal format. The binary s representations are shown between line 37 to line 39 which are created by the c file dec2bin.c (Figure 3). 11 bit coefficient 6

7 7

8 Figure 3 code listing of dec2bin.c The following figure shows the Matlab calculated results. Figure 4 Matlab calculated frequency response of structure in figure 1 After scaling the maximum output of each SOS is equal or less than 1. 8

9 The following figure shows the step response. [b,a] = cheby1(3, 3, [ ]); SYS = TF(b,a,1); step(sys);grid; Figure 5 Simulation diagram (step response) 9

10 3. Implementation 3.1 Order2_IIR.vhd One 2 nd order transpose form II IIR filter structure with bit descriptions is shown in the following figure. Only one sign bit is needed, due to scaling no overflow exist. Then converted into 17 bit [22:6]. After multiplication there are two sign bits, one sign bit is used as guard bit. Because the coefficients are less than 1, one sign bit is enough. Figure 6 SOS transposed form for VHDL modeling in case of ai <1 This bandpass IIR filter is of 6 th order, and is implemented using cascaded SOS structure. There are two basic ways to realize it. One way is that only one SOS is developed, because each SOS is nearly the same except the different coefficients. 6 order filter is realized by just instantiating the SOS for three times. This way simplifies the development, since only one SOS is coded. The other way is that all three SOSs are coded. This way treats each coefficient carefully. For example from line 33 of the figure 2 we can see that b1 equals 0, so b1 is not needed to be multiplied by x, that means one multiplier is saved. Using this way some additional work must be done in order to save hardware. In this lab report the first way was implemented. In order to save hardware less internal signal vector width can be used. During the lab the 13 bit and even 10 bit were tried, the IIR filter works fine. If another passband edge frequencies are chosen, the a i coefficients maybe greater than one. In this case one sign bit and one guard bit must be used to realize the value greater than 1. The following figure shows the VHDL source code. 10

11 Each SOS can use generic map to initialize the coefficients. The internal signals have one guard bit to avoid the addition overflow. One sign bit can be used as guard bit. Saturation is not needed because of scaling 11

12 The format of Sum0 is sg.msb...lsb (16:0) Because of scaling no overflow will occur, bit 16 and 15 are the same. Only one sign bit is needed for the feedback signal. Figure 7 Order2_IIR.vhd Because the scaling of output adders does not guaranty overflow free internal adders, one guard bit of the internal signal is needed. During the lab we saw that one bit guard bit is enough. In this implementation the output is delayed by one clock cycle, that is, one delay element is added after the feedback. The enable signal should be also delayed by one clock cycle. It is still a parallel structure where the SOSs are separated by pipelining register in order to cut off the chain of multipliers and adders (comp. fig 1). The latency increases but the throughput remains the same as without pipelining. 3.2 Order6_IIR.vhd This file instances three times the order2_iir in order to get the 6 order IIR. 12

13 Initialize the coefficients by generic map 13

14 Never be used, can be open Figure 8 Order6_IIR.vhd Order6_IIR connects the 3 SOS IIR filters to realize the 6 order IIR filter. The last output register y is not necessary because the interface component's input consists of a register which is loaded in parallel and shifted out in serial. 3.3 Mono_gen.vhd Because the ready signal which the interface provides lasts two clock cycles, the Mono_gen.vhd file is used to reduce the ready signal duration to 1 clock cycle. The following figure shows the structure of implementation. Figure 9 Structure of VHDL modeling The VHDL source code is shown in the following figure. 14

15 Figure 10 Mono_gen.vhd 3.4 Top Entity This file connects all components together. The VHDL source code is show in the following figure. 15

16 16

17 Figure 11 entity_iir.vhd Component CODEC_FPGA is the same as the Lab FIR, so the detail will not be mentioned in this report. 3.5 Package 17

18 Figure 12 IIR_PKG.vhd 18

19 3.6 Implementation Result Figure 13 and figure 14 show the implementation result using spectrum analyser. The passband edge frequency we chose is (0.4, 0.6), that is 0.4 * fn = 0.4 * 48 khz / 2 = 9.6 khz 0.6 * fn = 0.6 * 48 khz / 2 = 14.4 khz. That is nearly the same as the measured value. The difference is due to the not precise measurement. After scaling the maximum magnitude should be 1, namely 0 db, but the figure 15 shows the maximum magnitude is about -32dB. This is because of the Codec attenuation. The magnitude of Codec between frequency 0 and 22 khz is nearly -32 db. The passband ripple is 3 db getting from figure 15 and figure 16 which is fulfilled the specification. Figure 13 Measured frequency response of IIR filter (1) 19

20 Figure 14 Measured frequency response of IIR filter (2) Figure 15 Measured frequency response of IIR filter (3) 20

21 Figure 16 Measured frequency response of IIR filter (4) Figure 17 timing simulaton diagram of step response 21

22 The figure 17 shows the simulation diagram of step response (comparing with figure 5). 22

23 4. Conclusion In this lab, a parallel IIR chebyshev type I bandpass filter which has 6 th order was developed. The cascade parallel structure was used to realize the 6 th order filters, and each substructure represents 2 order filter. The matlab program was used to calculate the coefficients of each substructure. During the implementation only one SOS is developed, because each SOS is nearly the same except the different coefficients. 6 th order filter is realized by just instancing the SOS for three times. This way simplifies the development, since only one SOS is coded. The fixed-point implementation is chosen.the scaling using chebyshev norm was used to make output adder overflow free. One guard bit is added which is proved to be enough during the lab to avoid the internal adders overflow. The internal signals vector width with 17 bit was used at first. The result of IIR filter was good, then 13 bit, even 10 bit was tried which worked still good. 5. Reference Prof. Dr. B. Schwarz Script of DSP with FPGAs Script of Digital Systems

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