Cypress Semiconductor Qualification Report
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1 Cypress Semiconductor Qualification Report QT# VERSION 1.0 September, 1997 ATM-SONET/SDH TRANSCEIVER CY7C955
2 Cypress Semiconductor QT# 97105, V. 1.0 ATM-SONET/SDH Transceiver age 2 of 6 ackage: QF RODUCT DESCRITION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied: Marketing art #: ackage: Device Description: Cypress Division: CY7C pins QF ATM-SONET/SDH Transceiver Cypress Semiconductor Corporation - DCD Division Overall Die (or Mask) REV Level (pre-requisite for qualification): Rev. A Die Size (stepping): 306 mils x 288 mils What ID markings on Die: 7C955A TECHNOLOGY/FAB ROCESS DESCRITION Number of Metal Layers: 2 Metal Composition: Metal 1: 500A Ti/1,200A TiW/6,000A Al/1,200A TiW Metal 2: 1,500A TiW/10,000A Al/150A Ti assivation Type and Materials: Free hosphorus contents in top glass layer(%): Die Coating(s), if used: N/A 7,000A TEOS + 6,000A Oxynitride None Number of Transistors in device: 150,00 Number of Gates in device: 30,000 Generic rocess Technology/Design Rule (µ-drawn): CMOS, Single oly, Double Metal /0.65 µm Gate Oxide Material/Thickness (MOS): SiO2 / 145A Name/Location of Die Fab (prime) Facility: Die Fab Line ID/Wafer rocess ID: Cypress Semiconductor - Bloomington, MN L27/F3
3 Cypress Semiconductor QT# 97105, V. 1.0 ATM-SONET/SDH Transceiver age 3 of 6 ackage: QF LASTIC ACKAGE/ASSEMBLY DESCRITION ackage Outline, Type, or Name: 128-pin QF Mold Compound Name/Manufacturer: Sumitomo M-8000CH Lead Frame material: Copper Lead Finish, composition: Solder lated, 85%Sn, 15%b Die Attach Area lating: Silver Spot Die Attach Method: aste Die Attach Material: Silver Epoxy Wire Bond Method: Thermosonic Wire Material/Size: Gold / 1.3 mil JESD22-A112 Moisture Sensitivity Level Level 3 Assembly Line ID and rocess ID: Anam, Korea Note: lease contact a Cypress Representative for other packages availability.
4 Cypress Semiconductor QT# 97105, V. 1.0 ATM-SONET/SDH Transceiver age 4 of 6 ackage: QF RELIABILITY TESTS ERFORMED Stress/Test High Temperature Operating Life Early Failure Rate High Temperature Operating Life Latent Failure Rate Test Condition (Temp/Bias) Dynamic Operating Condition, Vcc = 6.5V, 125 C Dynamic Operating Condition, Vcc = 6.5V, 125 C Result /F Read and Record Life Test Dynamic Operating Condition, Vcc = 6.5V, 125 C High Temperature Steady State Life Static Operating Condition, Vcc = 5.5V, 150 C High Accelerated Saturation Test (HAST) 140 C, 85%RH, 5.5V recondition: JESD22 Moisture Sensitivity Level 3 (192 Hrs, 30/60%RH) Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65 C to 150 C recondition: JESD22 Moisture Sensitivity Level 1 (192 Hrs 30/60% RH ) High Temp Storage 165 C, no bias Electrostatic Discharge Human Body Model (ESD-HBM) Electrostatic Discharge Charge Device Model (ESD-CDM) MIL-STD-883, Method Cypress Spec ,400V 1,000V Latchup Sensitivity In accordance with JEDEC 17. Cypress Spec Static Latch-up Dynamc Latch-up 7.7V 9.0V
5 Cypress Semiconductor QT# 97105, V. 1.0 ATM-SONET/SDH Transceiver age 5 of 6 ackage: QF RELIABILITY FAILURE RATE SUMMARY Stress/Test Device Tested/ Devive Hours # Fails Activation Energy Thermal AF 3 Failure Rate High Temperature Operating Life Early Failure Rate High Temperature Operating Life 1,2 Long Term Failure Rate 1,238 Devices 0 N/A N/A 0 M 105,000 DHRs FIT 1 Assuming an ambient temperature of 55 C and a junction temperature rise of 15 C. 2 Chi-squared 60% estimations used to calculate the failure rate. 3 Thermal Acceleration Factor is calculated from the Arrhenius equation AF = exp E k A 1 T T1 where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 ev/kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions.
6 Cypress Semiconductor QT# 97105, V. 1.0 ATM-SONET/SDH Transceiver age 6 of 6 ackage: QF RELIABILITY TEST DATA QT#: DEVICE ASSY-LOC FABLOT# ASSYLOT# DURATION S/S REJ FAIL MODE ==================== ======== ======== ============== ======== ==== === ================================ STRESS: HIGH TEM DYNAMIC OERATING LIFE-EARLY FAILURE RATE (125C, 6.5V) CY7C955-NC KOREA-Q CY7C955-NC KOREA-Q CY7C955-NC KOREA-Q STRESS: ESD-CHARGE DEVICE MODEL (1,000V) CY7C955-NC KOREA-L COM 3 0 STRESS: ESD-HUMAN BODY CIRCUIT ER MIL STD 883, METHOD 3015 (4,400V) CY7C955-NC KOREA-L COM 3 0 STRESS: HI-ACCEL SATURATION TEST (140C, 5.5V), RECOND. 192 HRS 30C/60%RH CY7C955-NC KOREA-Q CY7C955-NC KOREA-Q STRESS: HIGH TEM STEADY STATE LIFE TEST (150C, 5.5V) CY7C955-NC KOREA-L CY7C955-NC KOREA-L STRESS: HIGH TEM DYNAMIC OERATING LIFE-LATENT FAILURE RATE (125C, 5.5V) CY7C955-NC KOREA-Q CY7C955-NC KOREA-Q EOS CY7C955-NC KOREA-Q EOS STRESS: READ & RECORD LIFE TEST (125C, 6.5V) CY7C955-NC KOREA-Q CY7C955-NC KOREA-Q CY7C955-NC KOREA-Q STRESS: TC COND. C, -65 TO 150C, RECOND. 192 HRS 30C/60%RH CY7C955-NC KOREA-Q CY7C955-NC KOREA-L CY7C955-NC KOREA-L CY7C955-NC KOREA-Q CY7C955-NC KOREA-Q
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