High Performance Silicon Gate CMOS

Transcription

1 SEIONUTO TEHNIAL ATA High Performance Silicon Gate OS The 4/74H64 is identical in pinout to the LS64. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs. The 4/74H64 is an 8 bit, serial input to parallel output shift register. Two serial data inputs, A and A2, are provided so that one input may be used as a data enable. ata is entered on each rising edge of the clock. The active low asynchronous eset overrides the lock and Serial ata inputs. Output rive apability: 0 LSTTL Loads Outputs irectly Interface to OS, NOS, and TTL Operating oltage ange: 2 to 6 Low Input urrent: µa High Noise Immunity haracteristic of OS evices In ompliance with the equirements efined by JEE Standard No. 7A hip omplexity: 244 FETs or 6 Equivalent Gates o Not Use for New esig 4 THIS EIE WILL BE SUPEEE BY 4/74H64A IN THE SEON UATE OF J SUFFIX EAI PAAGE ASE N SUFFIX PLASTI PAAGE ASE SUFFIX SOI PAAGE ASE 7A 03 SEIAL ATA INPUTS A A2 LOGI IAGA 2 ATA LO 8 3 A 4 B 6 0 E F 2 G 3 H PAALLEL ATA OUTPUTS OEING INFOATION 4HXXXJ 74HXXXN 74HXXX A A2 A B PIN ASSIGNENT eramic Plastic SOI H G F E ESET ESET 9 PIN 4 = PIN 7 = GN GN 7 8 LO FUNTION TABLE Inputs Outputs eset lock A A2 A B H L X X X L L L H X X No hange H H An Gn H H An Gn = data input An Gn = data shifted from the preceding stage on a rising edge at the clock input. 0/9 otorola, Inc E 7

2 4/74H64 AXIU ATINGS* SymbolÎ Parameter alue Unit ÎÎ Supply oltage (eferenced to GN) 0. to ÎÎ ÎÎ in Input oltage (eferenced to GN). to +. ÎÎ ÎÎ out Output oltage (eferenced to GN) 0. to + 0. ÎÎ I in Input urrent, per Pin ± 20 ma ÎÎ I out Output urrent, per Pin ± 2 ma ÎÎ I Supply urrent, and GN Pi ± 0 ma ÎÎ P Power issipation in Still Air, Plastic or eramic IP 70 mw Î TstgÎÎ SOI Package 00 Storage Temperature 6 to + 0 LÎÎ T Lead Temperature, mm from ase for 0 Seconds (Plastic IP or SOI Package) 260 (eramic IP) * aximum atings are those values beyond which damage to the device may occur. Functional operation should be restricted to the ecommended Operating onditio. erating Plastic IP: 0 mw/ from 6 to 2 eramic IP: 0 mw/ from 00 to 2 SOI Package: 7 mw/ from 6 to 2 For high frequency or heavy load coideratio, see hapter 2 of the otorola High Speed OS ata Book (L29/). EOENE OPEATING ONITIONS Symbol ÎÎ Parameter in ax Unit ÎÎ Supply oltage (eferenced to GN) 6.0 in, out ÎÎ Input oltage, Output oltage (eferenced to GN) 0 TA ÎÎ Operating Temperature, All Package Types + 2 tr, tf ÎÎ Input ise and Fall Time = Î (Figure ) Î = = 6.0 ELETIAL HAATEISTIS (oltages eferenced to GN) Guaranteed Limit to Symbol Parameter Test onditio ÎÎ Unit IH inimum High Level Input Î Î out = 0. or 0. oltage Iout ÎÎ 20 µa... ÎÎ IL aximum Low Level Input Î Î out = 0. or 0. oltage Iout ÎÎ µa 0.9Î OH inimum High Level Output Î Î in = IH or IL oltage Iout 20 µa Î Î Î ÎÎ Î.9.9 in = IH or IL Iout 4.0 ma Iout.2 ma Î ÎÎ OL Î aximum Low Level Output Î in = IH or IL oltage Iout ÎÎ ÎÎ µa in = IH or IL Iout 4.0 ma 0.40 Iout.2 ma ÎÎ 0.40 Iin aximum Input Leakage urrentîî in = or GN 6.0 ± 0. ±.0ÎÎ µa ÎÎ I aximum uiescent Supply in = or GN 6.0 urrent (per Package) Î Iout = 0 µa ÎÎ µa This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GN (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or ). Unused outputs must be left open. NOTE: Information on typical parametric values can be found in hapter 2 of the otorola High Speed OS ata Book (L29/). OTOOLA 3 2 High Speed OS Logic ata L29 ev 6

3 4/74H64 A ELETIAL HAATEISTIS (L = 0 pf, Input tr = tf = 6 ) Î Guaranteed Limit Î to SymbolÎ Parameter Î Unit fmax Î aximum lock Frequency ( uty ycle) ÎÎ Î ÎÎ Hz (Figures and 4) tplh, aximum Propagation elay, lock to Î ÎÎ tphl (Figures and 4) Î 37 4 tphl aximum Propagation elay, eset to ÎÎ (Figures 2 and 4) ÎÎ ttlh, Î aximum Output Traition Time, Any Output Î tthl (Figures and 4) Î aximum Input apacitance 0 0 ÎÎ 0 pf in NOTES:. For propagation delays with loads other than 0 pf, see hapter 2 of the otorola High Speed OS ata Book (L29/). 2. Information on typical parametric values can be found in hapter 2 of the otorola High Speed OS ata Book (L29/). 2, =.0 P Power issipation apacitance (Per Package)* 40 pf * Used to determine the no load dynamic power coumption: P = P 2 f + I. For load coideratio, see hapter 2 of the otorola High Speed OS ata Book (L29/). TIING EUIEENTS (Input tr = tf = 6 ) Guaranteed Limit to Symbol Parameter Unit Î tsu inimum Setup Time, A or A2 to lock Î (Figure 3) ÎÎ th Î inimum Hold Time, lock to A or A2 (Figure 3) 6.0 trec inimum ecovery Time, eset Inactive to lock Î (Figure 2) 6.0 Î tw inimum Pulse Width, lock (Figure ) Î ÎÎ tw Î inimum Pulse Width, eset ÎÎ (Figure 2) tr, Î tf aximum Input ise and Fall Times Î (Figure ) NOTE: Information on typical parametric values can be found in hapter 2 of the otorola High Speed OS ata Book (L29/) High Speed OS Logic ata L29 ev OTOOLA

4 4/74H64 PIN ESIPTIONS INPUTS A, A2 (Pi, 2) Serial ata Inputs. ata at these inputs determine the data to be entered into the first stage of the shift register. For a high level to be entered into the shift register, both A and A2 inputs must be high, thereby allowing one input to be used as a data enable input. When only one serial input is used, the other must be connected to. lock (Pin 8) Shift egister lock. A positive going traition on this pin shifts the data at each stage to the next stage. The shift register is completely static, allowing clock rates down to in a continuous or intermittent mode. OUTPUTS A H (Pi 3, 4,, 6, 0,, 2, 3) Parallel Shift egister Outputs. The shifted data is presented at these outputs in true, or noninverted, form. ONTOL INPUT eset (Pin 9) Active Low, Asynchronous eset Input. A low voltage applied to this input resets all internal flip flops and sets Outputs A H to the low level state. SWITHING WAEFOS LO tr 90% 0% t w tf GN ESET tphl tw GN 90% 0% /fmax tplh tphl ttlh tthl trec LO GN Figure. Figure 2. TEST POINT A O A2 LO tsu ALI th GN GN EIE UNE TEST OUTPUT L* * Includes all probe and jig capacitance Figure 3. Figure 4. Test ircuit OTOOLA 3 4 High Speed OS Logic ata L29 ev 6

5 4/74H64 EXPANE LOGI IAGA LO 8 A A2 2 ESET A B E F G H TIING IAGA LO A A2 ESET A B E F G H High Speed OS Logic ata L29 ev 6 3 OTOOLA

6 4/74H64 -B- -T- SEATING PLANE A- OUTLINE IENSIONS J SUFFIX EAI IP PAAGE ASE ISSUE Y F G N 4 PL J 4 PL 0.2 (0.00) T A S 0.2 (0.00) T B L S NOTES:. IENSIONING AN TOLEANING PE ANSI Y, ONTOLLING IENSION: INH. 3. IENSION L TO ENTE OF LEA WHEN FOE PAALLEL. 4. IESNION F AY NAOW TO 0.76 (0.030) WHEE THE LEA ENTES THE EAI BOY. I A B F G J L N INHES IN AX BS BS ILLIETES IN AX BS BS A F H G N B SEATING PLANE N SUFFIX PLASTI IP PAAGE ASE ISSUE L L J NOTES:. LEAS WITHIN 0.3 (0.00) AIUS OF TUE POSITION AT SEATING PLANE AT AXIU ATEIAL ONITION. 2. IENSION L TO ENTE OF LEAS WHEN FOE PAALLEL. 3. IENSION B OES NOT INLUE OL FLASH. 4. OUNE ONES OPTIONAL. INHES ILLIETES I IN AX IN AX A B F G 0.00 BS 2.4 BS H J L BS 7.62 BS N SEATING PLANE 4 A 7 G 8 B P 7 PL 4 PL 0.2 (0.00) T B S A S SUFFIX PLASTI SOI PAAGE ASE 7A 03 ISSUE F 0.2 (0.00) B X 4 J F NOTES:. IENSIONING AN TOLEANING PE ANSI Y, ONTOLLING IENSION: ILLIETE. 3. IENSIONS A AN B O NOT INLUE OL POTUSION. 4. AXIU OL POTUSION 0. (0.006) PE SIE.. IENSION OES NOT INLUE ABA POTUSION. ALLOWABLE ABA POTUSION SHALL BE 0.27 (0.00) TOTAL IN EXESS OF THE IENSION AT AXIU ATEIAL ONITION. I A B F G J P ILLIETES IN AX BS 0.00 BS INHES IN AX OTOOLA 3 6 High Speed OS Logic ata L29 ev 6

7 4/74H64 otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters can and do vary in different applicatio. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any licee under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use otorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUOPE: otorola Literature istribution; JAPAN: Nippon otorola Ltd.; Tatsumi SP JL, Toshikatsu Otsuki, P.O. Box 2092; Phoenix, Arizona F Seibu Butsuryu enter, Tatsumi oto u, Tokyo 3, Japan FAX: FAX0@ .sps.mot.com TOUHTONE (602) HONG ONG: otorola Semiconductors H.. Ltd.; 8B Tai Ping Industrial Park, INTENET: NET.com Ting ok oad, Tai Po, N.T., Hong ong High Speed OS Logic ata L29 ev 6 OELINE 4/74H64/ 3 7 OTOOLA

8 This datasheet has been download from: atasheets for electronics components.