Hugh de Lacy - Technical Manager Alun Jones Technical Director Micross Components Ltd., Given at CMSE, Portsmouth 2008

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1 Shrinking Silicon Feature Sizes Consequences for Reliability Hugh de Lacy - Technical Manager Alun Jones Technical Director Micross Components Ltd., Given at CMSE, Portsmouth

2 The Incredible Shrinking Die 2

3 Effects of Size Reduction Increasing Parameter Variability Wear-out Mechanisms parameter degradation catastrophic Increased Susceptibility to Radiation catastrophic hard / recoverable soft errors 3

4 Parameter Variability Static Mean Number of Dopan nt Atoms Technology Node (nm) Random Dopant Fluctuations Source: Intel 4

5 Parameter Variability Static 1 Source: Mark Bohr, Intel 1000 micron nm 180nm 130nm 248nm 90nm 65nm 193nm Lithography Wavelength Gap nm Generation 45nm 32nm 13nm EUV Sub-wavelength Lithography 10 Source: Intel 5

6 Parameter Variability Dynamic Heat Flux (W/cm2) Heat Flux (W/cm 2 ) Vcc variation Source: Intel 6

7 Parameter Variability Mitigation Maximise symmetry of layout distribute power dissipating elements include dummy features Advanced lithography techniques pattern compensation at design stage alternating phase shift masks Self compensating system design feedback loops to optimise supply voltage, clock speed 7

8 Parameter Variability Layout Symmetry Source: Intel Dummy features reduce leakage Source: Chip Forensics 8

9 Parameter Variability Advanced Lithography Design Compensation Source: Intel Source: ASM Alternating Phase Shift Mask 9

10 Parameter Variability Self Compensation Use of error correction techniques established for memory components now being adopted for logic devices Some techniques apply feedback to adjust supply voltage and clock speed to minimise errors 10

11 Wear-Out Mechanisms Supply voltages progressively reduced but reduction doesn t fully scale with dimensions Electromigration of metals Parameter degradation and catastrophic Hot carrier effects Parameter degradation Time dependent dielectric breakdown Catastrophic 11

12 Electromigration Caused by transfer of electron momentum to metal lattice Use of Cu has reduced electromigration by x10 but wire density greatly increased (5-7 layers common) Avoidable with correct design rules Void caused by electromigration Source: JEDEC 12

13 Hot Carrier Effects Carriers accelerated by high field in MOSFET drain region Some carriers penetrate gate oxide and are trapped Changes Vth and gm, increases gate leakage Carriers that are not trapped contribute to gate leakage or substrate current Worst at low temp (activation energy 0.1 to 0.2eV) 13

14 Time dependent dielectric breakdown (TDDB) Breakdown of MOSFET gate insulation Two different effects Field-enhanced thermal bond breakage of SiO2/Si bonds, occurs at lower field strengths Tunnelling current through dielectric causes impact ionisation damage, worse at higher fields Recent adoption of high-k dielectrics has improved situation 14

15 TDDB Gate Oxide Thickness Trend (SiOn) Source: Intel 15

16 TDDB Intel High K Dielectric Source: Intel 16

17 Radiation Effects Ionising radiation occurs from several natural sources The most important for ground-based electronics are: Cosmic rays, mainly neutrons Alpha particles from packaging materials Effects can be transient or catastrophic 17

18 Radiation Effects Terminology SEE single event effects Transient effects caused by random individual particle interactions SEU single event upset Transient which causes one-off effect that may corrupt data but does not halt operation of device or cause long term damage (soft error) SEL single event latch-up Transient that causes latch-up that halts operation of device until power is removed. May cause destruction of device if excessive currents flow 18

19 Radiation Effects Cosmic Rays Characteristics of cosmic neutron flux Source: Cypress 19

20 Radiation Effects Cosmic Rays High energy neutron Elastic collision: no electrical effect Silicon nucleus recoil (~2µm) Source: TI 20

21 Radiation Effects Cosmic Rays Inelastic collision: charged particles created Source: TI 21

22 Radiation Effects Cosmic Rays Source: Actel 22

23 Radiation Effects Alpha Particles Derive from trace radioactive elements in package materials Sources include: Ceramic package materials, aluminum IC interconnect, and lead in solder bump material. Ceramic package contamination due to uranium and thorium impurities in package material and lid attach glass. Aluminium contamination due to uranium and thorium impurities in aluminium ore. Lead contamination due to uranium and thorium impurities in lead ore including the radioactive lead decay products 210Pb and 212Pb 23

24 Radiation Effects Alpha Particles Typical Alpha Flux in IC Materials (α/cm 2 -hr) Processed wafers Copper interconnect metal Aluminum interconnect metal Mold compound <0.002 Underfill Lead solder bumps <0.002 Ceramic package

25 Radiation Effects Device Sensitivity Error rate = F x A x exp(-q crit /Q s ) F: neutron flux, A: area, Q crit : min charge to produce soft error, Q s : charge collection efficiency of device Sensitivity tends to increase linearly with decreasing feature size SRAM most sensitive (<5fC for 45nm 6 transistor SRAM cell with 1µm 2 area) Error correction used in µp cache memory DRAM: depends on size of capacitor 3D structures have increased capacitance Random logic becoming more sensitive as geometries reduce and architectures change 25

26 Radiation Effects SRAM Sensitivity Trends Source: TI BPSG: borophosphosilicate glass 26

27 Radiation Effects DRAM Sensitivity Trends Source: TI 27

28 Radiation Effects Logic Sensitivity Combinational logic: effects of masking Logical masking occurs when a particle strikes a portion of the combinational logic that is blocked from affecting the output due to a subsequent gate whose result is completely determined by its other input values. Electrical masking occurs when the pulse resulting from a particle strike is attenuated by subsequent logic gates due to the electrical properties of the gates to the point that it does not affect the result of the circuit. Latching-window masking occurs when the pulse resulting from a particle strike reaches a latch, but outside the clock transition where the latch captures its input value 28

29 Radiation Effects Logic Sensitivity Source: Univ Texas / IBM Error rate = F x A x exp(-q crit /Q s ) 29

30 Size Reduction Effects on Reliability Other things being equal, reducing size tends to reduce reliability, but: Authoritative data lacking, some data conflicting Depends on design rules Can be greatly influenced by system design Newer process technologies mitigate worst effects 30

31 Reliability Published Data FIT Rates at 85 C vs Feature Size 1000 FITs Actel Altera ADI Xilinx Feature Size µm 31

32 Reliability Recommendations for Specifiers Standard devices Obtain reliability data from manufacturers (including typical failure modes) Use older generation parts where practicable Design tolerance and redundancy into system Custom devices Obtain reliability data Use conservative design rules Design in error correction if practicable Comprehensive testing Rigorous qualification procedures 32

1.1 Silicon on Insulator a brief Introduction

Table of Contents Preface Acknowledgements Chapter 1: Overview 1.1 Silicon on Insulator a brief Introduction 1.2 Circuits and SOI 1.3 Technology and SOI Chapter 2: SOI Materials 2.1 Silicon on Heteroepitaxial