Layout Design. Lecture Fall Textbook: Design Methodology Insert A

Transcription

1 Layout Design Lecture Fall 2003 Textbook: Design Methodology Insert [Portions adapted from J. P. Uyemura Introduction to VLSI Circuits and Systems, Wiley 2001.]

2 Roadmap Today: Basic CMOS Layout: design in the small Thursday: Layout Verification & design in the large Next week: Transistor sizing Wires Homework 1: Due Thursday Homework 2: Out Thursday Lab 2: This week

3 Today s Overview Physical structure of ICs Design rules Basic gates layout Stick diagrams Basic rules Examples Cadence (Virtuoso)

4 Review: MOSFETs Gate (G) No connection Source Drain Open switch G = 0 Gate layer Conduction layer Source layer Drain layer Closed switch G = 1 G is responsible for the absence or presence of the conduction region between the drain and the source regions

5 Review: Controlling Current Flow (nfet) V G source diff 0V n+ n+ L No electrons p insulator drain diff W L n+ n+ Side view Top view + electron channel n+ n+ electrons n+ n+ p

6 Review: Manufacturing 2D top-down view How design engineers see the chip. 3D cross-section view How process engineers see the chip.

7 Design Rules Interface between designer and process engineer Clean separation between the process during wafer fabrication and the design effort Permissible geometries -> DESIGN RULES Width rule, space rule, overlap rule, etc. Ways to do design rules Scalable Design Rules bsolute measures

8 Scalable Design Rules CMOS scales Implement something now, shrink it later Express all design rules in terms of a unit dimension Change the actual dimension of the unit, and the whole design shrinks Mead and Conway Unit dimension: Minimum line width (2λ) In 1978, λ = 1.5 µm (a.k.a. 3 micron technology) In 2003, λ = µm (a.k.a micron technology) Important Intellectual idea, not used in industry (but we will)

9 Transistor Layout poly Transistor L 1 3 W 2 The choice of geometry determines transistor parameters! 5 Well boundary ll distances are expressed in λ

10 Transistor Layout 5λ Non-catastrophic misalignment λ 4λ λ W 2λ 2λ Source Source to gate shortcirc 2λ L 2λ Drain S = D =5λW λ = 0.5µm -> = 12.5µm 2

11 bsolute Design Rules It is hard to scale every aspect of design linearly The elegance of scalable CMOS isn t worth the cost Specify all dimensions in real units (µm or nm) Currently (0.13 micron), there are THOUSNDS of design rules

12 CMOS Process Layers Layer Well (p,n) ctive rea (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

13 Inverters V DD V DD V DD V in V out V in V out V in V out GND GND Layout of a NOT gate GND lternate layout of a NOT gate Transistor sizing determines inverter fundamental properties!

14 Series/Parallel Connections n+ n+ n+ B B n+ n+ n+ B n+ n+ n+ p Devices can share patterned regions; this may reduce the layout area or complexity! X B X X X B X poly Red n+/p+ Green metal Blue Y Y X contact Black

15 NND2 V DD V DD NOT(B) B NOT(B) B GND GND

16 Question: How bout ND2? V DD V DD V DD NOT(B) B NOT(B) and B B GND GND GND

17 NOR2 V DD V DD NOT(+B) B NOT(+B) B GND GND The output here is connected to one p-trans drain and two n-trans drains.

18 NOR2 (alternate layout) V DD V DD NOT(+B) B NOT(+B) B GND GND The output here is connected to one p-trans drain and one n-trans drain. This is better! Less drain area connected to the output. This results in a faster gate.

19 Complex Logic Gates: OI Gates #1 #2 2 2 B C D F B C D B C D F= NOT((B+C+D)) 1 1

20 OI Gates: Sharing S/D (option 1) 2 B C D 1 B C D

21 OI Gates: Sharing S/D 2 V DD B C D 1 GND B C D

22 OI Gates: Sharing S/D 2 V DD B C D 1 F GND The output here has four output drain capacitances. B C D

23 Capacitance: Friend or Foe??? Foe: Slows down the output: Big Capacitance More charge to to change voltage SLOWER! Friend: Stabilizes the Power Supply Big Capacitance More charge to to change voltage More stable supply voltage!

24 OI Gates: Sharing S/D (option 2) #2 2 B C D 1 B C D

25 OI Gates: Sharing S/D 2 V DD B C D F 1 GND B C D

26 OI Gates: Sharing S/D V DD V DD F F B C D Wrong GND The output here has two output drain capacitances. B C D Right GND

27 Gate Design Procedure Run VDD and GND in metal at top and bottom Run vertical poly for each gate input Order gates to allow maximum source-drain abutting Place max number of n-diffusions close to GND Place max number of p-diffusions close to VDD Make remaining connections with metal Minimize metal usage

28 Question: How bout TGs?

29 Overview Physical structure of ICs Design rules Basic gates layout Stick diagrams Basic rules Examples Cadence (Virtuoso)

30 Stick Diagrams Introduced by Mead & Conway in the 80s Every line of a conduction material layer is represented by a line of a distinct color

31 nfet and pfet Representations

32 Basic Rules (1)

33 Basic Rules (2)

34 Basic Rules (3)

35 Logic Gates Design

36 Examples

37 Complex Functions OUT = BC + D V DD VDD B C X X X X X D OUT OUT X X X B C D GND C B D

38 Summary Discussed Design rules Basic gates layout Stick diagrams Need more practice on Stick diagrams Layout (mostly in the lab)

39 Preview: The Flow Boolean function Transistor Schematic 1st part of the Thursday s Lecture Schematic Simulation Layout (w/ DRC) LVS Check Extracted Simulation Component Design

40 Preview: Modern SIC Design Designer Productivity is a big problem In 1978, people could draw transistors, now there are 100s of millions per chip New abstractions necessary: Masks Design Rules Layout Design Cell Libraries Std Cell Design