DESIGN AND PERFORMANCE ANALYSIS OF CMOS FULL ADDER WITH 14 TRANSISTOR

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1 DESIGN AND PERFORMANCE ANALYSIS OF CMOS FULL ADDER WITH 14 TRANSISTOR 1 Ruchika Sharma, 2 Rajesh Mehra 1 ME student, NITTTR, Chandigarh,India 2 Associate Professor, NITTTR, Chandigarh,India 1 Abstract Full adders are important components used in VLSI. In most of the systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the building block of the adder that is the 1-bit full adder cell is a significant goal. The low power VLSI demand has been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet this growing demand, various new low power adder cells have been designed by sacrificing the MOS Transistor count that considerably increases the speed and decreases the power and reduces the serious threshold loss problem. In this paper, 14 transistors full adder is designed and results shows that this adder consume less power with very less delay and threshold loss problem. Keywords Arithmetic circuit, full adder, low power, very large-scale integration (VLSI) 1. Introduction With the advance of VLSI technology, to either speed up the operation or reduce the power/energy consumption hardware implementation of many applications such as multimedia processing, digital communication can be possible. The essence of the approximately all digital computing lies in the full adder design. Transistor count which is of course of a primary concern largely affects the design complexity of many function units such as multiplier and algorithmic logic unit (ALU). Two other important conflicting design parameters are power consumption and speed. A better metric to indicate the optimal design tradeoffs would be the power delay product or energy consumption per operation. Related to the power consumption is the lowest supply voltage in which the design can still operate properly. Numbers of full adders designed [1] [8] in the categories of static CMOS, transmission gate, dynamic circuit and pass transistor logic have been presented in the literature. The 28 transistors full adder design in static CMOS with complementary pull-up P-type MOSFET and pull-down N- Type MOSFET networks is the most conventional one. But at circuit level, an optimized design is desirable having less numbers of transistors, small power consumption and reduces delay. Therefore different types of less transistor full adder have been designed in order to achieve all these requirements like novel architectures such as CMOS Transmission Gate (TG), Pass-Transistor Logic (PTL), Complementary Passtransistor Logic (CPL), Dual rail domino logic and Gate Diffusion Input (GDI), but all the types have their own advantages and disadvantages. Many low-power adders using various pass transistors, such as the SERF [6,7] Compared to the complementary static CMOS adders, such low-power adders have the problem of threshold loss. In the threshold problem, the logic value 1 is not the value of Vdd and the logic value 0 may not be the value of 0. This kind of threshold-loss logic gates may not be used as widely as the complementary static CMOS gates. Some of these less transistors full adder do not provide accurate result for some input combinations and some adder s designs are not practically realizable. So in this paper 14- transistor full adders is designed and analysed with other types of reduced transistor adders to give an idea of best Adder for different applications in terms of delay, power, area and with lesser threshold loss. 2. Full adder designs The most commonly used adder with complementary pull-up pmos and pull-down nmos networks in digital circiuts is conventional 28 transistor full adder. A complementary static CMOS full adder circuit consists of an NMOS pull down network connecting the ground to the output and a dual PMOS 1461

2 pull up network connecting the power to the output. This adder implements the following Boolean equations: CARRY = A.B + B.Cin + A.Cin.. 1 SUM = A.B.Cin + CARRY (A + B + Cin).. 2 This complementary static CMOS full adder circuit requires 28 transistors as shown in fig transistors full adder has been designed using six multiplexers and 12 transistors and each multiplexer is implemented by pass- transistor logic with two transistors. As shown in Fig. 3, in this circuit there is no VDD or GND connection and there are some circuit paths which contain three transistors connected in series which causes to increase delay of producing SUM signal. To balance the output and to optimize the circuit for Power delay product, the size of each transistor in that path should be three times larger which will therefore increases the area of the circuit. Fig.1 28 transistor full adder 20 transistor full adder was designed using a transmission gate plus inverter [9]. Transmission gate produces buffered outputs for both sum and carry with proper polarity. In this circuit 2 inverters are followed by two transmission gates which act as 8- transistor XOR. 4 transistor XOR which in the next stage is inverted to produce XNOR. These XOR and XNOR are used to generate sum and cin and Cin are multiplexed which can simultaneously used to generate sum and cout. The power dissipation in this circuit is more than the 28 Transistors adder. However with same power consumption it performs faster. The circuit diagram for 20T full adder is shown in Fig.2 Fig transistors full adder [9] The 16 transistors full adder called transmission-function full adder (TFA) [10] is illustrated in Fig.4. It consists of 16 transistors. The XOR circuit used in the design requires one of its two inputs in complementary forms. So, an additional inverter is required, which leads to a 6-transistor XOR design. For this circuit there are two possible short circuits paths to ground. This design uses pull-up and pull-down logic as well as complementary pass Logic to drive the load and it gives the same delay for sum and carry. Fig.2 20 transistor full Adder[9] Fig. 4 Transmission function 16T full adder [10] 1462

3 Full adder using 10 transistors are named as SERF, 9A, 9B and 13A. But the design, denoted as SERF (static energy recovery full adder) [6, 10], is more popular and give more importance to the low power consumption. As shown in Fig. 5, it uses two 4-transistor XNOR circuits and one 2-to-1 multiplexer. In non energy recovery design, during the logic level high the charge applied to the load capacitance is drained to ground during logic level low. The Static Energy Recovery Full adder has no direct path to the ground, so the elimination of that direct path to ground reduces power consumption and removing the short circuit from the power. The charge stored at the load capacitance is reapplied to the control gates. These both combination of not having a direct path to ground and re-application of the load charge to the control gate makes the energy recovering full adder an energy efficient design but gate in order to improve the threshold loss problem. Design of 4 transistor XOR gate is shown in fig.6 In this XOR gate circuit, when A=B=0, transistor P1 and P2 will be on and Transistor N1 and N2 will be off. Therefore low input at input B will pass through transistor P2 and we get low signal at the output. When A=0 and B=1, transistor N1 and P2 will be on and Transistor P1 and N2 will be off. Therefore high input at input B will pass through transistor P2 and we get high signal at the output. Fig 6 Circuit diagram for 4T XOR gate Fig.5 10T SERF full adder design [9] When A=1 and B=0, transistor N2 and P1 will be on and Transistor P2 and N1 will be off. At the output we get high signal from Input A through transistor P1 and N2. When A=1 and B=1, transistor N1 and N2 will be on and transistor P1 and transistor P2 will be off, thus we get low signal at the output. Circuit diagram for 14 transistor full adder circuit using 4 transistor XOR gate is as shown below in fig. 7 and the schematic diagram for is shown in fig. 8 it has the threshold loss problem. Also this circuit produces full-swing at the output nodes, but it face problem to provide full swing for the internal nodes. The circuit becomes slower with decrease in the circuit power consumption. Also it cannot be cascaded at low power supply due to multiple threshold problems. Other 10 Transistor Full adders are derived from a systematic exploration of circuit combinations from various XOR/XNOR gates and 2-to-1Multiplexer. The circuit for the 10 transistor SERF full adders is shown in fig Design simulation of 14 transistors full adder 14 Transistors adder cell need only 14 transistors to realize the full adder function. By sacrificing four extra transistors per adder cell as compared to SERF, it produces the better result in threshold loss, speed and power. The threshold loss problem is reduced in this adder design, which exists in the SERF by inserting the inverter between XOR Gate outputs which will form XNOR gate.. The design of 14 transistors full adder uses 4 transistors XOR gate same as SERF for its operation with additional inverter circuit at the output of XOR Fig 7 Circuit diagram for 14T full adder [11] 1463

4 4. Result Analysis In this paper 14 transistors full adder is designed and simulated. The conventional full adder has the advantage of very low power consumption. However, it has as many as 28 transistors and thus requires considerable chip area for its implementation. 20 transistors and 16 transistors full adder further decreases the power and delay but again require more area for its implementation. Fig 8 Schematic for 14 transistor full adder The Schematic of proposed design has been developed using Cadence Virtuoso Schematic Editor and simulated with Cadence Virtuoso Analog Design Environment. All the circuits were implemented using cadence virtuoso 180nm technology. After Simulation the output waveform for the 14 transistor full adder is shown below in fig 9 and the output power waveform is shown in Fig. 10. The speed, area and power for 14 transistors full adder is shown in table 1. The static energy recovery full adder based on pass transistor logic use as few as ten transistors and claimed superior in energy consumption, but the its design is relatively slower than its peer designs and hence is not suitable for high speed architectures. All 10 transistor full adders have very less power and delay and also lesser area but such low-power adders suffers from severe threshold loss problem, i.e., the logic value 1 is not the value of Vdd and the logic value 0 may not be the value of 0. So, it cannot operate properly when cascaded under low supply voltage and this kind of thresholdloss logic gates may not be used as widely as the complementary static CMOS gates. This 14 transistor full adder has very less threshold loss problem and high speed with considerably low power. 5. Conclusion The performance of many larger circuits basically depends upon the performance of the full adder circuits that have been used. So, the 14 transistor full adder circuit is a good option to build the large systems and circuits with low power consumption and area. Based on analysis 14 transistor full adder has lesser delay, power, area and better accuracy. With the help of this 14T adder cell, we can design an efficient and high performance multiplier unit. In future, this kind of low power and high speed adder cell will be used in designing the various digital circuits with lesser area and hence less power and delay which is main requirement of any digital circuit. Fig 9 Output waveform for 14 transistor full adder References Fig. 10 Power waveform for 14 transistors full adder TABLE 1 Simulation results of 14 Transistors full adder Parameter Post design Result Power(μW) 8.91 Delay (ns) 6.2 [1] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A System Perspective. Reading, MA: Addison-Wesley, [2] N. Zhuang and H. Wu, A new design of the CMOS full adder, IEEE Journal Solid-State Circuits, Vol. 27, no. 5, pp , May [3] J. Wang, S. Fang, and W. Feng, New efficient designs for XOR and XNOR functions on the transistor level, IEEE Journal Solid- State Circuits, Vol. 29, no. 7, pp , Jul [4] E. Abu-Shama and M. Bayoumi, A new cell for low power adders, in Proceedings International Midwest Symposium Circuits Systems, pp ,

5 [5] A. M. Shams and M. Bayoumi, A novel high-performance CMOS 1-bit full adder cell, IEEE Transaction Circuits System II, Analog Digital Signal Process., Vol. 47, no. 5, pp , May [6] R. Shalem, E. John, and L. K. John, A novel low-power energy recovery full adder cell, in Proceedings Great Lakes Symposium VLSI, pp , Feb [7] H. T. Bui, Y. Wang, and Y. Jiang, Design and analysis of lowpower 10-transistor full adders using XOR-XNOR gates, IEEE Transaction Circuits System II, Analog Digit. Signal Process, Vol. 49, no. 1, pp , Jan [8] A. Fayed and M. Bayoumi, A low-power 10-transistor full adder cell for embedded architectures, in Proceedings IEEE Symosium. Circuits System, Sydney, Australia, pp , May [9] M.B. Damle, Dr. S.S Limaye, M.G. Sonwani Comparative Analysis of Different Types of Full Adder Circuits IOSR Journal of Computer Engineering (IOSR-JCE),Volume 11, Issue 3, pp , May. - Jun [10] Jin-Fa Lin, Yin-Tsung Hwang,Ming-Hwa Sheu, Cheng-Che Ho A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design IEEE transactions on circuits and systems I, regular papers, Vol. 54, pp. 5, May [11] T. Vigneswaran, B. Mukundhan, and P. Subbarami Reddy A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem, Journal World Academy of Science, Engineering and Technology, pp ,

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