CPU- Internal Structure

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1 ESD-1 Elettronica dei Sistemi Digitali 1 CPU- Internal Structure Lesson 12 CPU Structure&Function Instruction Sets Addressing Modes Read Stallings s chapters: 11, 9, 10 esd-1-9:10: esd-1-9:10: CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data Registers CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy esd-1-9:10: esd-1-9:10:

2 General Purpose Registers May be General Purpose or Restricted May be used for Data or Addressing Data : Accumulator Addressing : Segment Make them General Purpose Increase flexibility and programmer options Increase instruction size & complexity Make them (specialized) Restricted Smaller (faster) instructions Less flexibility Condition Code Registers Sets of individual bits e.g. result of last operation was zero Can be read (implicitly) by programs e.g. Jump if zero Can not (usually) be set by programs esd-1-9:10: esd-1-9:10: Control & Status Registers Program Counter Instruction Decoding Register Memory Address Register Memory Buffer Register Program Status Word A set of bits Includes Condition Codes Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor esd-1-9:10: esd-1-9:10:

3 CPU : Instruction cycle What is an instruction set? The complete collection of instructions that are understood by a CPU Machine Code Binary Usually represented by assembly codes for human consumption esd-1-9:10: esd-1-9:10: Elements of an Instruction Operation code (Op code) Do this Source Operand reference To this Result Operand reference Put the answer here Next Instruction Reference When you have done that, do this... Instruction Representation In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used e.g. ADD, SUB, LOAD Operands can also be represented in this way ADD A,B esd-1-9:10: esd-1-9:10:

4 Instruction Types Number of Addresses Data processing : Arithmetic and logic Instructions Data storage (main memory) Memory Instruction (main memory) Data movement (I/O) I/O Instructions Program flow control Test and branch Instructions esd-1-9:10: addresses Operand 1, Operand 2, Result a = b + c; Needs very long words to hold everything 2 addresses One address doubles as operand and result a = a + b Requires some extra work (Temporary storage to hold some results) 1 address Implicit second address Usually a register (accumulator) Common on early machines esd-1-9:10: Example Programs for : Y = (A-B) / (C + D x E) Number of Addresses : ZERO 0 (zero) addresses All addresses implicit Uses a stack e.g. : c = a + b push a push b add pop c Note: the JAVA Virtual Machine (JVM) is a stack oriented machine. esd-1-9:10: esd-1-9:10:

5 push a 2 push b 3 sub 4 push c 5 push d 6 push e 7 mul 8 add 9 div 10 pop f How Many Addresses More addresses More complex (powerful?) instructions More registers Inter-register operations are quicker Fewer instructions per program Fewer addresses Less complex (powerful?) instructions More instructions per program Faster fetch/execution of instructions esd-1-9:10: esd-1-9:10: ISA Design Decisions Operation repertoire How many ops? What can they do? How complex are they? Data types Instruction formats Length of op code field Number of addresses Design Decisions (2) Registers Number of CPU registers available Which operations can be performed on which registers? Addressing modes (later ) RISC v CISC esd-1-9:10: esd-1-9:10:

6 Types of Operand Addresses Numbers Integer/floating point Characters ASCII etc. Logical Data Bits or flags(aside: Is there any difference between numbers and characters? Ask a C programmer!) Specific Data Types General - arbitrary binary contents Integer - single binary value Ordinal - unsigned integer Unpacked BCD - One digit per byte Packed BCD - 2 BCD digits per byte Near Pointer - 32 bit offset within segment Bit field Byte String Floating Point esd-1-9:10: esd-1-9:10: Types of Operation Data Transfer Arithmetic Logical Conversion I/O System Control Transfer of Control Data Transfer Specify Source Destination Amount of data May be different instructions for different movements e.g. IBM 370 Or one instruction and different addresses e.g. VAX esd-1-9:10: esd-1-9:10:

7 Arithmetic Add, Subtract, Multiply, Divide Signed Integer Floating point? May include Increment (a++) Decrement (a--) Negate (-a) Logical Bitwise operations AND, OR, NOT esd-1-9:10: esd-1-9:10: Conversion E.g. Binary to Decimal EBCDIC to ASCII Single-precision to double -precision Decimal to packed decimal Input/Output May be specific instructions May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA) esd-1-9:10: esd-1-9:10:

8 Systems Control Privileged instructions CPU needs to be in specific state Ring 0 on Kernel mode For operating systems use Transfer of Control Branch e.g. branch to x if result is zero Skip e.g. increment and skip if zero ISZ Register1 Branch xxxx ADD A Subroutine call esd-1-9:10: esd-1-9:10: SUB CALL : Nested Procedures (1) STACK : Operations and LIFO W/O STACK esd-1-9:10: esd-1-9:10:

9 Typical Stack Organization SUB CALL : Nested Procedures (2) With STACK esd-1-9:10: esd-1-9:10: Byte Order: Endian What order do we read numbers that occupy more than one byte? e.g. (numbers in hex to make it easy to read) can be stored in 4x8bit locations as follows Byte Order (example : # ) Address Value (1) Value(2) i.e. read top down or bottom up? esd-1-9:10: esd-1-9:10:

10 Byte Order Names The problem is called Endian The system on the left has the least significant byte in the lowest address This is called big-endian The system on the right has the least significant byte in the highest address This is called little-endian Standard What Standard? Pentium (80x86), VAX are little-endian IBM 370, Motorola 680x0 (Mac), and most RISC are big-endian Internet is big-endian Makes writing Internet programs on PC more awkward! WinSock provides htoi and itoh (Host to Internet & Internet to Host) functions to convert esd-1-9:10: esd-1-9:10: Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack Immediate Addressing Operand is part of instruction Operand = address field e.g. ADD 5 Add 5 to contents of accumulator 5 is operand No memory reference to fetch data Fast Limited range esd-1-9:10: esd-1-9:10:

11 Immediate Addressing Diagram Direct Addressing Opcode Instruction Operand Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A Add contents of cell A to accumulator Look in memory at address A for operand Single memory reference to access data No additional calculations to work out effective address Limited address space esd-1-9:10: esd-1-9:10: Direct Addressing Diagram Indirect Addressing (1) Opcode Instruction Address A Memory Operand Memory cell pointed to by address field contains the address of (pointer to) the operand Large address space EA = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator Multiple memory accesses to find operand Hence slower esd-1-9:10: esd-1-9:10:

12 Indirect Addressing (2) Indirect Addressing Diagram Large address space 2 n where n = word length May be nested, multilevel, cascaded e.g. EA = (((A))) Draw the diagram yourself Opcode Instruction Address A Memory Pointer to operand Multiple memory accesses to find operand Hence slower Operand esd-1-9:10: esd-1-9:10: Register Addressing Operand is held in register named in address field EA = R Limited number of registers Very small address field needed Shorter instructions Faster instruction fetch No memory access Very fast execution Very limited address space Multiple registers helps performance Requires good assembly programming or compiler writing Register Addressing (2) No memory access Very fast execution Very limited address space Multiple registers helps performance Requires good assembly programming or compiler writing N.B. C programming : register int a; esd-1-9:10: esd-1-9:10:

13 Register Addressing Diagram Register Indirect Addressing Opcode Instruction Register Address R Registers C.f. indirect addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2 n ) One fewer memory access than indirect addressing Operand esd-1-9:10: esd-1-9:10: Register Indirect Addressing Diagram Displacement Addressing Instruction Opcode Register Address R Registers Memory EA = A + (R) Address field hold two values A = base value R = register that holds displacement or vice versa Pointer to Operand Operand Three types Relative Addressing Base-register Addressing Indexing esd-1-9:10: esd-1-9:10:

14 Displacement Addressing Diagram Displacement Address Size? Instruction OpcodeRegister R Address A Registers Pointer to Operand + Memory Operand 30% 25% 20% 15% 10% 5% 0% Int. Avg. FP Avg Address Bits Avg. of 5 SPECint92 programs v. avg. 5 SPECfp92 programs X-axis is in powers of 2: 4 => addresses > 2 3 (8) and 2 4 (16) esd-1-9:10: % of addresses > 16-bits bits of displacement needed esd-1-9:10: Displacement: Relative Addressing A holds displacement R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC c.f locality of reference & cache usage Displacement: Base-Register Addressing A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers in 80x86 EA = A + (R) esd-1-9:10: esd-1-9:10:

15 Displacement: Indexed Addressing A = base R = displacement EA = A + R Good for accessing arrays EA = A + R R++ Stack Addressing Operand is (implicitly) on top of stack e.g. ADD Pop top two items from stack and add esd-1-9:10: esd-1-9:10: Instruction Formats Layout of bits in an instruction Includes opcode Includes (implicit or explicit) operand(s) Usually more than one instruction format in an instruction set Instruction Length Affected by and affects: Memory size Memory organization Bus structure CPU complexity CPU speed Trade off between powerful instruction repertoire and saving space esd-1-9:10: esd-1-9:10:

16 Allocation of Bits Number of addressing modes Number of operands Register versus memory Number of register sets Address range Address granularity Foreground Task QUIZ 3 TAKE-HOME Quiz Visit a manufacturers web site and prepare a document describing the CPU structure and function of a processor (microprocessor, workstation, mainframe) OTHER THAN the 80x86 series of machines esd-1-9:10: esd-1-9:10: CPU : Internal (1) CPU : Internal (2) esd-1-9:10: esd-1-9:10:

17 Examples of Registers Implementation Instruction Cycle (w/ Interrupts) esd-1-9:10: esd-1-9:10: Indirect Cycle Instruction Cycle with Indirect May require memory access to fetch operands Indirect addressing requires more memory accesses Can be thought of as additional instruction subcycle esd-1-9:10: esd-1-9:10:

18 Instruction Cycle State Diagram Data Flow (Instruction Fetch) Depends on CPU design In general: Fetch PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by 1 esd-1-9:10: esd-1-9:10: Data Flow (Data Fetch) Data Flow (Fetch Diagram) IR is examined If indirect addressing, indirect cycle is performed Right most N bits of MBR transferred to MAR Control unit requests memory read Result (address of operand) moved to MBR esd-1-9:10: esd-1-9:10:

19 Data Flow (Indirect Diagram) Data Flow (Execute) May take many forms Depends on instruction being executed May include Memory read/write Input/Output Register transfers ALU operations esd-1-9:10: esd-1-9:10: Data Flow (Interrupt) Data Flow (Interrupt Diagram) Simple Predictable Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded to MAR MBR written to memory PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched esd-1-9:10: esd-1-9:10:

20 Prefetch Fetch accessing main memory Execution usually does not access main memory Can fetch next instruction during execution of current instruction Called instruction prefetch Improved Performance But not doubled: Fetch usually shorter than execution Prefetch more than one instruction? Any jump or branch means that prefetched instructions are not the required instructions Add more stages to improve performance esd-1-9:10: esd-1-9:10: Pipelining is Natural! Sequential Laundry Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 30 minutes Folder takes 30 minutes B C D Stasher takes 30 minutes esd-1-9:10: to put clothes into drawers 79 A T a s k O r d e r A B C D 6 PM AM Time Sequential laundry takes 8 hours for 4 loads esd-1-9:10:

21 Pipelined Laundry: Start work ASAP Why Pipeline? T a s k O r d e r 6 PM AM A B C D Time Pipelined laundry takes 3.5 hours for 4 loads! Suppose we execute 100 instructions Single Cycle Machine 45 ns/cycle x 1 CPI x 100 inst = 4500 ns Multicycle Machine 10 ns/cycle x 4.6 CPI (due to inst mix) x 100 inst = 4600 ns Ideal pipelined machine 10 ns/cycle x (1 CPI x 100 inst + 4 cycle drain) = 1040 ns esd-1-9:10: esd-1-9:10: Pipelining Fetch instruction Decode instruction Calculate operands (i.e. EAs) Fetch operands Execute instructions Write result 6 stage instructions pipeline Overlap these operations esd-1-9:10: esd-1-9:10:

22 Timing of Pipeline Branch in a Pipeline esd-1-9:10: esd-1-9:10: Pipeline Performance Pipeline Speed-Up 1) Cycle Time? = max [? i ] + d =? m + d con i, 1? i? k 2) Total Time T k = [k + (n-1)]? 3) Speed up S k = T 1 /T k = n k? / [k + (n-1)]?= n k / [k + (n-1)] esd-1-9:10: esd-1-9:10:

23 Dealing with Branches Multiple Streams Prefetch Branch Target Loop buffer Branch prediction Delayed branching Multiple Streams Have two pipelines Prefetch each branch into a separate pipeline Use appropriate pipeline Leads to bus & register contention Multiple branches lead to further pipelines being needed esd-1-9:10: esd-1-9:10: Prefetch Branch Target Target of branch is prefetched in addition to instructions following branch Keep target until branch is executed Used by IBM 360/91 Loop Buffer Very fast memory Maintained by fetch stage of pipeline Check buffer before fetching from memory Very good for small loops or jumps c.f. cache Used by CRAY-1 esd-1-9:10: esd-1-9:10:

24 Branch Prediction (1) Predict never taken Assume that jump will not happen Always fetch next instruction & VAX 11/780 VAX will notprefetch after branch if a page fault would result (O/S v CPU design) Predict always taken Assume that jump will happen Always fetch target instruction Branch Prediction (2) Predict by Opcode Some instructions are more likely to result in a jump than thers Can get up to 75% success Taken/Not taken switch Based on previous history Good for loops esd-1-9:10: esd-1-9:10: Branch Prediction State Diagram Branch Prediction (3) Delayed Branch Do not take jump until you have to Rearrange instructions esd-1-9:10: esd-1-9:10:

25 Example Register Organizations Pentium II EFLAG Register esd-1-9:10: esd-1-9:10: Pentium II Control Registers Pentium II MMX Registers esd-1-9:10: esd-1-9:10:

26 Pentium Data Types Pentium II 8 bit Byte 16 bit word 32 bit double word 64 bit quad word Addressing is by 8 bit unit A 32 bit double word is read at addresses divisible by 4 esd-1-9:10: esd-1-9:10: Structure of Pentium II Internal Data Cache esd-1-9:10:

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