Contiguous Allocation (Cont.)

Transcription

1 // CS: Oerating System Lect 9: 5 th Oct Dr. A. Sahu Det of Com. Sc. & Engg. Inian Institute of Technology Guwahati ain emory an emory anagement Relocation & ultile Partition Contiguous Allocation Best fit, First Fit an Worst fit Buy System Segmentation Paging Segmentation with Paging Contiguous Allocation ain memory must suort both an user rocesses Limite resource, must allocate efficiently Contiguous allocation is one early metho ain memory usually into two artitions: Resient oerating system, usually hel in low memory with interrut vector User rocesses then hel in high memory Each rocess containe in single contiguous section of memory Contiguous Allocation (Cont.) Relocation registers use to rotect user rocesses from each other, an from changing coe an ata Base register contains value of smallest hysical aress Limit register contains range of logical aresses each logical aress must be less than the limit register U mas logical aress ynamically Base an Limit Registers Oerating System base 9 limit CPU Harware Aress Protection aress Base no yes Tra to monitor Aressing Error Base + Limit < no yes E O R Y

2 // ultile artition allocation Degree of multirogramming limite by number of artitions Fixe size Partition (Partition Size (PS)) Num rocess to suort is limite if PS is bigger Suorting a big size rocess is limite if PS is smaller Variable artition sizes for efficiency Size to a given rocess nees Hole block of available memory Holes of various size are scattere throughout memory Buy System A comromise between fixe size an variable size allocation emory is allocate that are a ower of Initially a single allocation unit A rocess is allocate a unit memory whose size is the smallest ower of larger than the size of rocess 5K rocess woul be lace in 6K sace If no allocation unit exist of that size, the smallest available allocation larger than the rocess will be slit into two Buy unit of ½ size Examle Action emory Start K Arr A (5) A 56K 5K Arr B () A B 8K 5K Arr C (5 ) A B C 6 k 5K Rel B A 8K C 6 k 5K Arr D () A 8K C 6 k D 56K Arr E (6) A 8K C E D 56K Rel C A 8K 6 k E D 56K Rel A 56K 8K 6 k E D 56K Rel E 5K D 56K Rel D K ultile artition allocation When a rocess arrives allocate memory from a hole large enough to accommoate it exiting frees its artition, ajacent free artitions combine maintains information about a) allocate artitions b) free artitions (hole) 8 Three es Running ultile artition allocation 8 Finishe 9 9 Arrives 9 Arrives Dynamic Storage Allocation Problem How to satisfy a request of size n from a list of free holes? First fit: Allocate the first hole that is big enough Best fit: Allocate the smallest hole that is big enough; must search entire list, unless orere by size Prouces the smallest leftover hole Worst fit: Allocate the largest hole; must also search entire list Prouces the largest leftover hole First fit an best fit better than worst fit in terms of see an storage utilization

3 // Fragmentation External Fragmentation Total memory sace exists to satisfy a request, but it is not contiguous Internal Fragmentation allocate memory may be slightly larger than requeste memory This size ifference is memory internal to a artition, but not being use First fit analysis reveals that given N blocks allocate,.5 N blocks lost to fragmentation / may be unusable > 5 ercent rule Fragmentation (Cont.) Reuce external fragmentation by comaction Shuffle memory contents to lace all free memory together in one large block Comaction is ossible only if relocation is ynamic, an is one at execution time I/O roblem Latch job in memory while it is involve in I/O Do I/O only into buffers Now consier that backing store has same fragmentation roblems Segmentation emory management scheme that suorts user view of memory A rogram is a collection of segments A segment is a logical unit such as: main rogram, roceure/function/metho, / object, local variables, global variables common block, stack, symbol table arrays User s View of a Program Sub routine ain Program Sqrt Stack Symbol table Logical aress Segmentation : Key Rule Logical View of Segmentation Instea of allocation memory for whole rocess Divie the rogram into smaller block call segments User view : Alreay segmente Finer granularity, less fragmentation ustar in Bag Vs Brinjal in Bag Each of which is allocate to memory ineenently Segments are variable size user sace hysical memory sace

4 // Segmentation Architecture Logical aress consists of a two tule: <segment number, offset>, Segment table mas two imensional hysical aresses; each table entry has: base contains the starting hysical aress where the segments resie in memory limit secifies the length of the segment Segmentation Architecture Segment table base register (STBR) oints to the segment table s location in memory Segment table length register (STLR) inicates number of segments use by a rogram; segment number s is legal if s < STLR Every memory access get translate to Two accesses Segmentation Architecture (Cont.) Protection With each entry in segment table associate: valiation bit = illegal segment rea/write/execute rivileges Protection bits associate with segments; coe sharing occurs at segment level Since segments vary in length, memory allocation is a ynamic storage allocation roblem A segmentation examle is shown in the following iagram CPU s Segmentation Harware S < Limit Base Segment Table no yes Aressing Error + E O R Y Segmentation an Paging Divie the rogram into smaller block call segments : User view, alreay segmente Finer granularity, less fragmentation ustar in Bag Vs Brinjal in Bag Divie the rogram in to smaller but uniform size unit calle age A rogram may contain many ages Last age of rogram may be artially fille Divie the memory in to smaller size units calle Frame Page get mae to Frame Paging Physical aress sace of a rocess can be noncontiguous; rocess is allocate hysical memory whenever the latter is available Avois external fragmentation Avois roblem of varying size memory chunks Divie hysical memory into fixe size blocks calle frames Size is ower of, between 5 bytes an 6 bytes

5 // Paging Divie logical/rogram memory into blocks of same size calle ages Kee track of all free frames To run a rogram of size N ages, nee to fin N free frames an loa rogram Set u a age table to translate logical to hysical aresses Backing store likewise slit into ages Still have Internal fragmentation Aress Translation Scheme Aress generate by CPU is ivie into: Page number () use as an inex into a age table which contains base aress of each age in hysical memory Page offset () combine with base aress to efine the hysical memory aress that is sent to the memory unit Page number Page offset m n n For given logical aress sace m an age size n CPU Logical Aress Paging Harware f Page table f Physical Aress F F E O R Y ain emory Paging oel of Logical an Physical emory Page Page Page Page Logical emory 7 Frame number Page Page Page Page Physical emory Paging (Cont.) Calculating internal fragmentation Page size =,8 bytes size = 7,766 bytes 5 ages +,86 bytes Internal fragmentation of,8,86 = 96 bytes Worst case fragmentation = frame byte Paging (Cont.) Calculating internal fragmentation Ct.. On average fragmentation = / frame size So small frame sizes esirable? But each age table entry takes memory to track Page sizes growing over time Page sizes growing over time Solaris suorts two age sizes 8 KB an B view an hysical memory now very ifferent By imlementation rocess can only access its own memory 5

6 // Page Page B Page Page A Examle 7 age number age offset m n= n= Free list,, 5, b=7 Page A Page B Page A Page B Physical emory Free Frames Before allocation After allocation Imlementation of Page table is ket in main memory Page table base register (PTBR)oints to the age table Page table length register (PTLR) inicates size of the age table In this scheme every ata/instruction access requires two memory accesses One for the age table an one for the ata / instruction Imlementation of Page Page Logical emory PTBR Length Two memory accesses er ata/inst access. Solution? Associative Registers Page Page Physical emory Imlementation of (Cont.) The two memory access roblem can be solve by the use of a secial fast looku harware cache calle associative memory or translation look asie buffers (TLBs) Some TLBs store aress sace ientifiers (ASIDs)in each TLB entry uniquely ientifies each rocess to rovie aresssace rotection for that rocess Otherwise nee to flush at every context switch Imlementation of (Cont.) TLBs tyically small (6 to, entries) On a TLB miss, value is loae into the TLB for faster access next time Relacement olicies must be consiere Some entries can be wire own for ermanent fast access 6