Memory Management (Ch.9)
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1 Memory Management (Ch.9)! Background! Address Binding - Linking and Loading! Swapping! Memory Protection! Contiguous Memory Allocation! Paging! Segmentation! Combined Paging and Segmentation Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 1
2 Background! CPU scheduling improves CPU utilization and the speed of the computer s response to its users. l To realize this goal memory must be shared by multiple processes! CPU goes through an instruction-execution cycle l Instruction fetched from memory and decoded resulting in possible retrieval of operands from memory l Instruction executed and results may be stored back in memory Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 2
3 Address Binding! Input queue collection of processes on the disk that are waiting to be brought into memory to run the program.! One of these processes is selected to be loaded into memory, run and, when terminated, removed from memory l A process can reside in any part of the physical memory. The first address of the user process does not have to be the first address of the computer Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 3
4 Binding of Instructions and Data to Memory Address binding of instructions and data to memory addresses! can occur at three different stages.!! Compile time If memory location known at compile time then absolute code can be generated; must recompile code if starting location changes.! Load time Must generate relocatable code if memory location is not known at compile time but is finalized at load time.! Execution time Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers). Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 4
5 Binding of Instructions and Data to Memory Absolute and Relocatable Load Modules Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 5
6 Memory-Management Unit (MMU)! Hardware device that performs run-time mapping between virtual and physical address.! In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory.! The user program deals with logical addresses; it never sees the real physical addresses. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 6
7 Swapping! A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution.! Backing store fast disk, large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images.! Roll out, roll in swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed.! Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 7
8 Contiguous Memory Allocation! Multiple-partition allocation l Hole block of available memory; holes of various size are scattered throughout memory. l When a process arrives, it is allocated memory from a hole large enough to accommodate it. l Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS! OS! OS! OS! process 5! process 5! process 5! process 5! process 9! process 9! process 8! process 10! process 2! process 2! process 2! process 2! Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 8
9 Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes.!! First-fit: Allocate the first hole that is big enough l Next-fit: look for first-fit from last allocation! Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole.! Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole.! Neither first-fit or best-fit is clearly better for storage utilization but first-fit is generally faster Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 9
10 Fragmentation! External Fragmentation free memory space is broken into non-contiguous pieces, none big enough to satisfy a request! Internal Fragmentation allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used.! Reduce external fragmentation by compaction l Shuffle memory contents to place all free memory together in one large block., this can be expensive l Compaction is possible only if relocation is dynamic, and is done at execution time. l Or, use Paging Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 10
11 Paging! Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available.! Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes).! Divide logical memory into blocks of same size called pages.! Keep track of all free frames.! To run a program of size n pages, need to find n free frames and load program.! Set up a page table to translate logical to physical addresses. l Contains the base address of each page in physical memory! Internal fragmentation. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 11
12 Address Translation Scheme! Address generated by CPU is divided into: l Page number (p) used as an index into a page table which contains base address of each page in physical memory. l Page offset (d) combined with base address to define the physical memory address that is sent to the memory unit. l If the size of the logical address space is 2 m and page size is 2 n then the high order m-n bits of the logical address designate the page number and the n low order bits designate the page offset page number (p) page offset(d) m-n n Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 12
13 Address Translation Architecture Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 13
14 Paging Model Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 14
15 Paging Example Page size = 4 bytes Physical memory = 32 bytes (8 pages) Page 0 is in frame 5 which is physical address 20 Logical address 3 (page 0 offset 3) is mapped to frame 5 offset 3 which is physical address 23 Paging is similar to using a table of base registers, one for each frame of memory To reduce internal fragmentation, some OSs support multiple page sizes Solaris 8KB and 4KB Research on variable, on-the-fly pages Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 15
16 Free Frames Before allocation! After allocation! Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 16
17 Implementation of Page Table! Page table can be implemented as a set of dedicated registers with very high speed logic. Reloaded by the CPU dispatcher. Good for reasonably small page tables (256 entries)! Large page tables (1 million entries) are kept in main memory. l Page-table base register (PTBR) points to the page table. l Page-table length register (PTLR) indicates size of the page table so as to minimize the amount of memory needed rather than allocate space for the full table! In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.! The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 17
18 Paging Hardware With TLB Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 18
19 Effective Access Time! Associative Lookup = ε time unit! Assume memory cycle time is x microsecond! Hit ratio percentage of times that a page number is found in the associative registers; ratio related to number of associative registers.! Hit ratio = α! Effective Access Time (EAT) EAT =?? Slide 19
20 Effective Access Time! Associative Lookup = ε time unit! Assume memory cycle time is x microsecond! Hit ratio percentage of times that a page number is found in the associative registers; ratio related to number of associative registers.! Hit ratio = α! Effective Access Time (EAT) EAT = (x + ε) α + (2x + ε)(1 α) = 2x α x + ε Slide 20
21 Effective Access Time! 20 nanosec to search TLB, 100 nanosec to access memory! TLB hit à?! TLB missà?! EAT with 80% hit ratio=?! EAT with 98% hit ratio =?! % slowdown in access time =? Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 21
22 ! 80% hit ratio Effective Access Time! 20 nanosec to search TLB, 100 nanosec to access memory! TLB hit à 20ns+100ns = 120ns! TLB missà 20ns + 100ns(page table lookup) + 100ns (physical memory lookup) = 220ns! Effective access time =.8* *220 = 140 ns (40% slowdown in access time)! 98% hit ratio à.98* *220 = 122ns (22% slowdown in access time) Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 22
23 Memory Protection! Memory protection in a paged environment is implemented by associating protection bits with each frame. l Bits specify execute-only, read-only, read-write or any combination! Valid-invalid bit attached to each entry in the page table: l valid indicates that the associated page is in the process logical address space, and is thus a legal page. l invalid indicates that the page is not in the process logical address space. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 23
24 Valid (v) or Invalid (i) Bit In A Page Table Page size 2KB, 14 bit address space à addresses 0 to 16,383 Program addresses 0 to 10,468 which is in frame 5, frames 6 and 7 are invalid Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 24
25 Page Table Structure! Hierarchical Paging! Hashed Page Tables! Inverted Page Tables Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 25
26 Hierarchical Page Tables! Most computers support a large logical address space (2 32 to 2 64 ) page table becomes excessively large l 32-bit logical address space with page size of 4KB How many entries the resulting page table has?! Break up the logical address space into multiple page tables.! A simple technique is a two-level page table. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 26
27 Hierarchical Page Tables! Most computers support a large logical address space (2 32 to 2 64 ) page table becomes excessively large l 32-bit logical address space with page size of 4KB (2 12 ) results in a page table of 1 million entries (2 32 /2 12 =1,048,575). l If each entry is 4 bytes, then each process may need up to 4MB of physical address space just for the page table! Break up the logical address space into multiple page tables.! A simple technique is a two-level page table. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 27
28 Two-Level Paging Example! A logical address (on 32-bit machine with 4K page size) is divided into: l a page number consisting of 20 bits. l a page offset consisting of 12 bits.! Since the page table is paged, the page number is further divided into: l a 10-bit page number. l a 10-bit page offset.! Thus, a logical address is as follows: page number! p 1! p 2! d! page offset! 10! 10! 12! where p 1 is an index into the outer page table, and p 2 is the displacement within the page of the outer page table. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 28
29 Two-Level, Forward-Mapped Page-Table Scheme Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 29
30 Address-Translation Scheme (32 bits) Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 30
31 Hashed Page Table Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 31
32 Inverted Page Table! Usually, each process has an associated page table. Each page table may consist of millions of entries consuming large amounts of physical memory.! Inverted page table uses one entry for each real frame of memory.! Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page! Only one page table in the system, but increases time needed to search the table when a page reference occurs.! Since may need to search the whole table for a match, use hash table to limit the search to one, or at most a few, page-table entries. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 32
33 Inverted Page Table Architecture Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 33
34 ! Shared code Shared Pages l One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). l Shared code must appear in same location in the logical address space of all processes. l Important in time-sharing environments if 40 users execute a text editor that is 150KB of code and 50KB of data l How much memory we need? l By sharing the re-entrant code how much memory do we save? Slide 34
35 ! Shared code Shared Pages l One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). l Shared code must appear in same location in the logical address space of all processes. l Important in time-sharing environments if 40 users execute a text editor that is 150KB of code and 50KB of data we would need 8,000KB of memory. By sharing the re-entrant code we reduce 6,000KB to 150KB! Private code and data l Each process keeps a separate copy of the private code and data. l The pages for the private code and data can appear anywhere in the logical address space. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 35
36 Shared Pages Example Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 36
37 Segmentation! Memory-management scheme that supports user view of memory.! A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 37
38 User s View of a Program Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 38
39 Logical View of Segmentation 1! 1! 4! 2! 3! 4! 2! 3! user space! physical memory space! Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 39
40 Segmentation Architecture! Logical address consists of a two tuple: <segment-number, offset>,! Segment table maps two-dimensional physical addresses; each table entry has: l base contains the starting physical address where the segments reside in memory. l limit specifies the length of the segment.! Segment-table base register (STBR) points to the segment table s location in memory.! Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR. Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 40
41 Segmentation Architecture (Cont.)! Protection. With each entry in segment table associate: l validation bit = 0 illegal segment l read/write/execute privileges! Protection bits associated with segments; code sharing occurs at segment level.! Since segments vary in length, memory allocation is a dynamic storage-allocation problem.! External fragmentation Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 41
42 Segmentation Hardware Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 42
43 Example of Segmentation! 2:53 or 2,53 refers to segment 2 byte 53 which is mapped to 4353! 0,1222 results in a trap to the OS as the segment is only 1000 bytes long Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 43
44 Sharing of Segments Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 44
45 Combined Paging & Segmentation Paging and segmentation have their strengths Paging transparent to the user, eliminates external fragmentation The pieces moved in and out of main memory are of fixed, equal size which enables the development of sophisticated algorithms that exploit this feature Segmentation visible to the programmer, can grow dynamically, enables sharing and protection by segment To combine the two, a user s address space is broken up into a number of segments at the discretion of the programmer Each segment is broken up into a number of fixed size pages, equal in length to a page frame Each segment has an associated page table When a process is running, a register holds the starting address of the segment table Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 45
46 Combined Paging & Segmentation Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 46
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