Performance of an IF sampling ADC in receiver applications


 Reynard Bruce
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1 Performance of an IF sampling ADC in receiver applications David Buchanan Staff Applications Engineer Analog Devices, Inc. Introduction The concept of direct intermediate frequency (IF) sampling is not a new one. In fact many modern receiver designs employ this architecture. Performance of commercially available analog to digital converters (ADC), however, often eliminates this architecture due to dynamic performance limitations. This paper explores the concept of direct IF sampling and ADC performance characteristics which designers should consider in this application, and highlights the performance of a new 12 bit, 125Msps ADC design optimized for this application. Basics of Direct IF Sampling The Nyquist sampling theorem, as traditionally interpreted, requires that the sampling rate (f s ) of an ADC be at least twice the highest frequency component in the waveform being sampled to recover or accurately represent the original waveform. 1 This is often referred to as baseband sampling. To meet this requirement, the analog signal must be low pass filtered before being sampled. In Figure 1, f 2 is filtered to meet the Nyquist criteria. If you examined the frequency content of the ADC output data with a fast Fourier transform (FFT), the desired signal (f 1 ) would be represented within the accuracy of the ADC. list of possible frequencies by considering real world limitations, such as the bandwidth of the analog source, or the bandwidth of the ADC s analog input circuit 2. Another helpful concept is to divide the unfiltered analog input spectrum into Nyquist zones. As defined in Figure 3, a signal at frequency f analog in an odd Nyquist zone N will alias to f analog = f analog  (N 1)f s /2. Even Nyquist zone frequencies will alias to fanalog = (N)f s /2  f analog. Figure 2. Aliasing in the time domain. Figure 1. Traditional Interpretation of Nyquist Sampling Theorem Without the low pass filter to guarantee the Nyquist sampling theorem is met, aliasing may occur. Aliasing is a term used to describe frequency content in the ADC output spectrum caused by undersampling signals (f analog >f s /2). If you reconstruct the samples of an under sampled frequency, it will always alias to a baseband frequency as shown in Figure 2. Alias is an appropriate term because the actual analog input frequency which has been aliased to f analog could theoretically be generated from any frequency Nf s (f analog, where N is an integer. In practice, f analog can always be narrowed to a more finite Figure 3. Dividing the analog input spectrum into Myquist zones. Figure 4 illustrates how frequencies are aliased in the frequency domain, with f 2 and f 3 being aliased to f 2' and f 3'. The traditional interpretation of the Nyquist sampling theorem is not completely accurate, in that it limits the absolute frequency of the waveform being sampled to be less than 1/2 the sampling frequency. In fact it is the bandwidth of the waveform that must be limited, and not the actual frequency. 3* In IF undersampling applications, a bandpass filter limits the * Also known as the Shannon sampling theorem. International IC China Conference Proceedings 63
2 output spectrum to a particular Nyquist zone, and in effect takes advantage of the aliasing affect. Figure 6. Traditional Super Heterodyne Digital Receiver. Figure 4. Aliasing occurs when the conditions of the Nyquist Sampling Theorem are not met. Figure 7. IF Sampling Digital Receiver. Figure 5. Bandpass or IF UnderSampling IF vs. Baseband Sampling Many modern receivers take advantage of digital signal processing, but most rely on traditional super heterodyne architectures to translate the signal of interest to a base band IF before the signal is sampled (base band sampling). Direct IF receivers take advantage of undersampling to eliminate one or more of the tuned analog IF stages. The ADC acts like a mixer, translating the signal to base band for digital processing. Depending on system performance, each IF stage eliminated has the potential to reduce system cost by $10 to $100. The eliminated IF stages are replaced by digital Receive Signal Processors (RSPs). These specialized devices take advantage of low cost VLSI solutions for filtering, frequency translation, error correction, and demodulation. In addition to system cost reduction, these RSPs eliminate the many of the sensitivities of analog solutions, such as device matching, phase noise, environmental sensitivity, and performance variation over time. If the ADC can maintain the required performance level over a wide bandwidth, it may be possible to implement a multi carrier receiver. In this architecture, a single ADC samples multiple signal channels, which are then separated and demaodulated in parallel in the digital domain. This architecture compounds the system cost and performance advantage of IF sampling by eliminating multiple RF / IF sections. Figure 8. Multi Carrier IF Sampling Receiver ADC Performance Considerations While ADC technology has improved significantly over time, only a few can provide the performance needed for IF sampling applications. Even fewer guarantee performance specifications for undersampling applications. This puts the burden on designers to understand the specifications and characteristics of the ADC. This section will highlight some of the more important dynamic performance characteristics designers should consider when selecting an ADC for IF sampling. It also offers examples of performance data for the AD9433, a new 12 bit, 125 Msps ADC from Analog Devices, Inc., which is targeted at this application. As discussed above, the minimum sample rate of an ADC must be twice the signal of interest. However, a higher sample rate is often instrumental in reducing the required selectivity, and therefore the cost and complexity, of the analog antialiasing filter. By frequency planning so that the signal of interest is not near the boundaries of the Nyquist zones, the selectivity of the band pass filter is relaxed. Since IF components, such as surface acoustic wave (SAW) filters, are only available at limited number of frequencies, it is not practical to design receivers with arbitrary IFs. Alternatively, increasing the sample rate is often an easy way to move the IF away from the Nyquist boundary. Relaxing the selectivity of the analog filter may also allow additional noise and adjacent interfering signals into the ADC 64 International IC China Conference Proceedings
3 output spectrum. These can be removed by additional filtering in the digital domain. There are obvious disadvantages to higher sample rates as well. Like many other components, the highest speed ADCs available are leading edge technology, and therefore their cost is higher. Designers will also find that resolution and dynamic performance will be degraded as compared to lower speed alternatives. Power dissipation of the converter may also increase with sample rate. The cost, performance, and power dissipation of other devices in the system (RSPs, drive amplifiers, and ADC clock sources) are also impacted by the ADC sample rate. An ADC s performance will also degrade as you increase the sample rate. This may be due to a variety of factors, but T/ H settling time is most often the main reason for this degradation. It may be advantageous to use a sample rate below the rated maximum to insure that system dynamic performance is not impacted by this effect. Another concern is the added noise of higher speed digital circuits, which can often degrade the performance of nearby analog circuits and the ADC itself. In fact, an ADCs own outputs may often degrade its performance. The bandwidth of an ADC can be defined in several ways. One is simply to specify the 3dB bandwidth of the ADC input stage or track and hold circuit. Another is to consider the frequency at which the spectral power of the ADCs digital output signal is reduced by 3dB. Perhaps the most stringent definition would be the analog frequency for which the ADCs signal to noise ratio (SNR, see below) performance was reduced by 3dB (as compared to it s base band performance). However it is defined, direct IF sampling receiver applications require the ADC to provide enough bandwidth to allow sampling of common IF frequencies, MHz. This frequency range is driven by availability of other IF components, such as mixers, amplifiers, and SAW filters. Additional bandwidth may be necessary in the analog front end for the ADC to meet other dynamic specifications, such as harmonic distortion, but it is important to consider that this extra bandwidth will also allow additional wide band noise to be aliased into the spectrum of the ADC output signal. Designers are cautioned not to assume that an ADC s dynamic specifications will be constant over its rated bandwidth. The bandwidth of the AD9433 is an extremely wide 750MHz, allowing it to extend other important performance characteristics to IFs as high as 400MHz. One of the more unique features of this ADC is a user configurable input bandwidth optimization. Control pins on the device allow the user to optimize the performance of the ADC for 3 different input bandwidths: Base band (<100MHz, IF Sampling I ( MHz), and IF Sampling II (>250MHz). The IF Sampling II mode also reduces the differential analog input voltage range from 2Vpp to 1Vpp, reducing the drive requirements of the signal source. The transfer function of the ADC is described in terms of its linearity. Differential nonlinearity (DNL) is the deviation of any output code from an ideal least significant bit (LSB) step. Manufacturers typically specify the worst short and long code in terms of an ideal LSB. Although it is not specified, the rms value of all the DNL errors in the ADC will determine the amount of quantization noise in the ADCs output spectrum. Integral nonlinearity is typically specified as the deviation, in LSBs, of the ADCs transfer function from a best straight line (offset and gain errors are ignored). While the INL specification is a good measure of overall dynamic performance, it does not tell the whole story. It is the shape of the linearity curve that will determine how it distortion performance. Devices with large INL errors, or many perturbations in the transfer function will have poor harmonic and spurious distortion performance. For instance, a S shaped linearity curve will cause the ADC to have pronounced third harmonic distortion. In the case of the AD9433, two key features minimize its linearity errors. The first is an on board circuit that trims out DNL errors to 0.25LSBs. During device test, DNL is measured and then adjusted by programming registers in the trim circuit. Once optimized, the trim setting is fixed with polysilicon fuses. The second linearity feature optimizes INL errors during device operation, and is referred to an SFDR (spurious free dynamic range) optimization circuit. This circuit shuffles some of the internal devices that determine the linearity of the ADC between each clock cycle, which randomizes the location of the worst DNL errors in the transfer function. This effectively spreads the worst DNL errors over the entire range of the converter transfer function. To illustrate the effectiveness of this circuit, an AD9433 was intentionally mistrimmed to exaggerate DNL errors, and then INL was measured with and without the SFDR optimization circuit. The results were that the SFDR circuit could reduce the INL error from LSBs to (0.25LSBs. Unless otherwise noted, the SFDR improvement circuit is active for all AD9433 data presented in this paper. Figure 9. AD9433 INL without SFDR Optimization Circuit. Figure 10. AD9433 INL With SFDR Optimization Circuit. Frequency domain testing and characterization of high speed ADCs has become standard over the past decade. Most of these specifications are measured by performing a FFT on the output International IC China Conference Proceedings 65
4 data. It is important that designers consider test conditions, such as sample rate, analog input frequency, and analog input amplitude, when interpreting and comparing these specifications. The most common benchmark is SNR. It is usually specified in db for a sine wave input, and at rated sample rate. It is defined as the ratio of the rms signal amplitude to the rms value of the sum of all other spectral components in the ADC output spectrum. To give designers a more accurate understanding of ADC performance, manufacturers typically specify SNR excluding the harmonics of the fundamental frequency. SNR with harmonics, or SINAD (signal to noise and distortion), as well as the relative levels of the individual harmonics (Harmonic Distortion) and other spurious frequency content (Spurious Free Dynamic Range) are often specified as well. The theoretical SNR of an ADC for a fullscale sine wave input is SNR Theoretical = 6.02N dB, where N is the number of bits. 4 Based on this, manufacturers often specify an Effective Number of Bits (ENOB), calculated from the measured SNR or SINAD based on the following equation: the output spectrum that are not traceable to the fundamental or its harmonics. They may be due to other frequency sources in the system which unintendendly couple into the ADCs clock, analog input, power supplies, or reference. Even worse are intermodulation products between two system frequencies, which may be nearly impossible to identify. In many ADC specifications, higher order harmonics are often considered spurious frequency content. Another key specification related to receiver sensitivity is two tone inter modulation distortion. In this test, the analog input contains two sine wave inputs, f 1 and f 2. The intermodulation distortion products fall at 2f 1  f 2, and 2f 2  f 1 as illustrated in Figure 12. Figure 12. Diagram Two Tone Intermodulation Distortion. The last term in the numerator compensates for any reduction in the signal amplitude during the test. It is impractical in production test systems (as well as in receiver applications) to maintain a constant full scale amplitude, so the testing is performed with a 0.5 to 1.0dBFS (relative to full scale) input level. Because they can affect overall sensitivity, harmonic and spurious frequency content in the ADC output spectrum are of key importance in receiver applications. It is important to note that these frequencies can be aliases, so they may be difficult to identify. The FFT result in Figure 11 is for the under sampling condition of 100Msps and 140.3MHz, so the fundamental and all harmonics appear as aliased frequencies. An FFT for the AD9433 illustrates additional higher order harmonics and IMD products in Figure 13. Figure 13. AD9433 Two Tone Intermodulation. 100Msps,ƒ 1 =210.3MHz, ƒ 2 =211.3Mhz Figure 11. FFT of AD Msps, 140.3MHz Harmonics may be difficult to recognize in the output spectrum, but since the fundamental frequency is known, it possible to predict where they will fall using the Nyquist zone technique discussed earlier. Spurious frequencies are technically those in Realizing ADC performance in Systems While it is not possible to give a comprehensive overview of realizing the performance of a high performance ADC such as the AD9433 in the space provided, it is worth mentioning a few key issues. The first is signal conditioning of the analog input circuit. While most real world signals are single ended, most high performance ADCs require a differential analog input signal to realize rated performance. It is also difficult to find cost effective differential amplifiers at IF frequencies, especially ones that provide the level of performance of the ad9433. A transformer, as configured in can provide cost effective solution to this problem. Perhaps the most important consideration in realizing the performance of the ADC is the sampling clock. While the 66 International IC China Conference Proceedings
5 Figure 14. Using two Transformers for Single Ended to Differential Signal Conversion AD9433 has an integrated clock duty cycle stabilization circuit that will the user to provide input duty cycles from 2575%, jitter in the clock reference will severely degrade noise performance at IF frequencies.5 For the test results presented in this paper, a 100MHz sine oscillator from Wenzel Associates was used as configured in Figure 15. Figure 15. Wenzel Sine Oscillator Sample Clock Circuit. Summary The direct IF sampling architecture provides the opportunity to simplify and cost reduce receiver designs when compared with standard super heterodyne architectures. The AD9433, a 12 bit, 125Msps ADC, provides a new level of performance in IF sampling ADC technology. The design innovations of this new device, including an SFDR optimization circuit, will allow designers to extend the IF sampling architecture to higher IF frequencies, and over wider bandwidth signals. References ( Also known as the Shannon sampling theorem. 1 Robert W. Ramirez. The FFT Fundamentals and Concepts. New Jersey: PrenticeHall, N. S. Tzannes. Communication and Radar Systems. New Jersey: PrenticeHall, Walt Kester. High Speed Design Seminar. Massachusetts. Analog Devices, Rudy Van De Plassche. Integrated Analog To Digital and Digital To Analog Converters. Massachusetts. Kluwer Academic Publishers, Brad Brannon. Application Note 501: Aperture Uncertainty and ADC System Performance. Massachusetts. Analog Devices, Author s contact details David C. Buchanan, Jr. Analog Devices, Inc Triad Center Drive Greensboro, NC USA Phone: (1336) Fax: (1336) International IC China Conference Proceedings 67
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