A Low-Power Reference Buffer with High PSRR and Low Crosstalk for Time- Interleaved ADCs
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1 This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* A Low-Power Reference Buffer with High PSRR and Low Crosstalk for Time- Interleaved ADCs Hyeonho Song a), Jintae Kim b) and Minjae Lee c) School of Information and Communications, Gwangju Institute of Science and Technology, 123 Cheomdan-gwrgiro, Buk-gu, Gwangju , Korea a) shh12kr@gist.ac.kr b) jintkim@konkuk.ac.kr c) minjae@gist.ac.kr Abstract: A low power reference buffer is proposed to achieve high PSRR and less crosstalk between channels for time-interleaved analog-to-digital converters (ADCs). A conventional approach requires enough bandwidth in feedback amplifiers to suppress high frequency supply noise, which tends to increase power consumption. Furthermore the number of output drivers that share error amplifier output is unavoidably limited due to the coupling across ADC channels. We propose design techniques to improve the corner frequency of power supply rejection ratio (PSRR) by a factor of 100 and the cross-channel isolation by 20dB without drawing more current. Keywords: Reference buffer, Time Interleaved ADC, analog to digital converter, Pipelined ADC, 1.5 bit ADC, High PSRR Classification: Integrated circuits References [1] H. Yu, S. W. Chin, B. C. Wong, A 12b 50MSPS 34mW Pipelined ADC, in Proc. IEEE Custom Integrated Circuits Conf., Aug. 2008, pp [2] Wei-Hsuan Tu, Tzung-Hung Kang, A 1.2V 30mW 8b 800MS/s Timeinterleaved ADC in 65nm CMOS, in Symp,VLSI Cricuits Dig. Papers, Jun. 2007, pp [3] Zwei-Mei Lee, A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digi tal Background Calibration, IEEE J. Solid-State Circuits, vol.42, no.10, Oct 2007, pp [4] Wei-Hsuan Tu, Tzung-Hung Kang, Reference Buffer circuit, US Patent , Nov. 26., IEICE 2013 DOI: /elex Received June 21, 2013 Accepted June 28, 2013 Publicized July 23, 2013
2 1. Introduction In pipelined ADCs or SAR ADCs, which utilize only a fraction of supply voltage as full scale range, a reference buffer with sufficient driving capability is required to provide accurate voltage references [1]. Furthermore, on-chip supply or substrate noise must be sufficiently attenuated with high PSRR, which is often achieved by using a large bandwidth error correcting amplifier in a negative feedback loop [1]. Low power and low driving impedance is usually achieved by using source follower driving stage and its relative accuracy is corrected by error amplifiers. In order to reduce bandwidth requirement of the error amplifier, a replica driving stage feeds error amplifier to correct the reference voltage variation. The voltage mismatch between the real driver and the replica driver due to threshold voltage mismatch results in ADC gain error, which can be calibrated out [2]. Especially, in a time interleaved ADC, a reference buffer can be shared across ADC arrays to minimize power as shown Fig.1. A reference buffer is connected to 4 channel ADCs with different phase for each. In this case, cross-channel coupling needs to be minimized to the required accuracy of the ADC. Theoretically, the cross-channel coupling must be below a half LSB(least significant bit) of ADC resolution. Such requirement limits the maximum number of driving buffers that share the same control voltage. To attach more driving buffers, it is essential to minimize the cross-channel coupling [3]. This paper proposes an on-chip reference buffer that improves PSRR and reduces cross-channel coupling without consuming more current by converting supply noise into common mode noise and adding crosstalk cancellation paths to balance out the effect of large voltage transients at the reference outputs, which contaminate the shared control voltage. Fig. 1 Time interleaved ADC with 4 channels 2. Proposed Implementation A conventional low power implementation uses two operational transimpedance amplifiers (OTAs) and output driving stages, of which current is shared to generate two reference voltages, Vrefo+ and Vrefo- [2], [4]. In order to get large PSRR at low frequencies, we utilized a two-stage amplifier to get large DC gain, whereas it
3 requires a compensation capacitor for stability. Generally the OTA1, used to generate upper reference voltage in Fig. 2, is designed with NMOS input pair to get enough headroom for the bottom current source, and the OTA2 for the lower reference voltage is realized with PMOS input pair for the same reason. However, this conventional design choice makes PSRR worse in our buffer design because the outputs of OTA1 and OTA2 are likely to track positive supply noise and ground noise respectively due to large compensation capacitors, which results in unavoidable differential noise on Vrefo+ and Vrefo-.To improve PSRR without spending additional power, we use the same type of input pair operational amplifiers as shown Fig. 2. With this implementation, both outputs of the operational amplifiers track supply noise similarly, and differential value of the reference voltages stays constant. Therefore, our implementation translates the supply fluctuation into common mode variation at the reference outputs, of which effect is not a critical in differential circuit implementation. Fig. 2 Proposed reference buffer In a reference buffer circuit shown in Fig. 2, when MDAC capacitors are switching, large current spikes results in large voltage transients on the reference lines, which couple on control lines, Vx and Vy through Cgs of MN1 and MP1. In the case of shared control voltage across multiple drivers, reference voltages of the neighboring channels are affected by the control voltage movement. In a time interleaved ADC, where sampling clocks are shifted in time, this small bump on the reference voltages must be suppressed enough before actual sampling take places in ADC stages [2]. A known solution is to use a bypass capacitor between high and low output voltage like MN4, MP4, MN5 and MP5 in Fig. 2, which provides low impedance, reduces the voltage transient on reference lines and improve noise as well. However, with the limited size of the on-chip capacitor, the bypass capacitor may not remove the ripples sufficiently.
4 In our proposed reference buffer, we utilized MOS capacitors, MN3 and MP3 as shown Fig. 2 to balance out the coupling using the fact that the large transients on reference lines always appear in opposite polarity. We set the size of MN3 and MP3 to about 2/3 of MN1 and MP1 respectively to replicate Cgs of MN1 and MP1. With this implementation, more reference driving stages can share the same control voltage. 3. Simulation results The proposed reference buffer is simulated in a 0.11μm CMOS process using Spectre at different corners. The reference buffer generates single-ended 300mV pp input (Vrefo+=900mV, Vrefo-=600mV) under 1.5V supply with the total current of 16.2mA; 1.5mA for each OTA, 1.2mA for the replica stage and 6mA for each driving stage. For the lower output noise and voltage transient, we used 1pF MOS capacitors (MN4 and MP4) as decoupling capacitors. The differential output noise of the implemented buffer is 75μV rms, which is low enough to achieve more than 10 ENOB(effective number of bits) in our application. Fig. 3(a) presents the performance comparison of PSRR(power supply rejection ratio) between the proposed buffer and a conventional one. The conventional one uses PMOS differential pair input for the OTA2. But our proposed reference buffer uses NMOS differential pair input for both OTA1 and OTA2, which shows better supply noise rejection over wider frequency range. In slow corner, DC gain is slightly lower than that of other corners. This degradation is from the lack of headroom in the second stage amplifier in OTAs. As shown in Fig. 3(a), the corner frequency for the supply rejection in our design is expanded 100 times greater than that of the conventional one. To verify cross-channel isolation capability, our reference buffer is connected to four 12b Pipelined ADC slices, ADC0, ADC90, ADC180 and ADC270, of which sampling clocks are 90 degree phase-shifted respectively to achieve 4 times faster sampling rate of each ADC. Input sampling capacitance of each ADC slice is 2.4pF to satisfy the thermal noise requirement. I-driver in Fig. 2 drives ADC0 and ADC180, and Q-driver in Fig. 2 drives ADC90 and ADC270 to minimize the effect of coupling. Fig. 3(b) at the bottom is the magnified view of the I-channel driver output when Q-channel driver sees entering into a new ADC phase, where large voltage excursion on the reference line appears. We verified that the amount of transient coupling from I-channel to Q-channel or vice versa is greatly reduced by the proposed method. In Fig. 3(c), cross channel isolation is also verified in AC simulation by finding AC gain from I-channel driver output to Q-channel driver output. The proposed reference buffer improves cross-channel isolation by 20dB over broad range of frequency. Fig. 3(d) shows SFDR(spurious free dynamic range) comparison of 12b ADCs for different sampling frequencies using the proposed buffer and a conventional buffer respectively. The performance of ADC without using the proposed cross-channel isolation technique degrades
5 significantly as the sample rate goes higher. (a) (b)
6 (c) (d) Fig. 3 Simulation results for different corners (a) Comparison of PSRR (b) Cross-channel isolation in transient simulation, (Top: I-driver output as an aggressor, Bottom: Q-driver output as a victim) (c) Cross-channel isolation in AC simulation (AC gain from I-driver output to Q-driver output is found) (d) Sampling frequency vs. SFDR using reference buffer
7 4. Conclusion This paper has proposed several methods to improve PSRR and suppress cross-channel coupling in a reference buffer without adding power. The presented low power techniques are especially useful in time-interleaved ADCs, where a large number of reference buffers and ADC slices are required and their power consumption must be minimized. Acknowledgments This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Science, ICT and Future Planning(2013R1A1A )
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