ACS8944 JAM PLL. Evaluation Board (EVB)

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1 Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4 ADVANCED COMMUNICATIONS COMMS & SENSING FINAL EVALUATION BOARD ACS8944 JAM PLL Evaluation Board (EVB) Overview This document describes the ACS8944 JAM PLL Evaluation Board (EVB). It describes how to set-up and operate the board in order to exercise and evaluate the functionality of the ACS8944 JAM PLL. The PCB Schematic and Bill of Materials (BOM) are included. This document should be read in conjunction with the ACS8944 JAM PLL Datasheet. Revision 1/January 2007 Semtech Corp. Page 1

2 Table of Contents Section Page Overview... 1 Description... 3 Features...3 Hardware Description...3 PCB Description...4 PCB Configuration...4 PCB Layout Recommendations...5 Bill Of Materials... 6 Schematic... 7 Trademark Acknowledgements... 8 Revision Status/History... 8 Abbreviations... 8 Notes... 9 Ordering Information Disclaimers Contacts Revision 1/January 2007 Semtech Corp. Page 2

3 Description Features The ACS8944 JAM PLL Evaluation Board (EVB) provides the means to quickly set-up and evaluate the functionality and performance of the ACS8944 JAM PLL device. The ACS8944 can be configured using simple jumper settings on the EVB. The board provides differential line input and output connections via SMB connectors, with appropriate termination circuitry for LVPECL signals. The required RC components that define the loop filter bandwidth can be determined from the datasheet for the specific application. These must then be soldered to the underside of the board. Hardware Description Figure 1 Annotated EVB - Top View 4-layer populated PCB Surface-mounted ACS8944 JAM PLL SMB connectors for a differential clock input and differential output Jumpers to configure input and output clock frequencies Pushbutton switch for board reset Single 3.3V supply connection JMP1 Configuration Jumpers Probe Point (VDD) Ref Clock Differential Input (-ve) SMB Connector IN Ref Clock Differential Input (+ve) SMB Connector Probe Point (RESET Bar) 0 V DC +3.3 V DC SK1 Terminal Block Decoupling Capacitor Probe Point (VDD) Lock Detector Probe Point (Active Low) Ref Clock Differential Output (+ve) SMB Connector OUT Ref Clock Differential Output (-ve) SMB Connector Probe Point (GND) Probe Point (GND) LVPECL Input Termination U1 ACS8944 JAM PLL SW1 RESET Switch LVPECL Output Termination F8944EVB_001annotop_01 Revision 1/January 2007 Semtech Corp. Page 3

4 F155 F77 F38 F19 ACS8944 JAM PLL Figure 2 Annotated EVB - Bottom View PLL Loop Filter Components C7 (PCB) = Datasheet C2 R9 (PCB) = Datasheet R1 C8 (PCB) = Datasheet C1 C10 (PCB) = Datasheet C3 R10 (PCB) = Datasheet R2 C9 (PCB) = Datasheet C4 Note... C7 and C9 landing pads allow different sized capacitors C11, R11: RC Delay for Reset R12, C17: Lock Detector Filter Components C5, C6, C13, C14, C15, C16: 3.3 V Supply Decoupling Capacitors F8944EVB_annotbotfig2_01 PCB Description Figures 1 and 2 indicate the location of the main PCB components referred to in this description. Where Datasheet terms are given in red in Figure 2, these refer to the loop filter components in the figures and tables in the Loop Filter Components section of the ACS8944 datasheet. A single 3.3 V DC supply is required for the board. This should be connected to the board via terminal SK1. A 100 uf supply decoupling capacitor is provided for the supply near to SK1. Each supply pin to the device has additional decoupling capacitors placed close to the pin. The configuration of the device is controlled via jumpers on the header block JMP1. The manual reset switch SW1 must be used to reset the device after a configuration change. The lock detector output can be observed via the test point TP1. This is located on the right hand side of the board and is labelled LOCKB. PCB Configuration The EVB can be configured using three jumpers on the JMP1 header block located on the top left hand corner of the evaluation board. Figure Jumper Configuration EXT1 Config JMP EXT2 Config EXT1 and EXT2 configure the input frequency of the ACS8944, whilst OPFSEL configures the required output frequency. The jumper connections should be configured as described in Tables 1 and OP_FSEL Config Revision 1/January 2007 Semtech Corp. Page 4

5 Table 1 Input Frequency Configuration Settings Input Frequency (MHz) EXT1 EXT2 C9, C10, R9 and R10) should be changed to the values specified in the Loop Filter Components section of the ACS8944 datasheet Connect 1 & 2 Connect 9 & Connect 3 & 4 Connect 11 & Connect 5 & 6 Connect 9 & Connect 7 & 8 Connect 11 & 12 Table 2 Output Frequency Configuration Settings Output Frequency (MHz) OP_FSEL Connect 13 & Connect 15 & Connect 17 & Connect 19 & 20 The ACS8944 EVB board comes configured with loop filter component values for a MHz input clock with a loop filter bandwidth of 2 khz. For other input frequencies and loop filter bandwidths the loop filter components (C7, C8, PCB Layout Recommendations The Evaluation Board PCB layout follows good layout practice for minimizing noise. Large area ground planes and supply decoupling are used. The analog and digital parts of the IC use separate ground and supply connections. The following guidelines should be considered when laying out a custom circuit board for the ACS8944 IC: 1. A generous ground plane should be provided around the IC to minimize noise and maximize the effectiveness of decoupling components. 2. Power supply decoupling capacitors should be placed as close as possible to the pins of the IC to decouple all power connections to the device. 3. Ensure that for the differential inputs and outputs, both tracks in each pair of tracks are matched in length. 4. Ensure that for the differential inputs and outputs, both tracks in each pair of tracks are of 50 Ohm impedance. Revision 1/January 2007 Semtech Corp. Page 5

6 Bill Of Materials Table 3 Evaluation Board Component Listing Reference Value Description PCB Qty. C1, C2, C3, C4, C5, C14, C16, C nf 0805 Capacitor (SMD). 8 C6, C13, C pf 0603 Capacitor (SMD). 3 C7, C9 15 uf 1812 Polarized Capacitor (Surface Mount). Low ESR Electrolytic. 2 C8, C nf 0805 Capacitor (SMD). 2 C11 22 nf 0603 Capacitor (SMD). 1 C uf Case D Polarised Capacitor (SMD). 1 JMP1 Header 10 x 2 Header, 10-Pin Dual Row R1, R3, R6, R8 82 R 0805 Resistor (SMD). 4 R2, R4, R5, R7 130 R 0805 Resistor (SMD). 4 R9, R10 75 R 0805 Resistor (SMD). 2 R11 10 K 0603 Resistor (SMD). 1 R K 0603 Resistor (SMD). 1 RF1 I- 5-Pin SMB - 90 deg. (PTH) 1.0mm Centre Hole. 1 RF2 I+ 5-Pin SMB - 90 deg. (PTH) 1.0mm Centre Hole. 1 RF3 O+ 5-Pin SMB - 90 deg. (PTH) 1.0mm Centre Hole. 1 RF4 O- 5-Pin SMB - 90 deg. (PTH) 1.0mm Centre Hole. 1 SK1 PCON2 5 mm Pitch Vertical Mount DC Connector. 1 SW1 SW SPST Push Button Single-Pole, Single-Throw Switch. 1 TP1 LOCKB Test Point. Not populated. 0 TP5 RESETB Test Point. Not populated. 0 TP6, TP8 + Test Point. Not populated. 0 TP7, TP9 - Test Point. Not populated. 0 U1 ACS8944_QFN_DUAL QFN 7 x 7 48L MLP Package Footprint. 1 Revision 1/January 2007 Semtech Corp. Page 6

7 Schematic Figure 4 EVB Schematic Revision 1/January 2007 Semtech Corp. Page 7

8 Abbreviations BOM DC EVB I/C I/O JAM PLL LVPECL MLP PCB PLL PTH RC SMB Bill of Materials Direct Current Evaluation Board Integrated Circuit Input/Output Jitter-Attenuating, Multiplying PLL Low Voltage Positive Emitter Coupled Logic Micro Leadframe Package Printed Circuit Board Phase Locked Loop Plated Through Hole Resistor/Capacitor Sub-Miniature type B- a connector type for use in DC to 4 GHz range Trademark Acknowledgements Table 4 Revision History Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. Revision Status/History The Revision Status, as shown in the top center of the document, may be DRAFT, PRELIMINARY, or FINAL, and refers to the status of the Device (not the document), with the design cycle. DRAFT status is used when the design is being realized but is not yet physically available, and the document content reflects the intention of the design. The document is raised to PRELIMINARY status when initial prototype devices are physically available, and the document content more accurately represents the realization of the design. The document is only raised to FINAL status after the device has been fully characterized. This is a FINAL release (Revision 1) of the ACS8944 EVB document. Changes made for this document revision are given in Table 4, together with a brief summary of previous revisions. For specific changes between earlier revisions, refer (where available) to those earlier revisions. Always use the current version of the document. Revision Reference Description of changes Rev. 1, January 2007 All pages Initial draft. Revision 1/January 2007 Semtech Corp. Page 8

9 Notes Revision 1/January 2007 Semtech Corp. Page 9

10 Ordering Information Table 5 Parts List Part Number Description ACS8944 EVB Evaluation Board (EVB). Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User s implementation and design practices. It is the responsibility of the User to ensure equipment using this device is compliant to any relevant standards. Contacts For Additional Information, contact the following: Semtech Corporation Advanced Communications Products Internet: USA: 200 Flynn Road, Camarillo, CA Tel: , Fax: FAR EAST: EUROPE: 12F No. 89 Sec. 5, Nanking E. Road, Taipei, 105, TWN, R.O.C. Tel: Fax: Semtech Ltd., Units 2 and 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN Tel: +44 (0) Fax: +44 (0) ISO9001 CERTIFIED Revision 1/January 2007 Semtech Corp. Page 10

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