VS-VSKT105.., VS-VSKH105.., VS-VSKL105.., VS-VSKN105.. Series

Transcription

1 ADD-A-PAK Generation II Power Modules Thyristor/Diode and Thyristor/Thyristor, 15 A FEATURES High voltage Industrial standard package Low thermal resistance UL approved file E78996 Designed and qualified for industrial level Material categorization: For definitions of compliance please see /doc?9991 PRODUCT SUMMARY I T(A) or I F(A) Type ADD-A-PAK 15 A Modules - Thyristor, Standard MECHANICAL DESCRIPTION The ADD-A-PAK Generation II, new generation of ADD-A-PAK module, combines the excellent thermal performances obtained by the usage of exposed direct bonded copper substrate, with advanced compact simple package solution and simplified internal structure with minimized number of interfaces. BENEFITS Excellent thermal performances obtained by the usage of exposed direct bonded copper substrate Up to 16 High surge capability Easy mounting on heatsink ELECTRICAL DESCRIPTION These modules are intended for general purpose high voltage applications such as high voltage regulated power supplies, lighting circuits, temperature and motor speed control circuits, UPS and battery charger. MAJOR RATINGS AND CHARACTERISTICS SYMBOL CHARACTERISTICS ALUES UNITS I T(A) or I F(A) 85 C 15 I O(RMS) As AC switch 5 I TSM, 5 Hz I FSM 6 Hz 94 I t 5 Hz 6 Hz 18.6 A ka s I t ka s RRM Range 4 to 16 T Stg -4 to 1 T J -4 to 1 C Revision: 1-Mar-14 1 Document Number: 9468 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

2 ELECTRICAL SPECIFICATIONS OLTAGE RATINGS TYPE NUMBER S-SK.15 OLTAGE CODE RRM, MAXIMUM REPETITIE PEAK REERSE OLTAGE RSM, MAXIMUM NON-REPETITIE PEAK REERSE OLTAGE DRM, MAXIMUM REPETITIE PEAK OFF-STATE OLTAGE, GATE OPEN CIRCUIT I RRM, I DRM AT 1 C ma ON-STATE CONDUCTION PARAMETER SYMBOL TEST CONDITIONS ALUES UNITS Maximum average on-state current (thyristors) I T(A) 18 conduction, half sine wave, Maximum average forward current (diodes) T C = 85 C 15 Maximum continuous RMS on-state current, as AC switch Maximum peak, one-cycle non-repetitive on-state or forward current Notes (1) I t for time t x = I t x t x () Average power = T(TO) x I T(A) r t x (I T(RMS) ) () 16.7 % x x I A < I < x I A (4) I > x I A I F(A) I O(RMS) or 5 I TSM or I FSM t = 1 ms No voltage t = 8. ms reapplied Sinusoidal 94 half wave, t = 1 ms % RRM initial T J = T J maximum 168 t = 8. ms reapplied 176 t = 1 ms No voltage t = 8. ms reapplied 18.6 Maximum I t for fusing I t Initial T J = T J maximum ka s t = 1 ms % RRM t = 8. ms reapplied 1.91 Maximum I t for fusing I t (1) t =.1 ms to 1 ms, no voltage reapplied ka T J = T J maximum s Low level ().98 Maximum value or threshold voltage () T(TO) T J = T J maximum High level (4) 1.1 Maximum value of on-state slope resistance Low level ().7 r () t T J = T J maximum High level (4).4 TM I TM = x I T(A) Maximum peak on-state or forward voltage T J = 5 C 1.8 FM I FM = x I F(A) Maximum non-repetitive rate of rise of T J = 5 C, from.67 DRM, di/dt 15 A/μs turned on current I TM = x I T(A), I g = 5 ma, t r <.5 μs, t p > 6 μs T J = 5 C, anode supply = 6, Maximum holding current I H 5 resistive load, gate open circuit ma Maximum latching current I L T J = 5 C, anode supply = 6, resistive load 4 I (RMS) I (RMS) A m Revision: 1-Mar-14 Document Number: 9468 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

3 TRIGGERING PARAMETER SYMBOL TEST CONDITIONS ALUES UNITS Maximum peak gate power P GM 1 Maximum average gate power P G(A) W Maximum peak gate current I GM A Maximum peak negative gate voltage - GM 1 Maximum gate voltage required to trigger GT T J = 5 C Anode supply = 6 resistive load.5 T J = -4 C 4. T J = 15 C 1.7 T J = 5 C Anode supply = 6 resistive load 15 ma T J = -4 C 7 T J = 15 C 8 Maximum gate voltage that will not trigger GD T J = 15 C, rated DRM applied.5 Maximum gate current that will not trigger I GD T J = 15 C, rated DRM applied 6 ma BLOCKING PARAMETER SYMBOL TEST CONDITIONS ALUES UNITS Maximum peak reverse and off-state leakage current at RRM, DRM I RRM, I DRM T J = 1 C, gate open circuit ma Maximum RMS insulation voltage INS 5 Hz (1 min) 6 (1 s) Maximum critical rate of rise of off-state voltage d/dt T J = 1 C, linear to.67 DRM /μs THERMAL AND MECHANICAL SPECIFICATIONS PARAMETER SYMBOL TEST CONDITIONS ALUES UNITS Junction operating temperature range T J -4 to 1 C Storage temperature range Maximum internal thermal resistance, junction to case per leg Typical thermal resistance, case to heatsink per module Mounting torque ± 1 % T Stg R thjc DC operation. R thcs Mounting surface flat, smooth and greased.1 to heatsink A mounting compound is recommended and 4 the torque should be rechecked after a period of hours to allow for the spread of the busbar compound. Approximate weight 75 g.7 oz. Case style JEDEC AAP GEN II (TO-4AA) C/W Nm R CONDUCTION PER JUNCTION SINE HALF WAE CONDUCTION RECTANGULAR WAE CONDUCTION DEICES UNITS SK C/W Note Table shows the increment of thermal resistance R thjc when devices operate at different conduction angles than DC Revision: 1-Mar-14 Document Number: 9468 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

4 Maximum allowable case temperature ( C) RthJC (DC) =. C/W Average on-state current (A) Fig. 1 - Current Ratings Characteristics Maximum average on-state power loss (W) RMS limit Per leg, Tj = 1 C Average on-state current (A) DC Fig. 4 - On-State Power Loss Characteristics Maximum allowable case temperature ( C) RthJC (DC) =. C/W DC Average on-state current (A) Fig. - Current Ratings Characteristics Peak half sine wave on-state current (A) At any rated load condition and with rated rrm applied following surge Initial Tj = Tj 6 Hz.8 5 Hz.s Per leg Number of equal amplitude half cycle current pulses (N) Fig. 5 - Maximum Non-Repetitive Surge Current Maximum average on-state power loss (W) RMS limit Per leg, Tj = 1 C Average on-state current (A) Fig. - On-State Power Loss Characteristics Peak half sine wave on-state current (A) Maximum Non-repetitive Surge Current ersus Pulse Train Duration. Control of conduction may not be maintained. Initial Tj = 1 C No oltage Reapplied Rated rrm reapplied Per leg Pulse train duration (s) Fig. 6 - Maximum Non-Repetitive Surge Current Revision: 1-Mar-14 4 Document Number: 9468 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

5 Maximum total on-state power loss (W) SK.15 Series 5 Per module Tj = 1 C Total RMS output current (A) Fig. 7 - On-State Power Loss Characteristics RthSA =.1 C/W. C/W. C/W.5 C/W.7 C/W 1 C/W C/W Maximum allowable ambient temperature ( C) Maximum total power loss (W) (sine) 18 (rect) RthSA =.1 C/W. C/W. C/W.5 C/W.7 C/W 1 C/W C/W x SK.15 Series single phase bridge connected Tj = 1 C Total output current (A) Fig. 8 - On-State Power Loss Characteristics Maximum allowable ambient temperature ( C) Maximum total power loss (W) (rect) x SK.15 Series three phase bridge connected Tj = 1 C Total output current (A) Fig. 9 - On-State Power Loss Characteristics RthSA =.1 C/W. C/W. C/W.5 C/W 1 C/W Maximum allowable ambient temperature ( C) Revision: 1-Mar-14 5 Document Number: 9468 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

6 Instantaneous on-state current (A) 1 Per leg Tj = 1 C Tj = 5 C Instantaneous on-state voltage () Fig. 1 - On-State oltage Drop Characteristics Transient thermal impedance Z thjc ( C/W) Steady state value RthJC =. C/W (DC operation) Per leg Square wave pulse duration (s) Fig Thermal Impedance Z thjc Characteristics Instantaneous gate voltage () Rectangular gate pulse a)recommended load line for rated di/dt:, ohms tr =.5 µs, tp >= 6 µs b)recommended load line for <= % rated di/dt: 15, 4 ohms 1 tr = 1 µs, tp >= 6 µs TJ = 15 C (b) TJ = 5 C (a) TJ = -4 C 1 (4) () () (1) GD IGD.1 SK. IRK.15.. Series Frequency Limited by PG(A) Instantaneous gate current (A) Fig. 1 - Gate Characteristics (1) PGM = W, tp = µs () PGM = 6 W, tp = 1 ms () PGM = W, tp = ms (4) PGM = 1 W, tp = 5 ms Revision: 1-Mar-14 6 Document Number: 9468 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

7 ORDERING INFORMATION TABLE Device code S-S K T 15 / 16 Note To order the optional hardware go to /doc?9517 CIRCUIT CONFIGURATION product - Module type - Circuit configuration (see Circuit Configuration table) 4 - Current code (15 A) 5 - oltage code (see oltage Ratings table) CIRCUIT DESCRIPTION CIRCUIT CONFIGURATION CODE CIRCUIT DRAWING (1) ~ SKT 1 Two SCRs doubler circuit T () () G1 K1 K G (4) (5) (7) (6) (1) ~ SKH 1 SCR/diode doubler circuit, positive control H () () G1 K1 (4) (5) (1) ~ SKL 1 SCR/diode doubler circuit, negative control L () () K G (7) (6) (1) - SKN 1 SCR/diode common anodes N () 4 5 () G1 K1 (4) (5) Dimensions LINKS TO RELATED DOCUMENTS /doc?9568 Revision: 1-Mar-14 7 Document Number: 9468 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

8 ADD-A-PAK Generation II - Thyristor Outline Dimensions DIMENSIONS in millimeters (inches) Fast-on tab.8 x.8 (.11 x.) 5 REF. ±.5 (1.18 ±.) 9 ±.5 (1 ±.) iti M5 x.8 Screws M5 x.8 18 (.7) REF ±.5 (.6 ±.) 6.7 ±. (.6 ±.1) 4 ±.5 (1 ±.) ± 1 (1.18 ±.9) 8 ±. (.15 ±.1).6 ±. (.89 ±.8) 6. ±. (.48 ±.8) ±.5 (.59 ±.) ±.5 (.79 ±.) ±.5 (.79 ±.) 9 ±.75 (.6 ±.) 5.8 ±.5 (.8 ±.1) 4 ±. (.157 ±.8) Document Number: 9568 For technical questions, contact: indmodules@vishay.com Revision: 11-Nov-8 1

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