Fabrication and Characterization of bulk FinFETs for Future Nano- Scale CMOS Technology

Transcription

1 nd US-Korea NanoForum, LA Fabrication and Characterization of bulk FinFETs for Future Nano- Scale CMOS Technology School of EECS and National Education Center for Semiconductor Technology Kyungpook National University, Daegu, Korea

2 ontents Introduction Simulation Study Fabrication of Bulk FinFETs by Spacer Technology by Selective Si3N4 Recess Device and SRAM Cell Characteristics Summary

3 ntroduction : Technology Roadmap Beyond Bulk LDD CMOS Performance Double/Triple-Gate SOI/SiGe G SOI PD/FD CMOS TG BG Double-Gate CMOS Si G SiGe SiGe CMOS (high mobility) G Fin Double/Triple-Gate FET Bulk Halo G Bulk LDD CMOS (Halo) Time

4 ntroduction Driving Force of CMOS Scaling-down: High Performance and High Integration Density A Promising Device Structure Double/Triple-Gate MOSFETs (or FinFETs) Why Double/Triple-Gate Transistor? Robustness against SCE Higher Current Drivability Good Subthreshold Swing S Si film G G D

5 ntroduction : Types of Double-Gate Transistors X S Z Y Top Gate Bottom Gate Current- Carrying Plane D (a) Type I Silicon Wafer Current- Carrying Plane Left Gate current direction D Z Y X Right Gate S Silicon Wafer (b) Type II Current- Carrying Plane S current direction Right Gate D Z Left Y Gate X Process technology of FinFET is easy and compatible with conventional fabrication process Silicon Wafer (c) Type III. P. Wong et al., IBM, vol. 87, no. 4, p.537, 1999, Proceedings of the IEEE

6 Types of Double/Triple-Gate Transistors Type Key Geometry Type I (Planar DG FETs) Type II (Vertical DG FETs) Type III (FinFETs) (Triple-Gate MOSFETs) Gate Position Top/Bottom Left/Right (or Cylinder) Left/Right Left/Right/Top Body Shape Horizontal Vertical Vertical Vertical Current Carrying Plane Horizontal Surfaces Side Surfaces Side Surfaces Side Surfaces Current Flow Direction Horizontal Vertical Horizontal Horizontal

7 ouble-gate Transistor (SOI FinFET) FinFET simple, self-aligned double-gates good process compatibility thickness control of fin body RIE damage on the channel, high resistance D. Hisamoto et al., UC Berkeley, p.1032, IEDM 1998

8 Body ody-tied Double/Triple-Gate MOSFET Using ulk Wafer (Bulk FinFET) Oxide Si Substrate Gate T FOX 0 H Fin x j W Fin Low wafer cost Low defect density Less back-bias effect High heat transfer rate to substrate Good process compatibility Schematic 3-D View J.-H. Lee., Korea/Japan/USA patent World 1 st Cost-Effective Double/Triple-Gate MOSFETs

9 ross-sectional Views (Body Structure) for 3- imensional Device Simulation Gate Fin body Gate Fin body SiO 2 SiO 2 Si sub Si sub SOI FinFET Bulk FinFET

10 -D Simulation Results V T (V) V L G =25 nm T OX =1.5 nm N a =1x10 19 cm -3 H Fin =70 nm x j, =66 nm Bulk SOI Fin Width (nm) V T and DIBL versus Fin Width DIBL (mv/0.9v) Subthreshold Swing (mv/dec) L G =25 nm T OX =1.5 nm qnsubt =Φ + 2φ + b for fully depleted body 2C ox T MS B V DS =0.9 V V DS =0.05 V N a =1x10 19 cm Fin Width (nm) J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003 Bulk SOI H Fin =70 nm x j, =66 nm Subthreshold Swing versus Fin Width

11 Body -D Simulation Results Oxide Si Substrate Gate T FOX H Fin Heat 0 x j W Fin 3-D Schematic View of Heat Transfer from Body to Substrate Device Temperature (K) L G =30 nm T OX =1.5 nm V DS =0.9 V substrate temperature=300 K SOI Bulk Gate Voltage (V) T~130 C Device Temperature versus Gate Voltage J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003

12 abrication Steps by Using Spacer Technology SiN 80 nm SiO 2 30 nm SiN 25 nm SiO 2 30 nm Si 4 Stack Layer Growth and Deposition SiN Removal Using Phosphoric Acid Poly-Si Spacer 30 nm Poly-Si Spacer Photo Lithography, SiN Etching, Poly-Si Depo., and Dry Etching Si

13 abrication Steps SiO 2, SiN, and SiO 2 Dry Etching Fin Dry Etching Top Si Width 25 nm Bottom Si Width 100 nm Si Fin Height 230 nm Fin body

14 abrication Steps SiO 2 Thin Ox., Filling, and Densification Wet Etch-back Field Oxide Thickness 80 nm SiO 2 Chemical Mechanical Polishing (CMP) / 27

15 irst Body-Tied Triple-Gate MOFET (Bulk infet) As +, 20 kev 3x10 15 /cm 2, 2 Fin Gate Poly-Si Etching 40 nm Poly-Si Drain Current (A) 10-7 V DS = 0.1 V Vbs = 0 V Vbs = -1 V Vbs = -2 V 50 nm 25 nm 40 nm Gate Voltage (V) I D -V GS Characteristics of 40 nm bulk NFiNFET T. Park et al., SNU/KNU, Nanomes T. Park et al., SNU/KNU, Physica E19, p.6, 2003

16 odified Structure of Bulk FinFET Top Si Width 25 nm Bottom Si Width 100 nm Si Fin Height 230 nm CMP and partial etch-back unclear Oxide Thick SiN liner formation & SiN liner only recessed Gate Electrode SiO 2 Si SiO 2 Fin SiN Clear Sidewall Open Planarization of the Top Surface of Poly-Si Gate Easy nano-scale patterning of gate poly-si Si Substrate E. Yoon, J.-H. Lee, and T. park, Korea/Japan/USA/Germany patent

17 ey Process Steps of Modified Bulk FinFET

18 EM Views of Key Process Steps Gate SiN Active Fin SiO 2 SiN Si Substrate Si Substrate SiN Liner Deposition SiN Recess Etch

19 EM Views of Key Process Steps Gate Etch Profiles Mask SiN Width = 70 nm, Poly-Si Neck Width = 47 nm Poly-Si Bottom Width = 64 nm SiN Gate Stack SiO 2 Si Substrate Gate Stack SiN Poly-Si Fins Si Substrate Along Gate Line Across Gate Line T. Park et al., Samung/SNU/KNU, Symp. on VLSI Tech., 2003

20 EM and TEM Views of Key Process Steps 30 nm SiN Liner Deposition Si Fin nm 99 nm fin Poly-Si Gate Poly-Si SiO nm SiN Si Substrate SiN Along Gate Line 12 nm fin body T. Park et al., Samung/SNU/KNU, IEDM., 2003

21 ulk FinFET Measurement I D -V GS plot: I D, DIBL, SS, and I sub I D, I SUB (A) V V BS = 0 V 1 V V DS =-0.05 V W Fin =25 nm H Fin =100 nm I SUB V DS =-1 V V I D V DS =1 V Gate Voltage (V) V DS =0.05 V L G =100 nm T Ox,top =1.8 nm T Ox,top =5.5 nm ISUB 0.05 V Measured I D -V GS of N and P type bulk FinFETs with drain bias high I on (~200 V GS =1.5 V) compared to that of first lot devices low I off (<0.2 V DS =1.0 V) I sub /I D < ~10-7

22 tatic Noise Margin (SNM) Bulk FinFET Planar MOSFET Pass Load Pull-Down W/L Load: 35 nm/90 nm Pass: 35 nm/90 nm Pull-Down: 50 nm/90 nm

23 ummary Briefly introduced key features of double/triple-gate FinFETs Bulk FinFETs were compared with SOI FinFETs Nearly the same device scalability Better wafer quality Better characteristics regarding the body connected to sub. Bulk FinFETs have been demonstrated experimentally First nano-scale bulk FinFET realized by using spacer technology Modified bulk FinFETs realized by adopting selective Si 3 N 4 recess Good device characteristics were achieved and SNM of 280 mv was obtained from SRAM cell at V CC of 1.2 V

24 -D Device Structure for Simulation Gate L G =25 nm T OX =1.5 nm SiO 2 body Si substrate body Si substrate

25 ey Process Steps for Thinning of the Fin Body