# Computer Organization and Architecture

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1 Computer Organization and Architecture Chapter 9 Computer Arithmetic Arithmetic & Logic Unit Performs arithmetic and logic operations on data everything that we think of as computing. Everything else in the computer is there to service this unit All ALUs handle integers Some may handle floating point (real) numbers May be separate FPU (math co-processor) FPU may be on separate chip (486DX +) ALU Inputs and Outputs Integer Representation We have the smallest possible alphabet: the symbols 0 & 1 represent everything No minus sign No period Signed-Magnitude Two s complement Benefits of 2 s complement One representation of zero Arithmetic works easily (see later) Negating is fairly easy 3 = Boolean complement gives Add 1 to LSB Geometric Depiction of Twos Complement Integers 1

3 Multiplication Example 1011 Multiplicand (11 dec) x 1101 Multiplier (13 dec) 1011 Partial products 0000 Note: if multiplier bit is 1 copy 1011 multiplicand (place value) 1011 otherwise zero Product (143 dec) Note: need double length result Simplifications for Binary Arithmetic Partial products are easy to compute: If bit is 0, partial product is 0 If bit is 1, partial product is multiplicand Can add each partial product as it is generated, so no storage is needed Binary multiplication of unsigned integers reduces to shift and add Control logic and registers 3 n bit registers, 1 bit carry register CF Register set up Q register <- multiplier M register <- multiplicand A register <- 0 CF <- 0 CF for carries after addition Product will be 2n bits in A Q registers Unsigned Binary Multiplication Multiplication Algorithm Repeat n times: If Q 0 = 1 Add M into A, store carry in CF Shift CF, A, Q right one bit so that: A n-1 <- CF Q n-1 <- A 0 Q 0 is lost Note that during execution Q contains bits from both product and multiplier Flowchart for Unsigned Binary Multiplication 3

4 Execution of Example Two s complement multiplication Shift and add does not work for two s complement numbers Previous example as 4-bit 2 s complement: -5 (1011) * -3 (1101) = -113 ( ) What is the problem? Partial products are 2n-bit products When the multiplicand is negative Each addition of the negative multiplicand must be negative number with 2n bits Sign extend multiplicand into partial product When the multiplier is negative When the multiplier (Q register) is negative, the bits of the operand do not correspond to shifts and adds needed 1101 <->1*2^3 + 1*2^2 + 1*2^0 = -(2^3 + 2^2 + 2^0) But we need -(2^1 + 2^0) Or sign extend both operands to double precision Not efficient The obvious solution Convert multiplier and multiplicand to unsigned integers Multiply If original signs differed, negate result But there are more efficient ways Fast multiplication Consider the product 6234 * We could do 4 single-digit multiplies and add partial sums Or we can express the product as 6234 * ( ) In binary x * can be expressed as x * ( ) = x * 60 We can reduce the number of operations to 2 by observing that = (64-4 = 60) x * = x * 2 6 x * 2 2 Each block of 1 s can be reduced to two operations In the worst case we still have only 8 operations 4

5 Booth s Algorithm Registers and Setup 3 n bit registers, 1 bit register logically to the right of Q (denoted as Q -1 ) Register set up Q register <- multiplier Q -1 <- 0 M register <- multiplicand A register <- 0 Count <- n Product will be 2n bits in A Q registers Booth s Algorithm Control Logic Bits of the multiplier are scanned one at a a time (the current bit Q 0 ) As bit is examined the bit to the right is considered also (the previous bit Q -1 ) Then: 00: Middle of a string of 0s, so no arithmetic operation. 01: End of a string of 1s, so add the multiplicand to the left half of the product (A). 10: Beginning of a string of 1s, so subtract the multiplicand from the left half of the product (A). 11: Middle of a string of 1s, so no arithmetic operation. Then shift A, Q, bit Q -1 right one bit using an arithmetic shift In an arithmetic shift, the msb remains unchanged Booth s Algorithm Example of Booth s Algorithm (7*3=21) Example: -3 * 2 = -6 (-3 = 1101) A Q Q -1 M C/P Comment Initial Values A <- A - 2 = >> A <- A >> A <- A - 2 = >>1 Example: 6 * -1 = -6 (1111 = -1) A Q Q -1 M C/P Comment Initial Values A <- A - 6 = >> >> >> >>1 A:Q = >>1 A:Q = -6 5

6 Example: 3 * -2 = -6 (1110 = -2) A Q Q -1 M C/P Comment Initial Values A <- A -(-2) = >> >> A <- A +(-2) = >>1 Division More complex than multiplication to implement (for computers as well as humans!) Some processors designed for embedded applications or digital signal processing lack a divide instruction Basically inverse of add and shift: shift and subtract Similar to long division taught in grade school >> 1 A:Q = -6 Unsigned Division In Principle 147 / 11 = 13 with remainder 4 Divisor Partial Remainders Quotient Dividend Remainder Unsigned Division algorithm Using same registers (A,M,Q, count) as multiplication Results of division are quotient and remainder Q will hold the quotient A will hold the remainder Initial values Q <- 0 A <- Dividend M <- Divisor Count <- n Unsigned Division Flowchart Example 6

7 Two s complement division More difficult than unsigned division Algorithm: 1. M <- Divisor, A:Q <- dividend sign extended to 2n bits; for example > ; 1001-> (note that 0111 = 7 and 1001 = -3) 2. Shift A:Q left 1 bit 3. If M and A have same signs, perform A <- A-M otherwise perform A <- A + M 4. The preceding operation succeeds if the sign of A is unchanged If successful, or (A==0 and Q==0) set Q 0 <- 1 If not successful, and (A!=0 or Q!=0) set Q 0 <- 0 and restore the previous value of A 5. Repeat steps 2,3,4 for n bit positions in Q 6. Remainder is in A. If the signs of the divisor and dividend were the same then the quotient is in Q, otherwise the correct quotient is 0-Q 2 s complement division examples 2 s complement division examples 2 s complement remainders 7 / 3 = 2 R 1 7 / -3 = -2 R 1-7 / 3 = -2 R -1-7 / -3 = 2 R -1 Here the remainder is defined as: Dividend = Quotient * Divisor + Remainder IEEE-754 Floating Point Numbers Format was discussed earlier in class Before IEEE-754 each family of computers had proprietary format: Cray,Vax, IBM Some Cray and IBM machines still use these formats Most are similar to IEEE formats but vary in details (bits in exponent or mantissa): IBM Base 16 exponent Vax, Cray: bias differs from IEEE Cannot make precise translations from one format to another Older binary scientific data not easily accessible IEEE 754 +/- 1.significand x 2 exponent Standard for floating point storage 32 and 64 bit standards 8 and 11 bit exponent respectively Extended formats (both mantissa and exponent) for intermediate results 7

8 Floating Point Examples FP Ranges For a 32 bit number 8 bit exponent +/ x Accuracy The effect of changing lsb of mantissa 23 bit mantissa x 10-7 About 6 decimal places Expressible Numbers Density of Floating Point Numbers Note that there is a tradeoff between density and precision For a floating point representation of n bits, if we increase the precision by using more bits in the mantissa then then we decrease the range If we increase the range by using more bits for the exponent then we decrease the density and precision Floating Point Arithmetic Operations FP Arithmetic +/- Addition and subtraction are more complex than multiplication and division Need to align mantissas Algorithm: Check for zeros Align significands (adjusting exponents) Add or subtract significands Normalize result 8

11 Guard bits Length of FPU registers > bits in mantissa Allows some preservation of precision when aligning exponents for addition Multiplying or dividing significands We have seen that results of arithmetic can vary when intermediate stores to memory are made in the course of a computation Rounding Conventional banker s rounding (round up if 0.5) has a slight bias toward the larger number To remove this bias use round-to-even: 1.5 -> > > > 4 Etc IEEE Rounding Four types are defined: Round to nearest (round to even) Round to + infinity Round to infinity Round to 0 Round to nearest If extra bits beyond mantissa are then round up If extra bits are 01 then truncate Special case: Round up if last representable bit is 1 Truncate if last representable bit is 0 Round to +/- infinity Useful for interval arithmetic Result of fp computation is expressed as an interval with upper and lower endpoints Width of interval gives measure of precision In numerical analysis algorithms are designed to minimize width of interval Round to 0 Simple truncation, obvious bias May be needed when explicitly rounding following operations with transcendental functions 11

12 Infinities Infinity treated as limiting case for real arithmetic Most arithmetic operations involving infinities produce infinity Quiet and Signaling NaNs NaN = Not a Number Signaling NaN causes invalid operation exception if used as operand Quiet NaN can propagate through arithmetic operations without raising an exception Signaling NaNs are useful for initial values of uninitialized variables Actual representation is implementation (processor) specific Quiet NaNs Denormalized Numbers Handle exponent underflow Provide values in the hole around 0 Unnormalized Numbers Denormalized numbers have fewer bits of precision than normal numbers When an operation is performed with a denormalized number and a normal number, the result is called an unnormal number Precision is unknown FPU can be programmed to raise an exception for unnormal computations 12

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