Functional Diagram 6N137, HCPL-2601/2611 HCPL-0600/0601/0611 ANODE CATHODE TRUTH TABLE (POSITIVE LOGIC) OUTPUT H H OFF NC

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1 High CMR, High Speed TTL Compatible Optocouplers Technical Data N HCNW HCNW HCNW HCPL- HCPL- HCPL- HCPL- HCPL- HCPL- HCPL- HCPL- HCPL- HCPL- HCPL- Features kv/µs Minimum Common Mode Rejection (CMR) at V CM = V for HCPL-X/ X, HCNW and kv/µs Minimum CMR at V CM = V for HCPL- X/X, HCNW High Speed: MBd Typical LSTTL/TTL Compatible Low Input Current Capability: ma Guaranteed ac and dc Performance over Temperature: - C to + C Available in -Pin DIP, SOIC-, Widebody Packages Strobable Output (Single Channel Products Only) Safety Approval UL Recognized - V rms for minute and V rms* for minute per UL CSA Approved VDE Approved with V IORM = V peak for HCPL- Option and V IORM = V peak for HCNW/X MIL-STD- Version Available (HCPL-XX/ XX) Applications Isolated Line Receiver Computer-Peripheral Interfaces Microprocessor System Interfaces Digital Isolation for A/D, D/A Conversion Switching Power Supply Instrument Input/Output Isolation Ground Loop Elimination Pulse Transformer Replacement Functional Diagram NC ANODE CATHODE NC N, HCPL-/ HCPL-// SHIELD TRUTH TABLE (POSITIVE LOGIC) LED ENABLE ON H OFF H ON L OFF L ON NC OFF NC V CC V E VO OUTPUT L H H H L H GND Power Transistor Isolation in Motor Drives Isolation of High Speed Logic Systems Description The N, HCPL-XX/XX/, HCNW/X are optically coupled gates that combine a GaAsP light emitting diode and an integrated high gain photo detector. An enable input allows the detector to be strobed. The output of the detector IC is ANODE CATHODE CATHODE ANODE HCPL-// HCPL-// SHIELD TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H V CC V O VO GND * V rms/ Minute rating is for HCNW/X and Option (N, HCPL-///, HCPL-) products only. A. µf bypass capacitor must be connected between pins and. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 an open collector Schottkyclamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of, V/µs for the HCPL-X/X and HCNW, and, V/µs for the HCPL-X/X and HCNW. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from - C to + C allowing troublefree system performance. The N, HCPL-XX, HCPL- XX, HCPL-, HCNW, and HCNWX are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate and are recommended for use in extremely high ground or induced noise environments. Selection Guide Widebody Minimum CMR -Pin DIP ( Mil) Small-Outline SO- ( Mil) Hermetic Input Single On- Single Dual Single Dual Single and Dual dv/dt V CM Current Output Channel Channel Channel Channel Channel Channel (V/µs) (V) (ma) Enable Package Package Package Package Package Packages NA NA YES N HCPL- HCNW NO HCPL- HCPL-, YES HCPL- HCPL- HCNW NO HCPL- HCPL-,, YES HCPL- HCPL- HCNW NO HCPL- HCPL-, YES HCPL- [], YES HCPL- [], YES HCPL-A [] HCPL-A [] NO HCPL-A [] HCPL-A [], [], YES HCPL-N [] HCPL-N [] NO HCPL-N [] HCPL-N [],. [] HCPL-9X [] HCPL-XX [] HCPL-XX [] Notes:. Technical data are on separate Agilent publications.. kv/µs with V CM = kv can be achieved using Agilent application circuit.. Enable is available for single channel products only, except for HCPL-9X devices.

3 Ordering Information Specify Part Number followed by Option Number (if desired). Example: HCPL-#XXX = V rms/ minute UL Rating Option* = VDE V IORM = Vpeak Option** = Gull Wing Surface Mount Option = Tape and Reel Packaging Option Option data sheets available. Contact Agilent sales representative or authorized distributor for information. *For N, HCPL-/// and HCPL- (-pin DIP products) only. **For HCPL- only. Combination of Option and Option is not available. Gull wing surface mount option applies to through hole parts only. Schematic N, HCPL-/ HCPL-// HCNW, HCNW/ ICC V CC + I O V O + V F HCPL-// HCPL-// I CC I O V CC V O V F SHIELD I E V E GND V F SHIELD I O V O USE OF A. µf BYPASS CAPACITOR CONNECTED BETWEEN PINS AND IS RECOMMENDED (SEE NOTE ). + SHIELD GND

4 Package Outline Drawings -pin DIP Package** (N, HCPL-///, HCPL-) 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER A XXXXZ YYWW UR OPTION CODE* DATE CODE. ±. (. ±.) UL RECOGNITION.9 (.) MAX.. (.) MAX.. (.) MAX. TYP (. +.) -.).9 (.) MIN.. (.) MIN.. ±. (. ±.) **JEDEC Registered Data (for N only).. (.) MAX.. ±. (. ±.) DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION "V" = OPTION OPTION NUMBERS AND NOT MARKED. -pin DIP Package with Gull Wing Surface Mount Option (N, HCPL-///, HCPL-) PAD LOCATION (FOR REFERENCE ONLY) 9. ±. (. ±.). (.).9 (.). ±. (. ±.).TYP. (.9) 9.9 (.) 9.9 (.9).9 (.). (.). (.). (.).9 (.) MAX.. (.) MAX..9 (.) MAX. 9. ±. (. ±.). ±. (. ±.) (. +.) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOM.

5 Small-Outline SO- Package (HCPL-/////).9 ±. (. ±.) PIN ONE XXX YWW. ±. (. ±.). (.) BSG.99 ±. (. ±.) TYPE NUMBER (LAST DIGITS) DATE CODE *. ±. (. ±.) X. (.). ±. (. ±.). (.) ~. ±. (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH). ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES) MAX.. (.) MIN.. ±. (. ±.) -Pin Widebody DIP Package (HCNW, HCNW/). ±. (. ±.). MAX. (.) A HCNWXXXX YYWW TYPE NUMBER DATE CODE 9. ±. (. ±.). (.) MAX. TYP.. (.) MAX.. (.) TYP (. +.) -.). (.).9 (.). (.) MIN.. (.) TYP.. ±. (. ±.). (.). (.) DIMENSIONS IN MILLIMETERS (INCHES).

6 -Pin Widebody DIP Package with Gull Wing Surface Mount Option (HCNW, HCNW/). ±. (. ±.) PAD LOCATION (FOR REFERENCE ONLY) 9. ±. (. ±.). (.) TYP.. ±. (. ±.). (.).9 (.). (.) MAX.. ±. (. ±.). MAX. (.). (.) MAX.. ±. (. ±.). (.) BSC. ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (.9 ±.) NOM (. +.) -.) Solder Reflow Temperature Profile (HCPL-XX and Gull Wing Surface Mount Option Parts) TEMPERATURE C T = C, C/SEC T = C,. C/SEC T = C,. C/SEC 9 TIME MINUTES Note: Use of nonchlorine activated fluxes is highly recommended.

7 Regulatory Information The N, HCPL-XX/XX/ XX, and HCNW/XX have been approved by the following organizations: UL Recognized under UL, Component Recognition Program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA. VDE Approved according to VDE /.9. (HCPL- Option and HCNW/X only) Insulation and Safety Related Specifications -pin DIP Widebody ( Mil) SO- ( Mil) Parameter Symbol Value Value Value Units Conditions Minimum External L() mm Measured from input terminals Air Gap (External to output terminals, shortest Clearance) distance through air. Minimum External L()... mm Measured from input terminals Tracking (External to output terminals, shortest Creepage) distance path along body. Minimum Internal... mm Through insulation distance, Plastic Gap conductor to conductor, usually (Internal Clearance) the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Minimum Internal NA NA. mm Measured from input terminals Tracking (Internal to output terminals, along Creepage) internal cavity. Tracking Resistance CTI Volts DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa IIIa Material Group (DIN VDE, /9, Table ) Option - surface mount classification is Class A in accordance with CECC.

8 VDE Insulation Related Characteristics (HCPL- Option Only) Description Symbol Characteristic Units Installation classification per DIN VDE /.9, Table for rated mains voltage V rms I-IV for rated mains voltage V rms I-III Climatic Classification // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, V PR Partial Discharge < pc V peak Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and sample test, V PR 9 t m = sec, Partial Discharge < pc V peak Highest Allowable Overvoltage* (Transient Overvoltage, t ini = sec) V IOTM V peak Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure, Thermal Derating curve.) Case Temperature T S C Input Current I S,INPUT ma Output Power P S,OUTPUT mw Insulation Resistance at T S, V IO = V R S 9 Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE ), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. VDE Insulation Related Characteristics (HCNW// Only) Description Symbol Characteristic Units Installation classification per DIN VDE /.9, Table for rated mains voltage V rms I-IV for rated mains voltage V rms I-III Climatic Classification (DIN IEC part ) // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, V PR Partial Discharge < pc V peak Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and sample test, V PR t m = sec, Partial Discharge < pc V peak Highest Allowable Overvoltage* (Transient Overvoltage, t ini = sec) V IOTM V peak Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure, Thermal Derating curve.) Case Temperature T S C Input Current I S,INPUT ma Output Power P S,OUTPUT mw Insulation Resistance at T S, V IO = V R S 9 Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE ), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.

9 9 Absolute Maximum Ratings* (No Derating Required up to C) Parameter Symbol Package** Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A - C Average Forward Input Current Single -Pin DIP ma Single SO- Widebody Dual -Pin DIP, Dual SO- Reverse Input Voltage V R -Pin DIP, SO- V Widebody Input Power Dissipation P I Widebody mw Supply Voltage V CC V ( Minute Maximum) Enable Input Voltage (Not to V E Single -Pin DIP V CC +. V Exceed V CC by more than Single SO- mv) Widebody Enable Input Current I E ma Output Collector Current I O ma Output Collector Voltage V O V (Selection for Higher Output Voltages up to V is Available.) Output Collector Power P O Single -Pin DIP mw Dissipation Single SO- Widebody Dual -Pin DIP, Dual SO- Lead Solder Temperature T LS -Pin DIP C for sec., (Through Hole Parts Only). mm below seating plane Widebody C for sec., up to seating plane Solder Reflow Temperature SO- and See Package Outline Profile (Surface Mount Parts Only) Option Drawings section *JEDEC Registered Data (for N only). **Ratings apply to all devices except otherwise noted in the Package column. C to C on JEDEC Registration. Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current, Low Level L * µa Input Current, High Level [] H ** ma Power Supply Voltage V CC.. V Low Level Enable Voltage V EL. V High Level Enable Voltage V EH. V CC V Operating Temperature T A - C Fan Out (at R L = kω) [] N TTL Loads Output Pull-up Resistor R L k Ω *The off condition can also be guaranteed by ensuring that V FL. volts. **The initial switching threshold is ma or less. It is recommended that. ma to ma be used for best performance and to permit at least a % LED degradation guardband. For single channel products only.

10 Electrical Specifications Over recommended temperature (T A = - C to + C) unless otherwise specified. All Typicals at V CC = V, T A = C. All enable test conditions apply to single channel products only. See note. Parameter Sym. Package Min. Typ. Max. Units Test Conditions Fig. Note High Level Output I OH * All. µa V CC =. V, V E =. V,,, Current V O =. V, = µa 9 Input Threshold I TH Single Channel.. ma V CC =. V, V E =. V,, 9 Current Widebody V O =. V, Dual Channel. I OL (Sinking) = ma Low Level Output V OL * -Pin DIP.. V V CC =. V, V E =. V,,,, 9 Voltage SO- = ma,, Widebody. I OL (Sinking) = ma High Level Supply I CCH Single Channel..* ma V E =. V V CC =. V Current. V E = V CC = ma Dual Channel Both Channels Low Level Supply I CCL Single Channel 9..* ma V E =. V V CC =. V Current. V E = V CC = ma Dual Channel Both Channels High Level Enable I EH Single Channel ma V CC =. V, V E =. V Current Low Level Enable I EL * ma V CC =. V, V E =. V 9 Current High Level Enable V EH. V 9 Voltage Low Level Enable V EL. V Voltage Input Forward V F -Pin DIP...* V T A = C = ma, Voltage SO-.. Widebody... T A = C.. Input Reverse BV R * -Pin DIP V I R = µa Breakdown SO- Voltage Widebody I R = µa, T A = C Input Diode V F / -Pin DIP -. mv/ C = ma Temperature T A SO- Coefficient Widebody -.9 Input Capacitance C IN -Pin DIP pf f = MHz, V F = V SO- Widebody *JEDEC registered data for the N. The JEDEC Registration specifies C to + C. HP specifies - C to + C.

11 Switching Specifications (AC) Over Recommended Temperature (T A = - C to + C), V CC = V, =. ma unless otherwise specified. All Typicals at T A = C, V CC = V. Parameter Sym. Package** Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay t PLH * ns T A = C R L = Ω, 9,,, Time to High C L = pf 9 Output Level Propagation Delay t PHL * ns T A = C,, Time to Low 9 Output Level Pulse Width t PHL - t PLH -Pin DIP. ns, 9,, 9 Distortion SO-, Widebody Propagation Delay t PSK ns,, Skew 9 Output Rise t r ns, 9 Time (-9%) Output Fall t f ns, 9 Time (9-%) Propagation Delay t ELH Single Channel ns R L = Ω,, Time of Enable C L = pf, from V EH to V EL V EL = V, V EH = V Propagation Delay t EHL Single Channel ns Time of Enable from V EL to V EH *JEDEC registered data for the N. **Ratings apply to all devices except otherwise noted in the Package column. Parameter Sym. Device Min. Typ. Units Test Conditions Fig. Note Logic High CM H N, V/µs V CM = V V CC = V, = ma,,, Common HCPL- V O(MIN) = V,, 9 Mode HCPL-/ R L = Ω, T A = C Transient HCNW Immunity HCPL-/,, V CM = V HCPL-/ HCNW HCPL-/,, V CM = kv HCPL-/ HCNW Logic Low CM L N, V/µs V CM = V V CC = V, =. ma,,, Common HCPL- V O(MAX) =. V,, 9 Mode HCPL-/ R L = Ω, T A = C Transient HCNW Immunity HCPL-/,, V CM = V HCPL-/ HCNW HCPL-/,, V CM = kv HCPL-/ HCNW

12 Package Characteristics All Typicals at T A = C. Parameter Sym. Package Min. Typ. Max. Units Test Conditions Fig. Note Input-Output I I-O * Single -Pin DIP µa % RH, t = s,, Insulation Single SO- V I-O = kv dc, T A = C Input-Output V ISO -Pin DIP, SO- V rms RH %, t = min,, Momentary With- Widebody T A = C, stand Voltage** OPT Input-Output R I-O -Pin DIP, SO- Ω V I-O = V dc,, Resistance Widebody T A = C T A = C Input-Output C I-O -Pin DIP, SO-. pf f = MHz, T A = C,, Capacitance Widebody.. Input-Input I I-I Dual Channel. µa RH %, t = s, Insulation V I-I = V Leakage Current Resistance R I-I Dual Channel Ω (Input-Input) Capacitance C I-I Dual -Pin DIP. pf f = MHz (Input-Input) Dual SO-. *JEDEC registered data for the N. The JEDEC Registration specifies C to C. HP specifies - C to C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE Insulation Characteristics Table (if applicable), your equipment level safety specification or Agilent Application Note entitled Optocoupler Input-Output Endurance Voltage. For N, HCPL-//// only. Notes:. Each channel.. Peaking circuits may produce transient input currents up to ma, ns maximum pulse width, provided average current does not exceed ma.. Peaking circuits may produce transient input currents up to ma, ns maximum pulse width, provided average current does not exceed ma.. Derate linearly above C free-air temperature at a rate of. mw/ C for the SOIC- package.. Bypassing of the power supply line is required, with a. µf ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure. Total lead length between both ends of the capacitor and the isolator pins should not exceed mm.. The JEDEC registration for the N specifies a maximum I OH of µa. HP guarantees a maximum I OH of µa.. The JEDEC registration for the N specifies a maximum I CCH of ma. HP guarantees a maximum I CCH of ma.. The JEDEC registration for the N specifies a maximum I CCL of ma. HP guarantees a maximum I CCL of ma. 9. The JEDEC registration for the N specifies a maximum I EL of. ma. HP guarantees a maximum I EL of -. ma.. The t PLH propagation delay is measured from the. ma point on the falling edge of the input pulse to the. V point on the rising edge of the output pulse.. The t PHL propagation delay is measured from the. ma point on the rising edge of the input pulse to the. V point on the falling edge of the output pulse.. t PSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature and specified test conditions.. See application section titled Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew for more information.. The t ELH enable propagation delay is measured from the. V point on the falling edge of the enable input pulse to the. V point on the rising edge of the output pulse.. The t EHL enable propagation delay is measured from the. V point on the rising edge of the enable input pulse to the. V point on the falling edge of the output pulse.. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., V O >. V).. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V O <. V).. For sinusoidal voltages, ( dv CM / dt) max = π f CM V CM (p-p).

13 9. No external pull up is required for a high logic state on the enable input. If the V E pin is not used, tying V E to V CC will result in improved CMR performance. For single channel products only.. Device considered a two-terminal device: pins,,, and shorted together, and pins,,, and shorted together.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the VDE Insulation Characteristics Table, if applicable.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the VDE Insulation Characteristics Table, if applicable.. Measured between the LED anode and cathode shorted together and pins through shorted together. For dual channel products only.. Measured between pins and shorted together, and pins and shorted together. For dual channel products only. I OH HIGH LEVEL OUTPUT CURRENT µa - V CC =. V V O =. V V E =. V* = µa * FOR SINGLE CHANNEL PRODUCTS ONLY - - V O OUTPUT VOLTAGE V -PIN DIP, SO- R L = Ω R L = KΩ R L = KΩ V CC = V T A = C V O OUTPUT VOLTAGE V WIDEBODY R L = Ω R L = KΩ R L = KΩ V CC = V T A = C T A TEMPERATURE C FORWARD INPUT CURRENT ma FORWARD INPUT CURRENT ma Figure. Typical High Level Output Current vs. Temperature. Figure. Typical Output Voltage vs. Forward Input Current. I TH INPUT THRESHOLD CURRENT ma V CC =. V V O =. V -PIN DIP, SO- R L = KΩ R L = KΩ R L = KΩ I TH INPUT THRESHOLD CURRENT ma V CC =. V V O =. V R L = KΩ WIDEBODY R L = Ω R L = KΩ T A TEMPERATURE C T A TEMPERATURE C Figure. Typical Input Threshold Current vs. Temperature.

14 V OL LOW LEVEL OUTPUT VOLTAGE V V CC =. V V E =. V* =. ma -PIN DIP, SO- I O = ma I O = 9. ma * FOR SINGLE CHANNEL PRODUCTS ONLY I O =. ma I O =. ma V OL LOW LEVEL OUTPUT VOLTAGE V I O = ma I O = 9. ma WIDEBODY V CC =. V V E =. V =. ma I O =. ma I O =. ma I OL LOW LEVEL OUTPUT CURRENT ma V CC =. V V E =. V* V OL =. V * FOR SINGLE CHANNEL PRODUCTS ONLY = - ma =. ma T A TEMPERATURE C T A TEMPERATURE C T A TEMPERATURE C Figure. Typical Low Level Output Voltage vs. Temperature. Figure. Typical Low Level Output Current vs. Temperature. FORWARD CURRENT ma... -PIN DIP, SO- T A = C + V F FORWARD CURRENT ma... WIDEBODY T A = C + V F V F FORWARD VOLTAGE V V F FORWARD VOLTAGE V Figure. Typical Input Diode Forward Characteristic. dv F /dt FORWARD VOLTAGE TEMPERATURE COEFFICIENT mv/ C PIN DIP, SO- -.. PULSE INPUT CURRENT ma dv F /dt FORWARD VOLTAGE TEMPERATURE COEFFICIENT mv/ C WIDEBODY -.. PULSE INPUT CURRENT ma Figure. Typical Temperature Coefficient of Forward Voltage vs. Input Current.

15 PULSE GEN. Z O = Ω t f = t r = ns INPUT MONITORING NODE R M SINGLE CHANNEL V CC GND.µF BYPASS *C L + V PULSE GEN. Z O = Ω t f = t r = ns INPUT R L MONITORING NODE OUTPUT V O MONITORING NODE R M DUAL CHANNEL V CC GND.µF BYPASS + V R L C L * OUTPUT V O MONITORING NODE *C L IS APPROXIMATELY pf WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. INPUT =. ma =. ma t PHL tplh OUTPUT V O. V Figure. Test Circuit for t PHL and t PLH. t P PROPAGATION DELAY ns V CC =. V =. ma t PHL, R L = Ω KΩ KΩ t PLH, R L = Ω t PLH, R L = KΩ t PLH, R L = KΩ T A TEMPERATURE C t P PROPAGATION DELAY ns 9 V CC =. V T A = C t PLH, R L = Ω t PLH, R L = KΩ t PLH, R L = KΩ t PHL, R L = Ω KΩ KΩ 9 PULSE INPUT CURRENT ma Figure 9. Typical Propagation Delay vs. Temperature. Figure. Typical Propagation Delay vs. Pulse Input Current. PWD PULSE WIDTH DISTORTION ns - - R L = kω R L = Ω R L = kω V CC =. V =. ma - - t r, t f RISE, FALL TIME ns 9 - V CC =. V =. ma R L = kω R L = kω R L = Ω t RISE t FALL R L = Ω, kω, kω - - T A TEMPERATURE C T A TEMPERATURE C Figure. Typical Pulse Width Distortion vs. Temperature. Figure. Typical Rise and Fall Time vs. Temperature.

16 PULSE GEN. Z O = Ω t f = t r = ns INPUT VE MONITORING NODE + V. ma V CC. µf BYPASS *C L RL OUTPUT V O MONITORING NODE INPUT V E OUTPUT V O t EHL t ELH. V. V. V GND *C L IS APPROXIMATELY pf WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure. Test Circuit for t EHL and t ELH. t E ENABLE PROPAGATION DELAY ns 9 - V CC =. V V EH =. V V EL = V =. ma t ELH, R L = kω t ELH, R L = kω t ELH, R L = Ω t EHL, R L = Ω, kω, kω - - T A TEMPERATURE C Figure. Typical Enable Propagation Delay vs. Temperature. V FF B A VCC SINGLE CHANNEL. µf BYPASS R L + V OUTPUT V O MONITORING NODE V FF B A VCC DUAL CHANNEL R L. µf BYPASS + V OUTPUT V O MONITORING NODE GND GND V CM + PULSE GENERATOR Z O = Ω V CM V CM (PEAK) V CM + PULSE GENERATOR Z O = Ω V SWITCH AT A: = ma V V O V O (MIN.) SWITCH AT B: =. ma V V O (MAX.) O. V CM H CM L Figure. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.

17 OUTPUT POWER P S, INPUT CURRENT I S HCPL- OPTION P S (mw) I S (ma) T S CASE TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S HCNWXXXX P S (mw) I S (ma) T S CASE TEMPERATURE C Figure. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE. GND BUS (BACK) V CC BUS (FRONT) NC.µF ENABLE NC OUTPUT mm MAX. (SEE NOTE ) SINGLE CHANNEL DEVICE ILLUSTRATED. Figure. Recommended Printed Circuit Board Layout.

18 SINGLE CHANNEL DEVICE V CC V V V CC Ω 9 Ω GND D* + V F SHIELD V E. µf BYPASS GND *DIODE D (N9 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. DUAL CHANNEL DEVICE CHANNEL SHOWN V CC V V V CC GND Ω D* + V F SHIELD 9 Ω. µf BYPASS GND Figure. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.

19 9 Propagation Delay, Pulse- Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output causing the output to change from high to low (see Figure ). Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of -% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS, RS, T-l, etc.). Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 9, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PLH or t PHL, and the longest propagation delay, either t PLH or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges.

20 DATA % INPUTS CLOCK V O. V V O %. V OUTPUTS DATA CLOCK t PSK t PSK t PSK Figure 9. Illustration of Propagation Delay Skew - t PSK. Figure. Parallel Data Transmission Example. For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: + () - or () - Europe: +9 () 9 China: Hong Kong: (+) India, Australia, New Zealand: (+) 9 Japan: (+ ) -(Domestic/International), or --(Domestic Only) Korea: (+) 9 Malaysia, Singapore: (+) Taiwan: (+) Data subject to change. Copyright Agilent Technologies, Inc. Obsoletes 9-EN March, 9-EN