C H A P T E R 14. CMOS Digital Logic Circuits

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1 C H A P T E R 14 CMOS Digital Logic Circuits

2 Introduction CMOS is by far the most popular technology for the implementation of digital systems. The small size, ease of fabrication, and low power consumption of MOSFET enable extremely high levels of integration of both logic and memory circuit. Digital electronics normally based on logic circuits. These circuits composed of logic gates depend on pulses of electricity to make the circuit work. A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits. 2

3 Figure 14.1 A logic inverter operating from a dc supply V DD.

4

5 Logic-Circuit Characterization The followings are major parameters usually used to characterize the performance of a logic-circuit family. Noise Margins Propagation Delay Power Dissipation Delay-Power Product Silicon Area Fan-in and Fan-out 5

6 Figure 14.3 Voltage transfer characteristic of an inverter. The VTC is approximated by three straight-line segments. Note the four parameters of the VTC (V OH, V OL, V IL, and V IH ) and their use in determining the noise margins (NM H and NM L ).

7 Figure 14.4

8 Noise Margins (1) The noise margin is an indicator of the ability to reject noise for a logic-circuit family and it is defined as Typical voltage transfer characteristic (VTC) of a logic inverter 8

9 Figure 14.6 The VTC of an ideal inverter.

10 Figure 14.7

11 Figure 14.8 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter that we shall study in Section 14.2.

12 Figure 14.9

13 Figure The resistively loaded MOS inverter and its VTC (Example 14.1). Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

14 Figure (a) Enhancement-load MOS inverter; (b) load curve; (c) construction to determine VTC; (d) the VTC. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

15 Power Dissipation E dissipation =CV DD2-1/2CV DD 2 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

16 Power Dissipation For power dissipation The need to minimize the power dissipation is motivated by the desire to pack an ever-increasing number of gates on a chip. It should be kept as low as possible, particularly for portable, battery-operated equipment. 2 types of power dissipation in a logic gate. Static power dissipation: it refers to dissipation in the absence of switching action. Dynamic power dissipation occurs only when the gate is switched. For an inverter operated from a power supply V DD,and driving a load capacitance C, the dynamic power dissipation is The advanced chip operated at V DD ~1V with 100 million transistors packed produces more than 100 W dynamic power dissipation when the operation frequency is above 1 GHz. 16

17 Figure An inverter fed with the ideal pulse in (a) provides at its output the pulse in (b). Two delay times are defined as indicated. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

18 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

19 Propagation Delay The dynamic performance of a logic-circuit family is characterized by the propagation delay of its basic inverter. Figure Definitions of propagation delays and transition times of the logic inverter. 19

20 Delay-Power Product High speed performance combined with low power dissipation is always desirable. However, the 2 requirements are often in conflict. Delay-Power product (DP) is a figure-of-merit for comparing logic circuit families and it defines as The unit of DP is joules! The lower DP figure of a logic family, the more effective it is. 20

21 Silicon Area and Fan-In/Fan-Out For Si area consideration, smaller area requirement enables the fabrication of a large number of gates per chip. There are 3 ways to reduce the area: Through advances in processing technology. Through circuit-design techniques. Through careful chip layout. For fan-in of a gate, it is the number of its inputs. For fan-out, itisthemaximum number of similar gates that a gate can drive while maintaining guaranteed specifications. Increasing the fan-out of the inverter will reduce V OH and hence NM H (example 5.10). 21

22 Digital IC Technologies and Logic-Circuit Family Technologies Members of each family are made with the same technology, have a similar circuit structure, and exhibit the same basic features. 22

23 CMOS Technology (1) CMOS has replaced NMOS, a dominant device employed in the early days of VLSI, because of the much lower power dissipation. CMOS has also replaced bipolar (BJT) in digital system due to CMOS logic circuits dissipate much less power than bipolar ones and thus more circuits can be packed on a chip. The high impedance of the MOS transistors allows the designer to use charge storage as a means for temporary storage of information. The feature size of the MOS transistors has decreased dramatically and permits very tight circuit packing. 23

24 Bipolar Technology 2 logic-circuit families based on BJT are TTL and ECL. The new version of TTL (transistor-transistor logic) operates BJT in non-saturating mode and therefore enjoys a higher speed the conventional one. However, the application of TTL declines with the advent of VLSI era. ECL (emitter-coupled logic) is the fastest logic among commercially available logic-circuit families. ECL is also used in VLSI circuit design if high speed is required and the designer is willing to accept high power dissipation and increased Si area. 24

25 BiCMOS and GaAs Technology BiCMOS combines the high operating speeds possible with BJTs (due to higher transconductance) with the low power dissipation in CMOS. It is used in special applications where the high performance justifies the more complex process technology it requires. GaAs (Gallium Arsenide) has higher carrier mobility and results in very high speed of operation. However, it remains the emerging technology and not commercially available. 25

26 Figure The CMOS inverter. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

27 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

28 28

29 Circuit Structure of A CMOS Inverter The inverter can be represented by a pair of switches operated in complementary fashion. Each switch is modeled by a finite on resistance, which is the source-drain resistance of the respective transistor. 29

30 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

31 Figure I p and I n as a function of V out. The intercepts of I p and I n (circled) represent the steady-state operation points of the CMOS inverter. 11 The curves are labeled by the input voltages: 0 = V in0 < V in1 < V in2 < V in3 < V in4 = V DD.

32 Figure Transfer curve of a CMOS inverter. 11 Points labeled A, B, C, and D correspond to those points labeled in Fig. 29.

33 Matching of Devices The term matching indicates the following conditions for Q N and Q P Matching of Q N and Q P provides equal transconductance equal current-driving capability in both pull-up and pull down directions equal propagation delays for t PLH and t PHL. symmetrical transfer characteristic 33

34 Figure The voltage-transfer characteristic of the CMOS inverter when Q N and Q P are matched. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

35 Static Operation of A CMOS Invertetr The voltage transfer characteristic of the CMOS inverter for matched Q N and Q P is shown below. The symmetry of VTC results in equal noise margins. (14.58), r=(kp/kn) 0.5 (14.59) 35

36 36

37 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

38 Vo: Vdd -> 0.5 Vdd Sat -> triode A calculation in complex and details can obtain Figure Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through Q N. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

39 Dynamic Operation of A CMOS Inverter A simple approximate but exact method for analyzing the dynamic operation of a CMOS inverter. (14.64) Vtn~ 0.2 V DD 39

40 Figure Equivalent circuits for determining the propagation delays (a) t PHL and (b) t PLH of the inverter. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

41 What contributes to the capacitor between the output node and ground? Internal capacitance from Q N and Q P. Interconnect wire between inverter output node and the input of next stage. Input capacitance of load gates. Figure Circuit for analyzing the propagation delay of the inverter formed by Q 1 and Q 2, which is driving a similar inverter formed by Q 3 and Q 4. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

42 Figure The Miller multiplication of the feedback capacitance C gd1. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

43 Ipeak is at Vi= 0.5 Vdd, while both Qn and Qp are in Sat Figure The current in the CMOS inverter versus the input voltage. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

44 Baisc Structure of CMOS Logic-Gate Sructure A CMOS logic circuit is in effect an extension of the CMOS inverter. The CMOS logic gate consists of 2 networks: pull-down network (PDN) and pull-up network (PUN). The PDN will conduct for all input combinations that require a low output and then pull the output down to ground Synthesizing PDN can be done by Expressing Y The input combinations that call for a high output will cause the PUN to conduct and pull the output up to V DD. Synthesizing PUN can be done by expressing Y. Figure Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

45 Examples of Pull-Down Networks Figure Examples of pull-down networks. usual and alternative circuit symbols Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

46 Examples of Pull-Up Networks Figure Examples of pull-up networks. usual and alternative circuit symbols Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

47 Figure Usual and alternative circuit symbols for MOSFETs. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

48 The Two-Input NOR Gate How to realize the two-input NOR function Y= A+B? Y= A+B = A B Y= A+B Figure A two-input CMOS NOR gate. 48

49 Figure A two-input CMOS NAND gate. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

50 A Complex Gate Note that PDN and PUN are dual networks: where a series branch exists in one, a parallel branch exists in the other. Duality can be always be used for PUN or PDN, however, the 2 networks are NOT necessarily duals. Figure CMOS realization of a complex gate. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

51 The Exclusive-OR Function (1) Exclusive-OR gates output a "high" (1) logic level if the inputs are at different logic levels, either 0 and 1 or 1 and 0. Conversely, they output a "low" (0) logic level if the inputs are at the same logic levels. The Exclusive-OR (sometimes called XOR) gate has both a symbol and a truth table pattern that is unique: Source: Lessons in Electric Circuits-Volume 4- Digital 51

52 The Exclusive-OR Function (2) How to realize the gate with more complex function Y= A B + A B? If Y is not a function of the complemented variables only, additional inverters are required. The type of exclusive-or requires 12 transistors for realization. Figure Realization of the exclusive-or (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (14.86). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (14.87). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 14.33). 52

53 Summary of the Synthesized Method The PDN can be most directly synthesized by expressing Y as a function of the un-complemented variables. If complemented variables appear, additional inverter will be required. The PUN can be most directly synthesized by expressing Y as a function of the complemented variables. If un-complemented variables appear, additional inverter will be required. The PDN can be obtained from PUN (and vice versa) using duality property. 53

54 DeMorgan s Therorem A mathematician named DeMorgan developed a pair of important rules regarding group complementation in Boolean algebra. Example Source: Lessons in Electric Circuits-Volume 4- Digital 54

55 Some Boolean Rules for Simplification (1) Source: Lessons in Electric Circuits-Volume 4- Digital 55

56 Some Boolean Rules for Simplification (2) Source: Lessons in Electric Circuits-Volume 4- Digital 56

57 Transistor Sizing (1) The W/L ratios for all devices are usually selected to provide the gate with current-driving capability equal to that of a basic inverter. The PDN (PUN) should be able to provide a capacitor discharging (charging) current at least equal to that of an NMOS (PMOS) transistor with W/L=n (W/L=p). This will guarantee a worst-case gate delay equal to that of the basic inverter. For a basic inverter design, n is usually 1.5~2 and, for a matched design, p = (μ n / μ p ) n. The derivation of equivalent W/L ratio is based on the on resistance. For transistors connected in series, For transistors connected in parallel, 57

58 Transistor Sizing (2) Proper sizing of a 4-input NOR and NAND gate. The NOR gate will require much larger area than the NAND gate. This is why NAND gates are preferred for implementing combinational logic functions in CMOS. Figure Proper transistor sizing for a four-input NOR gate. Note that n and p denote the W/L ratios of Q N and Q P, respectively, of the basic inverter. Figure Proper transistor sizing for a four-input NAND gate. Note that n and p denote the W/L ratios of Q N and Q P, respectively, of the basic inverter. 58

59 Transistor Sizing (3) How to provide the proper transistor W/L for the following case? 1.5p 3p 3p 3p n 2n 2n 2n Figure Circuit for Example

60 Effect of Fan-In and Fan-Out on Propagation Delay Each additional input to a CMOS gate requires two additional transistors, one NMOS and one PMOS. The additional transistors result in Chip area increase Total effective capacitance per gate increase Propagation delay increases (also for increased fan-out) Thus t p will increase with fan-in, a fact that imposes a practical limit on the fan-in of the NAND gate is about 4. Boolean function with gates of no more than 4 input is preferred. 60

61 Figure The MOSFET channel length has been reduced by a factor of 2 every about 5 years. This phenomenon, known as Moore s law is continuing. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

62 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

63 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

64 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

65 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

66 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

67 Figure The power-supply line in a deep submicron IC has non-zero resistance. The IR drops along the V DD line cause the voltages delivered to various circuits to differ. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

68 Figure The interconnect (wire) between two circuit blocks, A and B, on an IC chip has finite resistance and a capacitance to ground. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

69 Table 14.3 Summary of Important Characteristics of the CMOS Logic Inverter Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

70 Table 14.3 (Continued) Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

71 Figure Capture schematic of the CMOS inverter in Example

72 Figure Input output voltage transfer characteristic (VTC) of the CMOS inverter in Example 10.5 with m p /m n = 1 and m p /m n = 4. 72

73 Figure (a) Output voltage, and (b) supply current versus input voltage for the CMOS inverter in Example 10.5 with m p /m n = 1 and m p /m n = 4. 73

74 Figure Transient response of the CMOS inverter in Example 10.5 with m p /m n = 1 and m p /m n = 4. 74

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