C H A P T E R 14. CMOS Digital Logic Circuits
|
|
- Abigayle Gallagher
- 7 years ago
- Views:
Transcription
1 C H A P T E R 14 CMOS Digital Logic Circuits
2 Introduction CMOS is by far the most popular technology for the implementation of digital systems. The small size, ease of fabrication, and low power consumption of MOSFET enable extremely high levels of integration of both logic and memory circuit. Digital electronics normally based on logic circuits. These circuits composed of logic gates depend on pulses of electricity to make the circuit work. A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits. 2
3 Figure 14.1 A logic inverter operating from a dc supply V DD.
4
5 Logic-Circuit Characterization The followings are major parameters usually used to characterize the performance of a logic-circuit family. Noise Margins Propagation Delay Power Dissipation Delay-Power Product Silicon Area Fan-in and Fan-out 5
6 Figure 14.3 Voltage transfer characteristic of an inverter. The VTC is approximated by three straight-line segments. Note the four parameters of the VTC (V OH, V OL, V IL, and V IH ) and their use in determining the noise margins (NM H and NM L ).
7 Figure 14.4
8 Noise Margins (1) The noise margin is an indicator of the ability to reject noise for a logic-circuit family and it is defined as Typical voltage transfer characteristic (VTC) of a logic inverter 8
9 Figure 14.6 The VTC of an ideal inverter.
10 Figure 14.7
11 Figure 14.8 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter that we shall study in Section 14.2.
12 Figure 14.9
13 Figure The resistively loaded MOS inverter and its VTC (Example 14.1). Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
14 Figure (a) Enhancement-load MOS inverter; (b) load curve; (c) construction to determine VTC; (d) the VTC. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
15 Power Dissipation E dissipation =CV DD2-1/2CV DD 2 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
16 Power Dissipation For power dissipation The need to minimize the power dissipation is motivated by the desire to pack an ever-increasing number of gates on a chip. It should be kept as low as possible, particularly for portable, battery-operated equipment. 2 types of power dissipation in a logic gate. Static power dissipation: it refers to dissipation in the absence of switching action. Dynamic power dissipation occurs only when the gate is switched. For an inverter operated from a power supply V DD,and driving a load capacitance C, the dynamic power dissipation is The advanced chip operated at V DD ~1V with 100 million transistors packed produces more than 100 W dynamic power dissipation when the operation frequency is above 1 GHz. 16
17 Figure An inverter fed with the ideal pulse in (a) provides at its output the pulse in (b). Two delay times are defined as indicated. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
18 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
19 Propagation Delay The dynamic performance of a logic-circuit family is characterized by the propagation delay of its basic inverter. Figure Definitions of propagation delays and transition times of the logic inverter. 19
20 Delay-Power Product High speed performance combined with low power dissipation is always desirable. However, the 2 requirements are often in conflict. Delay-Power product (DP) is a figure-of-merit for comparing logic circuit families and it defines as The unit of DP is joules! The lower DP figure of a logic family, the more effective it is. 20
21 Silicon Area and Fan-In/Fan-Out For Si area consideration, smaller area requirement enables the fabrication of a large number of gates per chip. There are 3 ways to reduce the area: Through advances in processing technology. Through circuit-design techniques. Through careful chip layout. For fan-in of a gate, it is the number of its inputs. For fan-out, itisthemaximum number of similar gates that a gate can drive while maintaining guaranteed specifications. Increasing the fan-out of the inverter will reduce V OH and hence NM H (example 5.10). 21
22 Digital IC Technologies and Logic-Circuit Family Technologies Members of each family are made with the same technology, have a similar circuit structure, and exhibit the same basic features. 22
23 CMOS Technology (1) CMOS has replaced NMOS, a dominant device employed in the early days of VLSI, because of the much lower power dissipation. CMOS has also replaced bipolar (BJT) in digital system due to CMOS logic circuits dissipate much less power than bipolar ones and thus more circuits can be packed on a chip. The high impedance of the MOS transistors allows the designer to use charge storage as a means for temporary storage of information. The feature size of the MOS transistors has decreased dramatically and permits very tight circuit packing. 23
24 Bipolar Technology 2 logic-circuit families based on BJT are TTL and ECL. The new version of TTL (transistor-transistor logic) operates BJT in non-saturating mode and therefore enjoys a higher speed the conventional one. However, the application of TTL declines with the advent of VLSI era. ECL (emitter-coupled logic) is the fastest logic among commercially available logic-circuit families. ECL is also used in VLSI circuit design if high speed is required and the designer is willing to accept high power dissipation and increased Si area. 24
25 BiCMOS and GaAs Technology BiCMOS combines the high operating speeds possible with BJTs (due to higher transconductance) with the low power dissipation in CMOS. It is used in special applications where the high performance justifies the more complex process technology it requires. GaAs (Gallium Arsenide) has higher carrier mobility and results in very high speed of operation. However, it remains the emerging technology and not commercially available. 25
26 Figure The CMOS inverter. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
27 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
28 28
29 Circuit Structure of A CMOS Inverter The inverter can be represented by a pair of switches operated in complementary fashion. Each switch is modeled by a finite on resistance, which is the source-drain resistance of the respective transistor. 29
30 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
31 Figure I p and I n as a function of V out. The intercepts of I p and I n (circled) represent the steady-state operation points of the CMOS inverter. 11 The curves are labeled by the input voltages: 0 = V in0 < V in1 < V in2 < V in3 < V in4 = V DD.
32 Figure Transfer curve of a CMOS inverter. 11 Points labeled A, B, C, and D correspond to those points labeled in Fig. 29.
33 Matching of Devices The term matching indicates the following conditions for Q N and Q P Matching of Q N and Q P provides equal transconductance equal current-driving capability in both pull-up and pull down directions equal propagation delays for t PLH and t PHL. symmetrical transfer characteristic 33
34 Figure The voltage-transfer characteristic of the CMOS inverter when Q N and Q P are matched. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
35 Static Operation of A CMOS Invertetr The voltage transfer characteristic of the CMOS inverter for matched Q N and Q P is shown below. The symmetry of VTC results in equal noise margins. (14.58), r=(kp/kn) 0.5 (14.59) 35
36 36
37 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
38 Vo: Vdd -> 0.5 Vdd Sat -> triode A calculation in complex and details can obtain Figure Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through Q N. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
39 Dynamic Operation of A CMOS Inverter A simple approximate but exact method for analyzing the dynamic operation of a CMOS inverter. (14.64) Vtn~ 0.2 V DD 39
40 Figure Equivalent circuits for determining the propagation delays (a) t PHL and (b) t PLH of the inverter. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
41 What contributes to the capacitor between the output node and ground? Internal capacitance from Q N and Q P. Interconnect wire between inverter output node and the input of next stage. Input capacitance of load gates. Figure Circuit for analyzing the propagation delay of the inverter formed by Q 1 and Q 2, which is driving a similar inverter formed by Q 3 and Q 4. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
42 Figure The Miller multiplication of the feedback capacitance C gd1. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
43 Ipeak is at Vi= 0.5 Vdd, while both Qn and Qp are in Sat Figure The current in the CMOS inverter versus the input voltage. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
44 Baisc Structure of CMOS Logic-Gate Sructure A CMOS logic circuit is in effect an extension of the CMOS inverter. The CMOS logic gate consists of 2 networks: pull-down network (PDN) and pull-up network (PUN). The PDN will conduct for all input combinations that require a low output and then pull the output down to ground Synthesizing PDN can be done by Expressing Y The input combinations that call for a high output will cause the PUN to conduct and pull the output up to V DD. Synthesizing PUN can be done by expressing Y. Figure Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
45 Examples of Pull-Down Networks Figure Examples of pull-down networks. usual and alternative circuit symbols Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
46 Examples of Pull-Up Networks Figure Examples of pull-up networks. usual and alternative circuit symbols Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
47 Figure Usual and alternative circuit symbols for MOSFETs. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
48 The Two-Input NOR Gate How to realize the two-input NOR function Y= A+B? Y= A+B = A B Y= A+B Figure A two-input CMOS NOR gate. 48
49 Figure A two-input CMOS NAND gate. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
50 A Complex Gate Note that PDN and PUN are dual networks: where a series branch exists in one, a parallel branch exists in the other. Duality can be always be used for PUN or PDN, however, the 2 networks are NOT necessarily duals. Figure CMOS realization of a complex gate. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
51 The Exclusive-OR Function (1) Exclusive-OR gates output a "high" (1) logic level if the inputs are at different logic levels, either 0 and 1 or 1 and 0. Conversely, they output a "low" (0) logic level if the inputs are at the same logic levels. The Exclusive-OR (sometimes called XOR) gate has both a symbol and a truth table pattern that is unique: Source: Lessons in Electric Circuits-Volume 4- Digital 51
52 The Exclusive-OR Function (2) How to realize the gate with more complex function Y= A B + A B? If Y is not a function of the complemented variables only, additional inverters are required. The type of exclusive-or requires 12 transistors for realization. Figure Realization of the exclusive-or (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (14.86). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (14.87). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 14.33). 52
53 Summary of the Synthesized Method The PDN can be most directly synthesized by expressing Y as a function of the un-complemented variables. If complemented variables appear, additional inverter will be required. The PUN can be most directly synthesized by expressing Y as a function of the complemented variables. If un-complemented variables appear, additional inverter will be required. The PDN can be obtained from PUN (and vice versa) using duality property. 53
54 DeMorgan s Therorem A mathematician named DeMorgan developed a pair of important rules regarding group complementation in Boolean algebra. Example Source: Lessons in Electric Circuits-Volume 4- Digital 54
55 Some Boolean Rules for Simplification (1) Source: Lessons in Electric Circuits-Volume 4- Digital 55
56 Some Boolean Rules for Simplification (2) Source: Lessons in Electric Circuits-Volume 4- Digital 56
57 Transistor Sizing (1) The W/L ratios for all devices are usually selected to provide the gate with current-driving capability equal to that of a basic inverter. The PDN (PUN) should be able to provide a capacitor discharging (charging) current at least equal to that of an NMOS (PMOS) transistor with W/L=n (W/L=p). This will guarantee a worst-case gate delay equal to that of the basic inverter. For a basic inverter design, n is usually 1.5~2 and, for a matched design, p = (μ n / μ p ) n. The derivation of equivalent W/L ratio is based on the on resistance. For transistors connected in series, For transistors connected in parallel, 57
58 Transistor Sizing (2) Proper sizing of a 4-input NOR and NAND gate. The NOR gate will require much larger area than the NAND gate. This is why NAND gates are preferred for implementing combinational logic functions in CMOS. Figure Proper transistor sizing for a four-input NOR gate. Note that n and p denote the W/L ratios of Q N and Q P, respectively, of the basic inverter. Figure Proper transistor sizing for a four-input NAND gate. Note that n and p denote the W/L ratios of Q N and Q P, respectively, of the basic inverter. 58
59 Transistor Sizing (3) How to provide the proper transistor W/L for the following case? 1.5p 3p 3p 3p n 2n 2n 2n Figure Circuit for Example
60 Effect of Fan-In and Fan-Out on Propagation Delay Each additional input to a CMOS gate requires two additional transistors, one NMOS and one PMOS. The additional transistors result in Chip area increase Total effective capacitance per gate increase Propagation delay increases (also for increased fan-out) Thus t p will increase with fan-in, a fact that imposes a practical limit on the fan-in of the NAND gate is about 4. Boolean function with gates of no more than 4 input is preferred. 60
61 Figure The MOSFET channel length has been reduced by a factor of 2 every about 5 years. This phenomenon, known as Moore s law is continuing. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
62 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
63 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
64 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
65 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
66 Figure Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
67 Figure The power-supply line in a deep submicron IC has non-zero resistance. The IR drops along the V DD line cause the voltages delivered to various circuits to differ. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
68 Figure The interconnect (wire) between two circuit blocks, A and B, on an IC chip has finite resistance and a capacitance to ground. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
69 Table 14.3 Summary of Important Characteristics of the CMOS Logic Inverter Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
70 Table 14.3 (Continued) Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
71 Figure Capture schematic of the CMOS inverter in Example
72 Figure Input output voltage transfer characteristic (VTC) of the CMOS inverter in Example 10.5 with m p /m n = 1 and m p /m n = 4. 72
73 Figure (a) Output voltage, and (b) supply current versus input voltage for the CMOS inverter in Example 10.5 with m p /m n = 1 and m p /m n = 4. 73
74 Figure Transient response of the CMOS inverter in Example 10.5 with m p /m n = 1 and m p /m n = 4. 74
Chapter 10 Advanced CMOS Circuits
Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in
More informationGates & Boolean Algebra. Boolean Operators. Combinational Logic. Introduction
Introduction Gates & Boolean lgebra Boolean algebra: named after mathematician George Boole (85 864). 2-valued algebra. digital circuit can have one of 2 values. Signal between and volt =, between 4 and
More informationHere we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.
Outline Here we introduced () basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Circuit Logic Gate A logic gate is an elemantary building block
More informationGates. J. Robert Jump Department of Electrical And Computer Engineering Rice University Houston, TX 77251
Gates J. Robert Jump Department of Electrical And Computer Engineering Rice University Houston, T 77251 1. The Evolution of Electronic Digital Devices...1 2. Logical Operations and the Behavior of Gates...2
More informationAnalog & Digital Electronics Course No: PH-218
Analog & Digital Electronics Course No: PH-218 Lec-28: Logic Gates & Family Course Instructor: Dr. A. P. VAJPEYI Department of Physics, Indian Institute of Technology Guwahati, India 1 Digital Logic Gates
More informationEXPERIMENT 3: TTL AND CMOS CHARACTERISTICS
EXPERIMENT 3: TTL AND CMOS CHARACTERISTICS PURPOSE Logic gates are classified not only by their logical functions, but also by their logical families. In any implementation of a digital system, an understanding
More informationInternational Journal of Electronics and Computer Science Engineering 1482
International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant
More informationCMOS Logic Integrated Circuits
CMOS Logic Integrated Circuits Introduction CMOS Inverter Parameters of CMOS circuits Circuits for protection Output stage for CMOS circuits Buffering circuits Introduction Symetrical and complementary
More informationModule 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits
Module 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits Objectives In this lecture you will learn the following Introduction Logical Effort of an Inverter
More informationPass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches).
Pass Gate Logic n alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Switch Network Regeneration is performed via a buffer. We have already
More informationECE124 Digital Circuits and Systems Page 1
ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly
More informationModule 7 : I/O PADs Lecture 33 : I/O PADs
Module 7 : I/O PADs Lecture 33 : I/O PADs Objectives In this lecture you will learn the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up
More informationBOOLEAN ALGEBRA & LOGIC GATES
BOOLEAN ALGEBRA & LOGIC GATES Logic gates are electronic circuits that can be used to implement the most elementary logic expressions, also known as Boolean expressions. The logic gate is the most basic
More informationGates, Circuits, and Boolean Algebra
Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks
More informationThese help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption
Basic Properties of a Digital Design These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption Which of these criteria is important
More information. HIGH SPEED .LOW POWER DISSIPATION .COMPATIBLE WITH TTL OUTPUTS M54HCT27 M74HCT27 TRIPLE 3-INPUT NOR GATE. tpd = 9 ns (TYP.
M54HCT27 M74HCT27 TRIPLE 3-INPUT NOR GATE. HIGH SPEED tpd = 9 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =1µA (MAX.) AT T A =25 C.COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT
More information5.11 THE JUNCTION FIELD-EFFECT TRANSISTOR (JFET)
This material is from a previous edition of Microelectronic Circuits. These sections provide valuable information, but please note that the references do not correspond to the 6th or 7th edition of the
More informationEfficient Interconnect Design with Novel Repeater Insertion for Low Power Applications
Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,
More information1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
More informationNEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.
CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim
More informationELEC 2210 - EXPERIMENT 1 Basic Digital Logic Circuits
Objectives ELEC - EXPERIMENT Basic Digital Logic Circuits The experiments in this laboratory exercise will provide an introduction to digital electronic circuits. You will learn how to use the IDL-00 Bit
More informationMADR-009269-0001TR. Single Driver for GaAs FET or PIN Diode Switches and Attenuators Rev. V1. Functional Schematic. Features.
Features High Voltage CMOS Technology Complementary Outputs Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost Plastic SOIC-8 Package 100% Matte Tin Plating over
More informationCHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS
CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS Chapter Outline 10.1 The Two-Stage CMOS Op Amp 10.2 The Folded-Cascode CMOS Op Amp 10.3 The 741 Op-Amp Circuit 10.4 DC Analysis of the 741 10.5 Small-Signal Analysis
More informationCD4013BC Dual D-Type Flip-Flop
CD4013BC Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors.
More informationCMOS, the Ideal Logic Family
CMOS, the Ideal Logic Family INTRODUCTION Let s talk about the characteristics of an ideal logic family. It should dissipate no power, have zero propagation delay, controlled rise and fall times, and have
More informationMOS Transistors as Switches
MOS Transistors as Switches G (gate) nmos transistor: Closed (conducting) when Gate = 1 (V DD ) D (drain) S (source) Oen (non-conducting) when Gate = 0 (ground, 0V) G MOS transistor: Closed (conducting)
More informationField-Effect (FET) transistors
Field-Effect (FET) transistors References: Hayes & Horowitz (pp 142-162 and 244-266), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and,
More informationCD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated
More informationCD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
October 1987 Revised March 2002 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits
More informationSequential 4-bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationCD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-
More informationOptimization and Comparison of 4-Stage Inverter, 2-i/p NAND Gate, 2-i/p NOR Gate Driving Standard Load By Using Logical Effort
Optimization and Comparison of -Stage, -i/p NND Gate, -i/p NOR Gate Driving Standard Load By Using Logical Effort Satyajit nand *, and P.K.Ghosh ** * Mody Institute of Technology & Science/ECE, Lakshmangarh,
More informationANALOG & DIGITAL ELECTRONICS
ANALOG & DIGITAL ELECTRONICS Course Instructor: Course No: PH-218 3-1-0-8 Dr. A.P. Vajpeyi E-mail: apvajpeyi@iitg.ernet.in Room No: #305 Department of Physics, Indian Institute of Technology Guwahati,
More informationEGR 278 Digital Logic Lab File: N278L3A Lab # 3 Open-Collector and Driver Gates
EGR 278 Digital Logic Lab File: N278L3A Lab # 3 Open-Collector and Driver Gates A. Objectives The objectives of this laboratory are to investigate: the operation of open-collector gates, including the
More informationMADR-009190-0001TR. Quad Driver for GaAs FET or PIN Diode Switches and Attenuators Rev. 4. Functional Schematic. Features.
Features High Voltage CMOS Technology Four Channel Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost Lead-Free SOIC-16 Plastic Package Halogen-Free Green Mold Compound
More informationSo far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
More informationTHE INVERTER DYNAMICS
Dynamic Behavior THE IVERTER DYAMIC Propagation Delay, T p Defines how quickly output is affected by input Measured between 5% transition from input to output t plh defines delay for output going from
More informationChapter 6 TRANSISTOR-TRANSISTOR LOGIC. 3-emitter transistor.
Chapter 6 TRANSISTOR-TRANSISTOR LOGIC The evolution from DTL to TTL can be seen by observing the placement of p-n junctions. For example, the diode D2 from Figure 2 in the chapter on DTL can be replaced
More informationCMOS Thyristor Based Low Frequency Ring Oscillator
CMOS Thyristor Based Low Frequency Ring Oscillator Submitted by: PIYUSH KESHRI BIPLAB DEKA 4 th year Undergraduate Student 4 th year Undergraduate Student Electrical Engineering Dept. Electrical Engineering
More informationStatic-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology
Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department
More informationCO2005: Electronics I (FET) Electronics I, Neamen 3th Ed. 1
CO2005: Electronics I The Field-Effect Transistor (FET) Electronics I, Neamen 3th Ed. 1 MOSFET The metal-oxide-semiconductor field-effect transistor (MOSFET) becomes a practical reality in the 1970s. The
More informationCMOS Binary Full Adder
CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry - - Table of Contents Key Terminology...- - Introduction...- 3 - Design Architectures...-
More informationCpE358/CS381. Switching Theory and Logical Design. Class 4
Switching Theory and Logical Design Class 4 1-122 Today Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification
More information.LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M74HC154 4 TO 16 LINE DECODER/DEMULTIPLEXER. HIGH SPEED tpd = 15 ns (TYP.) at VCC =5V
. HIGH SPEED tpd = 15 ns (TYP.) at VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE
More informationMADR-009443-0001TR. Quad Driver for GaAs FET or PIN Diode Switches and Attenuators. Functional Schematic. Features. Description. Pin Configuration 2
Features Functional Schematic High Voltage CMOS Technology Four Channel Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost 4x4 mm, 20-lead PQFN Package 100% Matte
More informationCD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
More informationDesign of Energy Efficient Low Power Full Adder using Supply Voltage Gating
Design of Energy Efficient Low Power Full Adder using Supply Voltage Gating S.Nandhini 1, T.G.Dhaarani 2, P.Kokila 3, P.Premkumar 4 Assistant Professor, Dept. of ECE, Nandha Engineering College, Erode,
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More information10 BIT s Current Mode Pipelined ADC
10 BIT s Current Mode Pipelined ADC K.BHARANI VLSI DEPARTMENT VIT UNIVERSITY VELLORE, INDIA kothareddybharani@yahoo.com P.JAYAKRISHNAN VLSI DEPARTMENT VIT UNIVERSITY VELLORE, INDIA pjayakrishnan@vit.ac.in
More informationMM74HC4538 Dual Retriggerable Monostable Multivibrator
MM74HC4538 Dual Retriggerable Monostable Multivibrator General Description The MM74HC4538 high speed monostable multivibrator (one shots) is implemented in advanced silicon-gate CMOS technology. They feature
More informationDesign and analysis of flip flops for low power clocking system
Design and analysis of flip flops for low power clocking system Gabariyala sabadini.c PG Scholar, VLSI design, Department of ECE,PSNA college of Engg and Tech, Dindigul,India. Jeya priyanka.p PG Scholar,
More informationCD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate
Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits cotructed
More informationChapter 8 Differential and Multistage Amplifiers. EE 3120 Microelectronics II
1 Chapter 8 Differential and Multistage Amplifiers Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4.
More informationCD4013BC Dual D-Type Flip-Flop
Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit cotructed with N- and P-channel enhancement mode traistors. Each
More informationNotes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits
Notes about Small Signal Model for EE 40 Intro to Microelectronic Circuits 1. Model the MOSFET Transistor For a MOSFET transistor, there are NMOS and PMOS. The examples shown here would be for NMOS. Figure
More informationDigital Electronics Detailed Outline
Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept
More informationLecture 060 Push-Pull Output Stages (1/11/04) Page 060-1. ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002
Lecture 060 PushPull Output Stages (1/11/04) Page 0601 LECTURE 060 PUSHPULL OUTPUT STAGES (READING: GHLM 362384, AH 226229) Objective The objective of this presentation is: Show how to design stages that
More informationMULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
CHAPTER3 QUESTIONS MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. ) If one input of an AND gate is LOW while the other is a clock signal, the output
More information3-input EXCLUSIVE-OR gate. The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function.
Rev. 02 3 September 2007 Product data sheet 1. General description The provides a 3-input EXCLUSIVE-OR function. The input can be driven from either 3.3 or 5 V devices. This feature allows the use of these
More informationHCC4541B HCF4541B PROGRAMMABLE TIMER
HCC4541B HCF4541B PROGRAMMABLE TIMER 16 STAGE BINARI COUNTER LOW SYMMETRICAL OUTPUT RESISTANCE, TYPICALLY 100 OHM AT DD = 15 OSCILLATOR FREQUENCY RANGE : DC TO 100kHz AUTO OR MASTER RESET DISABLES OSCIL-
More informationCMOS Power Consumption and C pd Calculation
CMOS Power Consumption and C pd Calculation SCAA035B June 1997 1 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or
More informationLAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS
LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS Objective In this experiment you will study the i-v characteristics of an MOS transistor. You will use the MOSFET as a variable resistor and as a switch. BACKGROUND
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationHCF4001B QUAD 2-INPUT NOR GATE
QUAD 2-INPUT NOR GATE PROPAGATION DELAY TIME: t PD = 50ns (TYP.) at V DD = 10V C L = 50pF BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V
More information3.Basic Gate Combinations
3.Basic Gate Combinations 3.1 TTL NAND Gate In logic circuits transistors play the role of switches. For those in the TTL gate the conducting state (on) occurs when the baseemmiter signal is high, and
More informationDesign Verification and Test of Digital VLSI Circuits NPTEL Video Course. Module-VII Lecture-I Introduction to Digital VLSI Testing
Design Verification and Test of Digital VLSI Circuits NPTEL Video Course Module-VII Lecture-I Introduction to Digital VLSI Testing VLSI Design, Verification and Test Flow Customer's Requirements Specifications
More informationBasic Logic Gates Richard E. Haskell
BASIC LOGIC GATES 1 E Basic Logic Gates Richard E. Haskell All digital systems are made from a few basic digital circuits that we call logic gates. These circuits perform the basic logic functions that
More informationMC14008B. 4-Bit Full Adder
4-Bit Full Adder The MC4008B 4bit full adder is constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure. This device consists of four full adders with fast
More informationHCF4028B BCD TO DECIMAL DECODER
BCD TO DECIMAL DECODER BCD TO DECIMAL DECODING OR BINARY TO OCTAL DECODING HIGH DECODED OUTPUT DRIVE CAPABILITY "POSITIVE LOGIC" INPUTS AND OUTPUTS: DECODED OUTPUTS GO HIGH ON SELECTION MEDIUM SPEED OPERATION
More informationStep Response of RC Circuits
Step Response of RC Circuits 1. OBJECTIVES...2 2. REFERENCE...2 3. CIRCUITS...2 4. COMPONENTS AND SPECIFICATIONS...3 QUANTITY...3 DESCRIPTION...3 COMMENTS...3 5. DISCUSSION...3 5.1 SOURCE RESISTANCE...3
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. fmax = 48 MHz (TYP.
M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. HIGH SPEED fmax = 48 MHz (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.)
More informationSequential Logic Design Principles.Latches and Flip-Flops
Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch
More informationHIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
DESCRIPTION The, /6 single-channel and /6 dual-channel optocouplers consist of a 5 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationMM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides
More informationHCC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP
DUAL-J-K MASTER-SLAVE FLIP-FLOP. SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER HIGH OR LOW MEDIUM SPEED OPERATION - 16MHz (typ. clock toggle rate
More informationInterfacing 3V and 5V applications
Authors: Tinus van de Wouw (Nijmegen) / Todd Andersen (Albuquerque) 1.0 THE NEED FOR TERFACG BETWEEN 3V AND 5V SYSTEMS Many reasons exist to introduce 3V 1 systems, notably the lower power consumption
More informationDesign of a Fully Differential Two-Stage CMOS Op-Amp for High Gain, High Bandwidth Applications
Design of a Fully Differential Two-Stage CMOS Op-Amp for High Gain, High Bandwidth Applications Rajkumar S. Parihar Microchip Technology Inc. Rajkumar.parihar@microchip.com Anu Gupta Birla Institute of
More informationContent Map For Career & Technology
Content Strand: Applied Academics CT-ET1-1 analysis of electronic A. Fractions and decimals B. Powers of 10 and engineering notation C. Formula based problem solutions D. Powers and roots E. Linear equations
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
More informationINSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043
INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043 ELECTRONICS AND COMMUNICATION ENGINEERING Course Title VLSI DESIGN Course Code 57035 Regulation R09 COURSE DESCRIPTION Course Structure
More informationDATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
More informationLecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors.
Whites, EE 320 Lecture 30 Page 1 of 8 Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors. There are two different environments in which MOSFET amplifiers are found, (1) discrete circuits and
More informationDESIGN OF A 7490-LIKE DECADE-COUNTER INTEGRATED CIRCUIT, USING GaAs MESFET DCFL FAMILY, FOR FREQUENCIES UP TO 1 GHz.
DESIGN OF A 7490-LIKE DECADE-COUNTER INTEGRATED CIRCUIT, USING GaAs MESFET DCFL FAMILY, FOR FREQUENCIES UP TO 1 GHz. Luiz Carlos Kretly and Daniel Cardoso de Souza Centro de Componentes Semicondutores
More informationSeries and Parallel Circuits
Direct Current (DC) Direct current (DC) is the unidirectional flow of electric charge. The term DC is used to refer to power systems that use refer to the constant (not changing with time), mean (average)
More informationA New Low Power Dynamic Full Adder Cell Based on Majority Function
World Applied Sciences Journal 4 (1): 133-141, 2008 ISSN 1818-4952 IDOSI Publications, 2008 A New Low Power Dynamic Full Adder Cell Based on Majority Function 1 Vahid Foroutan, 2 Keivan Navi and 1 Majid
More informationMM74HC273 Octal D-Type Flip-Flops with Clear
MM74HC273 Octal D-Type Flip-Flops with Clear General Description The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise
More informationUsing Op Amps As Comparators
TUTORIAL Using Op Amps As Comparators Even though op amps and comparators may seem interchangeable at first glance there are some important differences. Comparators are designed to work open-loop, they
More informationCHAPTER 16 MEMORY CIRCUITS
CHPTER 6 MEMORY CIRCUITS Chapter Outline 6. atches and Flip-Flops 6. Semiconductor Memories: Types and rchitectures 6.3 Random-ccess Memory RM Cells 6.4 Sense-mplifier and ddress Decoders 6.5 Read-Only
More informationLayout of Multiple Cells
Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed
More informationDigital circuits make up all computers and computer systems. The operation of digital circuits is based on
Digital Logic Circuits Digital circuits make up all computers and computer systems. The operation of digital circuits is based on Boolean algebra, the mathematics of binary numbers. Boolean algebra is
More informationDesign of Low Power One-Bit Hybrid-CMOS Full Adder Cells
Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells Sushil B. Bhaisare 1, Sonalee P. Suryawanshi 2, Sagar P. Soitkar 3 1 Lecturer in Electronics Department, Nagpur University, G.H.R.I.E.T.W. Nagpur,
More informationThree-Phase Dual-Rail Pre-Charge Logic
Infineon Page 1 CHES 2006 - Yokohama Three-Phase Dual-Rail Pre-Charge Logic L. Giancane, R. Luzzi, A. Trifiletti {marco.bucci, raimondo.luzzi}@infineon.com {giancane, trifiletti}@die.mail.uniroma1.it Summary
More informationObsolete Product(s) - Obsolete Product(s)
SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR INTERNAL LOOK-AHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOW-POWER TTL COMPATIBILITY STANDARDIZED
More information+5 V Powered RS-232/RS-422 Transceiver AD7306
a FEATURES RS- and RS- on One Chip Single + V Supply. F Capacitors Short Circuit Protection Excellent Noise Immunity Low Power BiCMOS Technology High Speed, Low Skew RS- Operation C to + C Operations APPLICATIONS
More informationCHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
More information3 The TTL NAND Gate. Fig. 3.1 Multiple Input Emitter Structure of TTL
3 The TTL NAND Gate 3. TTL NAND Gate Circuit Structure The circuit structure is identical to the previous TTL inverter circuit except for the multiple emitter input transistor. This is used to implement
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey Homework #2 EECS 141 Due Friday, February 6, 5pm, box in 240 Cory 1. Suppose you
More informationHCF4010B HEX BUFFER/CONVERTER (NON INVERTING)
HEX BUFFER/CONVERTER (NON INVERTING) PROPAGATION DELAY TIME: t PD = 50ns (Typ.) at V DD = 10V C L = 50pF HIGH TO LOW LEVEL LOGIC CONVERSION MULTIPLEXER: 1 TO 6 OR 6 TO 1 HIGH "SINK" AND "SOURCE" CURRENT
More information