# Boolean Representations and Combinatorial Equivalence

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1 Chapter 2 Boolean Representations and Combinatorial Equivalence This chapter introduces different representations of Boolean functions. It then discuss the applications of these representations for proving Boolean equivalence between two circuits. 2.1 Representing Boolean functions The objective is to decide whether two circuits compute the same function. We will consider pure Boolean circuits, that is, circuits with no states. The result of the circuit only depends on the current values of its outputs. It does not depend on previous values of these inputs. Regarding terminology, the inputs of a circuits are called primary inputs and the outputs of a circuits are called primary outputs. This is to make the difference of inputs and outputs at internal gates (also called nodes) of a circuit Truth Tables Truth tables are an easy way to represent a Boolean function. The idea is to construct a table that for each possible combination of primary inputs values, gives the resulting values of the primary outputs. Truth tables are very easy to construct, but they are very large. There are exponentially many rows as inputs. Given a Boolean function of n inputs, its truth table will have 2 n rows. A simplification is to represent rows that only yield positive results. We will only represent the rows representing combinations of primary input values that result in a positive primary output. Depending on the circuit, this can reduce the truth table quite dramatically. 13

2 14CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE Disjunctive Normal Form An alternative is to use the reduced truth table to represent the Boolean function using the Disjunctive Normal Form (DNF). In DNF, a Boolean function is represented by a disjunction of conjunctions. Note that converting a truth table to DNF has an exponential blow-up. For instance, the DNF representation of a two-input xor-gates is the following: x xor y (x y)+( x y) Very often, the is omitted and negation is denoted using a bar on top of a variable: x xor y xy + xy The DNF representation is canonical and can serve as a normal form. The main drawback is that DNF expressions are exponential in the size of the original expressions. For every xor-gate, the number of literals doubles. Exercise To get a sense of how fast DNF expressions are growing, simply compute the DNF expression of two consecutive xor-gates. That is, compute the DNF representation of the following expression: (x xor y) xor z Sum of Products The Sum of Products (SoP) is a generalisation of the DNF. Instead of using AND and OR as building blocks, one can also choose to have AND and XOR as building blocks. For circuits with many XOR-gates like in arithmetic circuits such a well-chosen SoP can yield compact representations Conjunctive Normal Form Another normal form can be obtained by writing products of sum. This translates a Boolean expression into its Conjunctive Normal Form (CNF), that is, a conjunction of disjunctions. The CNF is the input format of SAT solvers. It is possible to convert an expression in CNF to an expressing in DNF and vice versa. These conversions induce an exponential blow-up of the size of the resulting expression. The general objective is to translate each gate of a circuit into a CNF formula such that the solutions of the formula coincide with the values of the gate wires that make the gate true. Consider an AND gate with wire a and b as inputs and wire c as output. We need to find a CNF encoding that will be compact and faithfully represent the truth values of the AND gate. We will consider the following cases: (1) if any input is 0, then the output must be 0 and (2) if all inputs are 1, the output must be one. Case (1). If input a is false then output c must be false. This expression if a then c is logically equivalent to a _ c, hence a _ c. A similar clause is generated for b: (b _ c). Case (2). If all inputs are true, then the output must be true. This logically means if (a ^ b) then c, which is logically equivalent to (a ^ b) _ c. Hence, ( a _ b _ c).

3 2.1. REPRESENTING BOOLEAN FUNCTIONS 15 Finally, an AND gate with inputs a and b and output c is represented by the following CNF formula: (a _ c) ^ (b _ c) ^ ( a _ b _ c) Consider another example: a XOR gate with inputs a and b and output c. Let s split on whether the output is 1 or 0. Case 1: the output is 1 (that is c is true). This happens when one of the input is 1 and the other 0. We have if a is true and b is false then c is true, which is equivalent to the clause (a _ b _ c). We have a similar clause for the opposite case: ( a _ b _ c). Case 2: the output is 0 (that is c is true). This happens when the two inputs are 1 or the two inputs are 0. We have if a and b are true, then c is false. This is represented by the clause ( a _ b _ c). The clause representing the case when both inputs are false is: (a _ b _ c). Finally, the CNF encoding of a XOR-gate is the following CNF formula: (a _ b _ c) ^ ( a _ b _ c) ^ ( a _ b _ c) ^ (a _ b _ c) When translating an entire circuit, the output of a gate will be used as a helper variable representing the input to the next gates. By doing so, the CNF representation of a circuit is linear and not exponential in the size of the input circuit BDDs Reduced Ordered Binary Decision Diagrams (ROBDDs) provide a canonical representation of Boolean functions. They often are more compact that other canonical representations like Sum-Of-Products for instance. The presentation about BDD is based on Chapter 5 from the textbook by Clarke, Grunberg, and Peled [3] and part of the notes by Henrik Reif Andersen []. Constructing BDDs The fundamental notion underlying this section is Shannon s expansion. For a Boolean function f and a given variable x of f, it states that function f can be decomposed into two sub-functions considering the cases where either x is false or x is true. Formally, we have the following equation: f =( x ^ f x=0 ) _ (x ^ f x=1 ) Another way to look at Shannon s expansion is to consider the if-then-else operator defined as follows: x! y 0,y 1 =(x ^ y 0 ) _ ( x ^ y 1 ) The semantics are that if x holds then y 0, else y 1. So, the expression x! y 0,y 1 is true if either x true and y 0 is true or if x is false and y 1 is true. Let t[0/x] be expression t where x is replaced with 0 and similarly t[1/x] be t where x is 1, then the following equivalence holds: t = x! t[1/x],t[0/x]

4 16CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE Figure 2.1: Binary decision tree for two-bit comparator. This exactly is Shannon s expansion. Using Shannon s decomposition, it is possible to build a binary decision tree. Figure 2.1 shows the tree for a two-bit comparator, that is, for the following Boolean function: f(a 1,a 2,b 1,b 2 )=(a 1 \$ b 1 ) ^ (a 2 \$ b 2 ) A binary tree basically is a rooted, directed tree with terminal and nonterminal vertices. Each nonterminal vertex v is labelled by a variable noted var(v). Such a vertex has two successors: a successor corresponding to the case where the variable is low (false) noted low(v) and a successor corresponding to the case where the variable is high (true) noted high(v). Graphically, we often identify the successor by a 0 or 1 label on the edges. Each terminal vertex v is either 0 or 1. To know the truth value of formula for a given assignment, one traverses the tree down to a leaf by following the low successor if a variable is false or the high successor if a variable is true. As one can see, such a tree is not a very compact representation. Bryant [2] showed how to obtain a compact and canonical representation of Boolean functions by placing two restrictions on binary diagrams. The first restriction imposes an ordering among the variables. This means that variables must always appear in the same order along all paths from the root to terminals. Second, there should be no isomorphic sub-trees or redundant vertices in the diagram. To achieve the first restriction, a total order < is imposed among the variables. We require that if any vertex u has a nonterminal successor v, var(u) < var(v). The second restriction is achieved by recursively applying the following rules: Remove duplicate terminals: Keep only one terminal vertex for each label (0 or

5 2.1. REPRESENTING BOOLEAN FUNCTIONS 17 Figure 2.2: ROBDD for two-bit comparator. 1) and redirect all edges to eliminated vertices to the remaining ones. Remove duplicate nonterminals: If two nonterminals vertices u and v are labelled with the same variables, that is, var(u) =var(v), eliminate one of the vertices and redirect edges to the eliminated vertex to the remaining one. Remove redundant tests: If the two successors of a nonterminal vertex v are equal, that is, low(v) =high(v), remove v and redirect incoming edges of v to low(v). Starting with an ordered diagram, the reduced version is obtained by applying these rules until the size can no longer be reduced. We then obtained a Reduced Ordered Binary Decision Diagram (ROBDD). Bryant [2] showed that this reduction can be done in a bottom-up manner and in time that is linear in the size of the original BDD. Figure 2.2 shows the ROBDD obtained from the decision tree in Figure 2.1. This BDD has only 6 nodes. The variable ordering has a strong impact on the size of the ROBDD. For instance, choosing the ordering a 1 <b 1 <a 2 <b 2 the 2-bit comparator results in the ROBDD shown in Figure 2.3, which is larger than the one shown in Figure 2.2. This larger BDD has 9 nodes. ROBDDs are canonical given a variable ordering. This means that checking equivalence between two ROBDDs reduce to checking equality between two diagrams. Validity reduces to showing equivalence to the trivial diagram composed of one terminal labelled by 0. To further illustrate the construction of BDDs we consider the following Boolean function: f(a, b, c) =a _ (b ^ c) We will use Shannon s expansion to build a Binary Decision Tree for this Boolean

6 18CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE Figure 2.3: ROBDD for two-bit comparator. function. To apply the expansion we need to determine an ordering of the variables. Let us consider the ordering a<b<c. We first decompose according to a, this gives the following equation: f(a, b, c) =( a ^ f(0,b,c)) _ (a ^ f(1,b,c)) The first part of the tree from this equation is pictured in Figure a 1 f(0,b,c) f(1,b,c) Figure 2.4: First part of the binary decision tree. We can recursively proceed with decomposing each sub-formula. For instance, we can expand the subtree f(0,b,c) and obtain: f(0,b,c)=( b ^ f(0, 0,c)) _ (b ^ f(0, 1,c)) A similar expansion is obtained for f(1,b,c). We then insert these terms in the tree and obtain the tree pictured in Figure 2.5. We proceed with the four leaves and then compute the values of f where all literals have been assigned a definite value. We obtain the Binary Decision Tree pictured in Figure 2.6. We apply the rules proposed by Bryant [2] to transform this BDT into a Reduced Ordered BDD. We first apply the rule remove redundant tests 1, this means that we eliminate all nodes where the value at the end of the left and the right branches is the same. There are three cases where this applies. We obtain the graph in Figure The order in which the rules are applied does not matter.

7 2.1. REPRESENTING BOOLEAN FUNCTIONS 19 a b b f(0, 0,c) f(0, 1,c) f(1, 0,c) f(1, 1,c) Figure 2.5: The binary decision tree continued... b b c c c c Figure 2.6: The binary decision tree a 1 The same rule applies once more to the true branch of a. After applying this rule, we apply the rule remove duplicate terminals and obtain the ROBDD in Figure 2.8. The size of a ROBDD depends on the variable ordering. The following question illustrates this point. Exercise For which ordering(s) is the size of the ROBDD for our function f maximal? (Note: The size is counted in the number of nodes and edges)? Finding an optimal ordering is infeasible and there exist functions with no optimal ordering, like bitwise multiplication. In such cases, explicit algorithms might perform better than symbolic ones. Operations on BDDs The main advantage of ROBDDs is that they can be manipulated efficiently. In particular, checking that two ROBDDs are equal requires constant time. Negation is also very easy and simply requires to negate the two leaves 2 of a ROBDD. Other operations are performed using the Apply algorithm proposed by Bryant [2] and that can be used to compute any 2-argument logical operation. The main idea is to use Shannon s decomposition to break problems into sub-problems. 2 Note that any ROBDD has only two leaves, namely, 1 for true and 0 for false.

8 20CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE a b 0 c 1 b 1 Figure 2.7: Reducing the BDT with remove redundant tests. 0 a 0 b 1 c 1 Figure 2.8: Reducing the BDT to a ROBDD. Let? be an arbitrary 2-argument logical operation. Let f and f 0 be two Boolean functions. Let v be the current vertex of f and v 0 be the current vertex of f 0. The algorithm basically is the following case distinction: If v and v 0 are both terminals, f?f 0 = value(v)? value(v 0 ). If var(v) =var(v 0 ), apply Shannon s expansion: f?f 0 = var(v)^(f var(v) 0?f 0 var(v) 0 )_var(v)^(f var(v) 1?f 0 var(v) 1 ) to break the problem into subproblems. The resulting ROBDD will have a new node w with var(w) =var(v), low(w) will be the ROBDD for (f var(v) 0? f 0 var(v) 0 ) and high(w) will be the ROBDD for (f var(v) 1?f 0 var(v) 1 ). If var(v) < var(v 0 ), f 0 var(v) 0 = f 0 var(v) 1 = f 0 since f 0 does not depend on var(v). In this case, the Shannon s expansion reduces to: f?f 0 = var(v) ^ (f var(v) 0?f 0 ) _ var(v) ^ (f var(v) 1?f 0 ) If var(v 0 ) < var(v), similar to previous case.

9 2.1. REPRESENTING BOOLEAN FUNCTIONS 21 By reducing and caching intermediate results, the algorithm is polynomial. The number of sub-problems is bounded by the product of the size of the ROBDDs for f and f 0. We illustrate the Apply algorithm using our small example: f(a) _ f 0 (b, c) where f(a) =a and f 0 (b, c) =b ^ c. We consider the ordering a<b<c. We assume we have the ROBDDs of each function, that is, the graphs pictured in Figure 2.9. a f(a) 0 b 1 c f 0 (b, c) Figure 2.9: ROBDDs for f and f 0. We now use Apply and Shannon s expansion to compute the disjunction of these two ROBDDs. Since the roots of the ROBDDs are not terminal vertices and since the variables in the two roots are not the same we need to determine which of the two variables comes first in the ordering. Since we consider the ordering where a<b, we apply the formula from the third case of the aforementioned algorithm: f(a) _ f 0 (b, c) =( a ^ (f(0) _ f 0 (b, c))) _ (a ^ (f(1) _ f 0 (b, c))) We now start to build a new ROBDD as illustrated in Figure a f(0) _ f 0 (b, c) f(1) _ f 0 (b, c) Figure 2.10: Partial ROBDDs for f _ f 0. Now, we have f(0) = 0 and f(1) = 1 (since f(a) = a). Therefore, the left branch simplifies to f 0 (b, c) and the right branch to 1. We already have a ROBDD for f 0 (b, c). We simply insert it as the left branch. Finally, we obtain the ROBDD pictured in Figure 2.8 for the formula: f(a, b, c) =a _ (b ^ c) The last operation we will need on ROBDDs is existential quantification. Assume a Boolean function f and x a variable of f. Using Shannon s decomposition, we have:

10 22CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE 9x.f = x ^ f x 0 _ x ^ f x 1 That is, f is true if either f is true when x is false, or f is true when x is false. We will come back to existential quantification in Section of Chapter Directed Acyclic Graphs Another way to represent Boolean functions is to use Directed Acyclic Graph. Consider the 2-bit comparator, that is, the following equation: f(a 1,a 2,b 1,b 2 )=(a 1 \$ b 1 ) ^ (a 2 \$ b 2 ) Using the if-then-else operator defined earlier, we can also expand this expression to the following: t = a 1! t 1,t 0 t 0 = a 2! t 01,t 00 t 1 = a 2! t 11,t 10 t 00 = b 1! 0,t 000 t 01 = b 1! 0,t 010 t 10 = b 1! t 101, 0 t 11 = b 1! t 111, 0 t 000 = b 2! 0, 1 t 010 = b 2! 1, 0 t 101 = b 2! 0, 1 t 111 = b 2! 1, 0 We again obtain a tree note that it is already smaller than the one in Figure 2.1 where t is the root and each t i are sub-trees corresponding to the expansion following, in order, variables a 1,a 2,b 1,b 2. Nodes in this tree are equal, as it can be seen in the above expressions. For instance, t 111 = t 010 and t 000 = t 101. By substituting all equal expressions, we obtain a binary decision diagram, that is no longer a tree but a DAG. For instance, in the above example, we obtain: t = a 1! t 1,t 0 t 0 = a 2! t 01,t 00 t 1 = a 2! t 11,t 10 t 00 = b 1! 0,t 000 t 01 = b 1! 0,t 111 t 10 = b 1! t 000, 0

11 2.1. REPRESENTING BOOLEAN FUNCTIONS 23 t 11 = b 1! t 111, 0 t 000 = b 2! 0, 1 t 111 = b 2! 1, 0 Exercise Is it possible to even reduce this DAG using Bryant s rule? Exercise Re-do the construction of the tree and its reduction to a DAG using sharing with the following variable order: a 1,b 1,a 2,b AIGs And Inverter Graphs (AIGs) are directed and acyclic graphs representing Boolean functions. They consist in two input nodes representing conjunction and edges with an optional label indicating negation. The size of an AIG is given by the number of AND nodes in it. The number of logic levels is the number of AND-gates on the longest path from a primary input to a primary output. If you remember your old course 2IC30 on Computer Systems, you should remind yourself about the completeness of the NAND gates. That is, any Boolean function can be represented using two-input NAND gates only. Therefore, AIGs can also represent any Boolean functions. and nand inverter or nor xor Figure 2.11: Basic gates and their representation using And Inverter Graphs Figure 2.11 shows the AIGs representing basic gates. The only slighly more difficult one is the xor gate. One has to express this function using conjunction and negation only. This is given by the following expression: x xor y = (x ^ y) ^ ( x ^ y) Figure 2.12 shows a circuit and its representation as an AIG. The AIG is constructed in a bottom-up manner starting from the Primary Outputs (POs). Note that each time all gates are expressed using and-gates and inverters only using equivalences like the ones shown in Figure When a PI is reached, the construction stops with a leave

12 24CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE a b y c Figure 2.12: A circuit and its representation as an AIG. x1 x2 x3 x4 x5 y x1 x2 x3 x4 y x5 Figure 2.13: A cascade of four xor-gates. node representing this input. Otherwise, the construction proceeds recursively for the fanins of the node. The time needed to construct AIGs and their size is proportional to the size of the input, being a circuit, a SoP expression, or a BDD. A nice feature of AIGs is that they can be smaller than Sum-Of-Products or BDDs. Figure 2.13 shows four cascaded xor-gates and their AIGs. The SoP representation of this function would be exponentially large, whereas the AIG is rather small. Also, there are BDDs that are exponential e.g., multiplier circuits while the size of an AIG always is proportional to the size of the input circuit, SoP, or BDD. The main drawback of AIGs is that they are not canonical, that is, testing for equality is not trivial. AIGs may contain syntactically distinct but functionally equivalent that is redundant nodes. Manipulating such AIGs is also not efficient. To solve this issue, algorithms have been developed introduce some canonicity, in particular, Functionally Reduced AIGs (FRAIGs) [5]. The idea is to reduce AIGs such that they do not exist any pairs of functionally equivalent nodes. FRAIGs are semicanonical in the sense that a Boolean function may have distinct FRAIGs structures. Recent work [5] proposes an algorithm that generates on-the-fly an AIG that is ensured to be functionally reduced.

13 2.2. BOOLEAN SATISFIABILITY (SAT) 25 Figure 2.14: Decisions and the resulting implication graph. 2.2 Boolean satisfiability (SAT) Boolean satisfiability consists in checking whether there exists an assignment of the variables of a Boolean formula that makes this formula true. This problem is wellknown and is very hard (NP-Complete). Still, there are several SAT solvers that can effectively check satisfiability of formulas with thousands of variables. In this section, we briefly recall the basic algorithm behind SAT solvers. Our presentation follows a tutorial given by K. McMillan at CAV The basic SAT algorithm has been proposed by Davis, Putnam, Loveland, and Logeman in the 60 s. Therefore it is called the DPLL algorithm. The objective is to check satisfiability of a CNF formula: literal: p or p clause: disjunction of literals CNF: conjunction of clauses The basic methods consists in three steps: Branch: make some arbitrary decisions in assignment values to variables. Propagate these assignments, that is, computing an implication gap. Use conflicts to guide inferences steps. Implication graph The implication graph is obtained by performing unit propagation (UP) or also called Boolean constraint propagation (BCP). Consider the CNF formula ( a _ b) ^ ( a _ c _ d). The first step always is to make arbitrary decisions, say, assign true to a so a is true and assign false to c so, c is true. The implication graph resulting of

14 26CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE these decisions is shown in Figure From the first clause, namely a _ b, and the assignment a is true, we need to assign true to b to make this clause true, so b holds. From the second clause, namely, a _ c _ d, and the decisions a and c, we also conclude that d must be true to satisfy this second clause. In conclusion, from the arbitrary decision a and c, the implication graph tells us that we have to choose b and d. For this formula, we have found a satisfiable assignment a ^ b ^ c ^ d. So, the formula is SAT. Conflicts and resolution Another step in SAT solving is resolution. Resolution is used to solve conflicts. Consider the following clauses: a _ b _ c a _ b _ d There is here a conflict between a and a that might appear for some decisions, e.g., b ^ c ^ d. From these two clauses, resolution will remove the two occurrences of a and produce the resolved clause b _ c _ d. In SAT, the implication graph is used to guide where resolution must be applied. Consider the following CNF formula: ( a _ b) ^ ( a _ c _ d) ^ ( b _ d) Assume we make the same arbitrary decisions as above, namely, a and c. As explained before, the implication graph obtained by propagating the decisions through the first two clauses will produce the assignment a ^ b ^ c ^ d. This assignment conflicts with the last clause. We can apply resolution between the last two clauses. This creates the clause b _ c. We then apply resolution between this new clause and the first one. This gives us a _ c, that is, the opposite decision as the initial arbitrary one. We can then propagate this decision again. This will make the first two clause true independently of the value of b. This leaves us with free choices for b and d to make the last clause true. We found an assignment making the formula true, so it is SAT. Implementation In practice, many heuristics are implemented to choose variables to start with and which values they should have. Also, heuristics are used to choose how to propagate choices and in selecting clauses for resolution. Also, heuristics are needed to decide when to stop applying resolution. The basic SAT algorithm is given in Figure The current assignment (noted CS) initially is empty. If resolution derives the empty clause, then the problem is UNSAT and the algorithm stops. Otherwise, if a conflict is detected, resolution is used to solve and then to backtrack and change some decisions. If all variables have an assignment, then a satisfiable assignment has been found and the algorithm returns SAT.

15 2.3. COMBINATORIAL EQUIVALENCE CHECKING (CEC) 27 Figure 2.15: Basic SAT algorithm. 2.3 Combinatorial Equivalence Checking (CEC) One of the main application of formal verification techniques is Boolean equivalence checking. The idea is to check whether two Boolean functions are equivalent, that is, for all possible input vectors they produce the same outputs Using SoP, CNF or DNF SoP, CNF, and DNF are all normal forms. To check equality between two circuits, one can simply rewrite a circuit into one of these normal forms. There is an exponential blow-up created by this translation, if done naively. Section presented a translation that using helper variables is linear in the size of the input circuits. In practice, CNF is the input format for SAT solvers and it will work for many cases. CNF is a popular representation for Boolean circuits. When performance are becoming an issue BDD and AIGs are modern alternative (see next sub-sections) Using BDDs ROBDDs are also a normal form. To check the equivalence between two functions, build their ROBDD and check equality of their root pointer. Building ROBDDs is more efficient than SoP. BDDs have been the main tool for equivalence checking for a long time Using AIGs AIGs in contrast to SoP and BDDs do not have canonical representations. Checking for equality seems therefore more difficult. This issue is solved using a SAT solver to determine local equality between AIG nodes. When equal nodes are found, they are

16 28CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE Figure 2.16: Two combinatorial circuits. removed until the remaining AIGs are equal. Because SAT solvers are very efficient, the queries sent to the SAT solver are answered very quickly. Nowadays, AIGs are at the core of modern CEC checkers. The technique proceeds in three steps: 1. Random Simulation: First candidate equivalent nodes are found by simulating the circuits using random test vectors 2. Build AIGs: More equivalent nodes are found by constructing an AIG of the combination of the two circuits. 3. SAT Sweeping: Candidates nodes are used to guide calls to the SAT solver Random simulations Consider the two circuits in Figure 2.16, where a box with A denotes an AND-gate, a box with O an OR-gate, and a small circle an inverter. The first step is to run random simulation to find potential equivalent nodes. Assume a random test vector assigns true to all inputs. These inputs propagate to give the following values to each node: node value 0 true 1 false 2 true 3 true 4 false 5 true 6 true 7 false 8 false

17 2.3. COMBINATORIAL EQUIVALENCE CHECKING (CEC) 29 From this value we can cut the set of nodes in two sets, the sets of node that are true and the set of nodes that are false. We get the following classes: {0, 2, 3, 5, 6}, {1, 4, 7, 8} Assume another random test vector assigns false to all inputs. These inputs propagate and give the following values: node value 0 false 1 true 2 true 3 true 4 false 5 true 6 true 7 false 8 false Node 0 has the value false, while all other nodes in its equivalence class are true (these are nodes 2,3,5,6). We need to remove node 0 from this equivalence class. Node 0 is then a singleton and is therefore not equivalent to any other node. Nodes 1 and 4 are true while nodes 7 and 8 are false. We need to split the equivalence class {1, 4, 7, 8} into two classes. We now have the following equivalence classes: {2, 3, 5, 6}, {1, 4}, {7, 8} Assume a random test vector assigning false to a and b and true to c. This results in the following values: node value 0 false 1 true 2 true 3 false 4 true 5 false 6 true 7 true 8 true Nodes 1 and 4 have the same value. Nodes 7 and 8 also have the same values. This confirms that they seem to be equivalent. Nodes 2 and 6 are true while the other nodes of their equivalence class, namely 3 and 5, are false. We therefore need to split them into two equivalence classes. We obtain: {2, 6}, {3, 5}, {1, 4}, {7, 8} Finally, assume a random test vector assignment true to a and b and false to c. This results in the following values for the nodes:

18 30CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE Figure 2.17: Combining two AIGs into one. node value 0 true 1 false 2 false 3 true 4 true 5 true 6 false 7 true 8 true Nodes 1 and 4 have different values but form an equivalence class. These nodes are split into two classes. Each class is a singleton. So, these nodes are equivalent to no other nodes. This gives us the following equivalence classes. Each class identify a pair of potentially equivalent node. Building AIGs {2, 6}, {3, 5}, {7, 8} The idea is to build the AIG of the two circuits and merge these two AIGs into one. In practice, one can build one AIG and then stepwise add the AIG of the other while the AIG is constructed. Figure 2.17 shows the resulting AIG of combining the two circuits in Figure SAT sweeping From the simulations, we obtained potential equivalent nodes and we now have an AIG representation of the two circuits. The last step is to call a SAT solver to actually check whether the candidate nodes are indeed equivalent. Assume we first ask whether nodes

19 2.4. CONCLUSION 31 Figure 2.18: Combining two AIGs into one. 3 and 5 are equivalent and that the SAT solver proves this. We can then in the AIG remove node 5 and directly connect the open edge of node 7 to node 3 as shown in Figure The same procedure applies to nodes 2 and 6. We can them remove node 6 and make the open edge of node 7 point to node 2. We are left with an AIG where nodes 7 and 8 structurally points to the same nodes, see Figure These two nodes are therefore equivalent. 2.4 Conclusion This chapter presented different ways of representing Boolean functions. When using normal forms, equivalence checking is simple. The issue is that the size of the Boolean representation grows exponentially with the size of the circuits to be compared. AIGs provide a more compact representation but are not canonical. Explicit tests using SAT solvers are needed to identify equivalent nodes. 2.5 Exercises BDDs Exercise Draw the ROBDD for (x 1, y 1 ) ^ (x 2, y 2 ) ^ (x 3, y 3 ) with orderings x 1 <x 2 <x 3 <y 1 <y 2 <y 3 and x 1 <y 1 <x 2 <y 2 <x 3 <y 3. Which ordering would you recommend for constructing a ROBDD for (x 1, y 1 ) ^ (x 2, y 2 ) ^ (x 3, y 3 ) ^... ^ (x k, y k )? Exercise Draw the ROBDD for x 1 ^ (x 2, x 3 ) with ordering x 1 <x 2 <x 3. Exercise Construct the ROBDD for x 1 and x 1 ) x 2 using whatever ordering you want. Use the APPLY procedure to build the ROBDD for their disjunction.

20 32CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE Figure 2.19: Combining two AIGs into one. Exercise Construct the ROBDD for (x 1 ^ x 3 ) and (x 2 ^ x 3 ) with the ordering x 1 <x 2 <x 3. Use APPLY to construct the ROBDD for (x 1 ^ x 3 ) _ (x 2 ^ x 3 ) AIGs Figure 2.20: A circuit. Exercise Build an AIG for the circuit in Figure Exercise Draw an AIG representing each one of the circuits in Figure Then, build the combined AIG for the two circuits. These circuits are equivalent. Is the combined AIG functionally reduced? Would techniques like SAT Sweeping be effective here? What query would you submit to a SAT solver?

21 2.5. EXERCISES 33 Figure 2.21: Two circuits CNF encoding Exercise Write the CNF encoding for the following gates: NAND, OR,NOR, XNOR, and NOT.

22 34CHAPTER 2. BOOLEAN REPRESENTATIONS AND COMBINATORIAL EQUIVALENCE

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