Exclusive OR/Exclusive NOR (XOR/XNOR)


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1 Exclusive OR/Exclusive NOR (XOR/XNOR) XOR and XNOR are useful logic functions. Both have two or more inputs. The truth table for two inputs is shown at right. a XOR b = 1 if and only if (iff) a b. a XNOR b = 1 if and only if (iff) a = b. Both may also have many inputs. For >2 inputs, the XOR output is 1 for an odd number of 1 inputs; XNOR has a 1 output for an even number of 1 inputs. Symbols are shown below and to the right. a b XOR a b Like NAND and NOR, XOR and XNOR are not a basic Boolean functions, XNOR a b but can be made from b AND, OR and NOT. 1 Lecture #6: More Complex Combinational Logic Circuits XOR/XNOR Truth Table a b a XOR b a XNOR b XNOR = ab + ab XOR = ab + ab
2 Quick Simplification Review The first technique we studied to simplify a Boolean expression used algebraic techniques. For instance, consider the truth table at right. The minterms shown represent the SOP expression: f = abc + abc + abc The Boolean expression is easily simplifiable using the Boolean identities: f = abc + abc + abc f = abc + abc + abc + abc 1 1 f = ab( c + c) + ac( b + b) f = ab + ac The simplified circuit is shown below the truth table. a b c f Lecture #6: More Complex Combinational Logic Circuits
3 Quick Simplification Review (2) We can also plot the minterms on a Kmap and graphically simplify the expression (and the circuit). On the Kmap below, the three minterms ( abc, abc, abc) are plotted. The simplified expression derived from the two prime implicants is the same as that using algebraic simplification. a a bc bc bc bc Identical circuit solution using Kmap method: f = ab + ac a b c f Lecture #6: More Complex Combinational Logic Circuits
4 4 Lecture #6: More Complex Combinational Logic Circuits Exercise 1 Let s do another simplification exercise before moving on. Consider this spec: The function f of three variables, x, y, and z, is 1 when x and y are both 1 or when x and z are both 1. Find the SOP expression, the simplified expression, and the simplified circuit. Use the Kmap on the next slide to perform the same simplification. x y z f
5 x x yz KMap Solution yz yz yz 5 Lecture #6: More Complex Combinational Logic Circuits
6 Decoders An nto2 n decoder is a combinational logic circuit that has n inputs and up to 2 n outputs. That is, it can have 2 n outputs, but it may have less. Each output of a decoder will normally be true (i.e., go to logic 1) for only one combination of the n inputs. Consider the case of an n = 2 decoder. The decoder will have 2 inputs and up to 2 n = 2 2 = 4 outputs. Assume that the decoder has the maximum possible number of outputs (4). Then the truth table for the 2input decoder will show that for each combination of y and x (00, 01, 10, 11), one of the outputs will go high (logic 1). Let us call the inputs y and x and the outputs a, b, c, and d (here, x is the more significant bit). Then let us define a = 1 for x = 0, y = 0; b = 1 for x = 0 and y = 1; c = 1 for x = 1 and y = 0, and d = 1 for x = 1 and y = 1. 6 Lecture #6: More Complex Combinational Logic Circuits
7 Decoders (2) The truth tables for ad in our 2to4 decoder are: x y * a b c d Using the truth tables above, we can define ad in terms of x and y. a= xy b c d = xy = xy = xy Boolean expressions for a, b, c, and d in terms of x and y. * Note that we put x first because we regard the xy pair as a number, with x the more significant bit. 7 Lecture #6: More Complex Combinational Logic Circuits
8 Decoders (3) Remembering that a = x y, b = xy, c = x y, and = xy : If we consider xy a binary number with x the MSB and y the LSB, then ad represent a x true condition for each of the four possible y binary numbers that x and y can represent. Thus we say that each output ad has an address, which is a unique combination of the two bits in the binary number yx: For xy = 00, a = 1; for xy = 01, b = 1; for xy = 10, c = 1; for xy = 11, d = 1. a b c d Based on the logic expressions above, we can draw the decoder circuit as shown at right. 8 Lecture #6: More Complex Combinational Logic Circuits
9 Decoders (4) In the same way, a decoder with 3 inputs may have up to 2 3 = 8 outputs, and each output will have a unique address that represents one of the eight possible combinations of the three inputs. Such a circuit is shown to the right. In the same way, a 4input decoder could have up to 2 4 = 16 outputs, each of which is a unique combination of the inputs. Etc., for 5, 6, 7 Two Notes: Any ninput decoder can have up to 2 n outputs, but it may have less. In general, each output for an ninput decoder is created by a single ninput AND gate. Its inputs are the n decoder inputs, some of which may be inverted. 9 Lecture #6: More Complex Combinational Logic Circuits x y z 3input, eightoutput decoder x y z g a b c d e f g h
10 Definition of a Multiplexer A multiplexer is a combinational logic circuit that has up to 2 n inputs, an nbit address, and one output. The multiplexer connects one of the inputs to the output, depending on the value of the nbit address. The nbit address is decoded, just as we have studied in the last five slides. Thus the multiplexer uses a decoder and a selector circuit (which we will see in a subsequent slide) to tie one of its inputs to its output. The multiplexer is usually symbolized by the abbreviation MUX as the symbol for its function. 10 Lecture #6: More Complex Combinational Logic Circuits
11 Multiplexer: An Input to Output Selector The truth table for a multiplexer is shown below. Assume a 4input MUX, with inputs labeled a, b, c, d. Then there must be two address lines, x (MSB) and y (LSB). The output is denoted as f. x y f 0 0 a 0 1 b 1 0 c 1 1 d 11 Lecture #6: More Complex Combinational Logic Circuits
12 Components of a Multiplexer a b c f d Output* x y Selector * Note that the multiplexer has a 1bit output. Decoder The multiplexer is shown above, with the various parts of the circuit labeled. 12 Lecture #6: More Complex Combinational Logic Circuits
13 Differences in Decoder and Multiplexer Decoder: A decoder has n inputs, which are called the address. A decoder has up to 2 n outputs (it can have that many, maximum; but it might have less). Each output line is true (or 1) for a specific combinations of the input lines, called the address. Multiplexer: A multiplexer has two sets of inputs: n address lines (just like the decoder) and as many as 2 n inputs, one of which is selected by each address for output (it may have less inputs). A multiplexer has only one output. The output is the value of the input selected by the address. Thus we see that a decoder makes up a part of a multiplexer. 13 Lecture #6: More Complex Combinational Logic Circuits
14 Let s design a simple decoder and multiplexer. A decoder has a threeinput address, xz, with x = MSB, but although it may have up to 2 3, or 8 outputs, in this case, it has only three. Output 1 is true on address 3, 2 on address 6, and 3 on address 7. Design the decoder. Now using the decoder and adding a selector circuit, design a MUX to output the inputs ac on addresses 3, 6, and 7, respectively. Exercise 2 14 Lecture #6: More Complex Combinational Logic Circuits
15 Binary Arithmetic Circuits A binary adder is a large part of a computer central processor unit (CPU). The CPU figuring unit is sometimes called the ALU, or arithmetic/logic unit, (Patterson and Hennessey call it the datapath ). The ALU or datapath is a combinational logic unit that can add, subtract, or do logical operations such as AND, OR, NOT, etc. Consider the rules of addition (adding two numbers only*): Numbers are added on a columnar basis, starting on the right. If the sum of one column is a 2digit number, the right number goes in current column, and the left number (always a 1) becomes a carry to the next column to the left. Column addition always includes the carry from the column to the right. The resulting sum in any column will be only a single digit. * A computer never adds but two numbers together at one time. 15 Lecture #6: More Complex Combinational Logic Circuits
16 Principles of Addition Decimal addition example: Carries Binary numbers are added in exactly the same way: Carries Lecture #6: More Complex Combinational Logic Circuits (1) Basic principles for an ncolumn addition: Add column i plus carry from column i 1 (c i 1 ). If a onedigit result, that number is the sum of column i, s i. If a 2digit result, the right digit is s i. The left digit is carry i, or c i. The column i carry, c i, will be added to column (i+1).
17 A HalfAdder Circuit We would now like to design a digital adder for two binary numbers. Since addition is done on a columnar basis, all that is necessary to add two n bit numbers, is to use one binary column adder for each of the n bits. Thus, to add two 8bit numbers, we simply use eight column adders. First we consider a 2bit halfadder. The truth table on the right shows sum and carry bits for the 2 input bits a & b. Thus, sum is the simple SOP expression: S = ab + ab. Likewise, carry out is defined as: Co = ab The SOP representation of the 2bit half adder is at the right. a b S c o S Exp c o Exp a b ab ab HalfAdder Circuit ab S C o 17 Lecture #6: More Complex Combinational Logic Circuits
18 Alternate Construction of a HalfAdder We note that in a halfadder, the sum s is expressed as: s = ab + ab As noted on the first slide today, this is the expression for the XOR gate. Thus an alternate expression for s is: s= a b Note that carry out is still: Co = ab. We can then construct the logic gate equivalent of the halfadder as shown on the right. Note that this is no longer a standard SOP representation, but it is easier to build! 18 Lecture #6: More Complex Combinational Logic Circuits
19 HalfAdder in Action = 0, =1 19 Lecture #6: More Complex Combinational Logic Circuits
20 The Full Adder The halfadder circuit is an important step in building a digital adder, but it is not the total solution to the binary addition problem. When adding binary numbers on a columnar basis, in addition to the column bits, a i and b i, there is also the possibility of a carry bit, c i1 from the column to the right. Thus the 2bit column adder must be a 3bit adder. This 3bit adder is called a full adder. In adding two nbit binary numbers, the rightmost bits of the two numbers of two numbers could be added with a halfadder (no carry in). However, most adder circuits use all fulladders, since carryin for the least significant bit can be useful; we will see that use later in this lecture. Col (i+1) Col (i) Col (i 1) (c i ) + a i+1 + b i+1 s i+1 (c i 1 ) + a i + b i s i (c i 2 ) + a i 1 + b i 1 s i 1 Columnar Addition 20 Lecture #6: More Complex Combinational Logic Circuits
21 21 Lecture #6: More Complex Combinational Logic Circuits Full Adder Boolean Equations The full column adder truth table is shown, along with SOP terms for the 1 s in the S and c o columns. For the sum SOP function:* S = abc + abc + abc + abc For the carry out SOP function: Co = abc + abc + abc + abc The SOP circuit for the full adder is shown on the next slide. a b c i S c o S Exp c o Exp abc * abc abc abc abc abc abc abc * For simplicity, we represent carry in above simply as c.
22 SOP Circuit for a Full Adder Above is the SOP equivalent circuit for a full adder. Note that sum and carry have a common term. 22 Lecture #6: More Complex Combinational Logic Circuits
23 Alternate Construction of Full Adder We note that since we can construct a fulladder similarly to a halfadder, then we should be able to use the alternate halfadder (XOR logic) to construct a full adder. That is, for the full adder, S = ( a b) c Co = ab + ( a b) c Where c = c in The equivalent logic construction is shown in the circuit on the right. The exact proof is left to the student. Although this is an easier circuit to build (XOR s simplify the circuit), it is NOT in correct SOP or POS form. 23 Lecture #6: More Complex Combinational Logic Circuits
24 32Bit Adder 1digit (2bit) full adder 32digit (2bit) adder May be a halfadder A 32bit adder would be made up like this: The 32 1digit full adders would be wired up so that each would add one column of two 32bit numbers (a halfadder could be used in column 1). 24 Lecture #6: More Complex Combinational Logic Circuits
25 Subtraction In the past, digital subtractors were constructed as well as digital adders. However, it quickly became apparent that the subtraction function could be added very easily to a digital adder. Consider the following: A 1bit full adder produces carry out (c O ) and sum (s) outputs from carry in (c i ) and numerical (a and b) inputs. We note that ( a b) = a+ ( b, so that we can 2's complement ) = a+ b+ 1 subtract using an adder if we: Invert b (can obtain via an XOR). Set the carry in input (c i ) of bit 0 to 1 (which is why we would need a full adder even in column 1 of the binary adder circuit). To select subtraction, we need two control signals: Invert b which selects b instead of b. Carry in, column 1 which sets c i = 1 for bit 0. We can combine these into one control signal, Add /Sub+ 25 Lecture #6: More Complex Combinational Logic Circuits
26 If the Add /Sub+ input is high, the XOR s invert the B input, while if it is low, the B input is not changed. Inputs Add/Subtract Selector 26 Lecture #6: More Complex Combinational Logic Circuits FourBit Binary Add/Subtract Circuit Carry in = 1 for subtract. A0 A1 A2 A3 B0 B1 B2 B3 Add/Sub+ A B A B A B A B Ci Ci Ci Ci C0 C1 C2 1Bit Full Adder (Used 4 Times) S0 S1 S2 S3 C3 Outputs Note that the Add /Sub+ line must be XOR ed with the C3 line to be correct for the subtract case. 4Bit Adder Section
27 The ALU or Datapath We have already noted that the arithmetic/logical unit (ALU, or what P&H call the datapath ) is the calculating unit of the computer central processor. The amazing thing about the ALU is that it is mostly combinational logic composed of the very logic functions that we have studied so far! Patterson & Hennessy discuss a simple version ALU in Chapter 4 of their book that only functions as an AND/OR/add/subtract/compare unit. This ALU takes the columnar approach we have discussed for a binary adder. Their 32bit ALU (the prototype for the MIPS R2000 computer we will learn to program later on) is composed of 32 of the 1bit ALUs. 27 Lecture #6: More Complex Combinational Logic Circuits
28 A 1Bit ALU 2Bit MUX Select Address a OR b Carry In 1bit Full Adder/ Subtractor AND Sum Carry/ Borrow 4to1 MUX 1Bit Result Out The 1bit ALU provides all the possible results of logic/arithmetical analysis to the 41 MUX. The 2bit select address (derived from decoding a part of the computer instruction) selects the desired result and outputs it. For instance, outputting the borrow signal provides a comparison of a and b. 28 Lecture #6: More Complex Combinational Logic Circuits
29 Bit Slicing: N 1bit ALU s = NBit Processor Thirtytwo of the onebit ALU s shown on the previous page may be combined to form a 32bit MIPS CPU (which we will study later). In the 32bit ALU, an operation is performed on all bits at once using the 32 separate 1bit ALU s. This slices the data into 32 bits, which is where the name bit slicing comes from. This approach works well for AND and OR functions. For add and subtract, we have to propagate carries from each lower column to the next higher column. This means that in a 32bit computer, we have 32 carries (the 32 nd carry would be overflow ). All these carries/borrows are VERY timeconsuming, and so some special digital fast carry circuits have been developed to accelerate the carry/borrow action (they are not shown on the 1bit ALU diagram). These accelerators are not covered in EE Lecture #6: More Complex Combinational Logic Circuits
30 Exercise 3 As a special exercise in reviewing the digital adder plus some of the principles we learned earlier, consider the following: The SOP Boolean expression for a full adder carry out is: C = abc + abc + abc + abc, where c = c o This expression can be simplified to three terms. Do so. Then show the circuit design. i 30 Lecture #6: More Complex Combinational Logic Circuits
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