Calculating the Logical Effort of Gates

Transcription

1 Chpter 4 Clulting the Logil Effort of Gtes The simpliity of the theory of logil effort follows from ssigning to eh kind of logi gte numer its logil effort tht desries its drive pility reltive to tht of referene inverter. The logil effort is independent of the tul size of the logi gte, llowing one to postpone detiled lultions of trnsistor sizes until fter the logil effort nlysis is omplete. Eh logi gte is hrterized y two quntities: its logil effort nd its prsiti dely. These prmeters my e determined in three wys: Using few proess prmeters, one n estimte logil effort nd prsiti dely s desried in this hpter. The results re suffiiently urte for most design work. Using test iruit simultions, the logil effort nd prsiti dely n e simulted for vrious logi gtes. This tehnique is eplined in Chpter 5. Using frited test strutures, logil effort nd prsiti dely n e physilly mesured. Before turning to methods of lulting logil effort, we present disussion of different definitions nd interprettions of logil effort. While these re ll equivlent, in some sense, eh offers different perspetive to the design tsk nd eh leds to different intuitions. 0 Copyright 1998, Morgn Kufmnn Pulishers, In. This mteril my not e opied or distriuted without permission of the pulisher. 59

2 60 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES 4.1 Definitions of logil effort Logil effort ptures enough informtion out logi gte s topology the network of trnsistors tht onnet the gte s output to the power supply nd to ground to determine the dely of the logi gte. In this setion, we give three equivlent onrete definitions of logil effort. Definition 4.1 The logil effort of logi gte is defined s the numer of times worse it is t delivering output urrent thn would e n inverter with identil input pitne. Any topology required to perform logi mkes logi gte less le to deliver output urrent thn n inverter with identil input pitne. For one thing, logi gte must hve more trnsistors thn n inverter, nd so to mintin equl input pitne, its trnsistors must e nrrower on verge nd thus less le to ondut urrent thn those of n inverter with identil input pitne. If its topology requires trnsistors in prllel, onservtive estimte of its performne will ssume tht not ll of them ondut t one, nd therefore tht they will not deliver s muh urrent s ould n inverter with identil input pitne. If its topology requires trnsistors in series, it nnot possily deliver s muh urrent s ould n inverter with identil input pitne. Whtever the topology of simple logi gte, its ility to deliver output urrent must e worse thn n inverter with identil input pitne. Logil effort is mesure of how muh worse. Definition 4. The logil effort of logi gte is defined s the rtio of its input pitne to tht of n inverter tht delivers equl output urrent. This lterntive definition is useful for omputing the logil effort of prtiulr topology. To ompute the logil effort of logi gte, pik trnsistor sizes for it tht mke it s good t delivering output urrent s stndrd inverter, nd then tlly up the input pitne of eh input signl. The rtio of this input pitne to tht of the stndrd inverter is the logil effort of tht input to the logi gte. The logil effort of logi gte will depend slightly on the moilitiy rtio in the frition proess used to uild it. These lultions re shown in detil lter in this hpter. Definition 4. The logil effort of logi gte is defined s the slope of the gte s dely vs. fnout urve divided y the slope of n inverter s dely vs. fnout urve.

3 4.. GROUPING INPUT SIGNALS 61 This lterntive definition suggests n esy wy to mesure the logil effort of ny prtiulr logi gte y eperiements with rel or simulted iruits of vrious fnouts. 4. Grouping input signls Beuse logil effort reltes the input pitne to the output drive urrent ville, nturl question rises: for logi gte with multiple inputs, how mny of the input signls should we onsider when omputing logil effort? It is useful to define severl kinds of logil effort, depending on how input signls re grouped. In eh se, we define n input group to ontin the input signls tht re relevnt to the omputtion of logil effort: Logil effort per input, in whih logil effort mesures the effetiveness of single input in ontrolling output urrent. The input group is the single input in question. All of the disussion in preeding hpters uses logil effort per input. Logil effort of undle, group of relted inputs. For emple, multipleer requires true nd omplement selet signls; this pir might e grouped into undle. Beuse undles of omplementry pirs of signls our frequently in CMOS iruits, we dopt speil nottion: s stnds for undle ontining the true signl s nd the omplement signl s. The input group of undle ontins ll the signls in the undle. Totl logil effort, the logil effort of ll inputs tken together. The input group ontins ll the input signls of the logi gte. Terminology nd ontet determine whih kind of logil effort pplies. The djetive totl is lwys used when totl logil effort is ment, while the other two ses re distinguished y the signls ssoited with them in ontet. The totl logil effort of -input NAND gte is the logil effort of oth inputs tken together, while the logil effort of -input NAND gte is the logil effort per input of one of its two inputs. The logil effort of n input group is defined nlogously to the logil effort per input, shown in the previous setion. The nlog of Definition 4. is: the logil effort g of n input group is just g C P C i = = (4.1) C inv C inv

4 6 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES where C is the omined input pitne of every signl in the input group, nd C inv is the input pitne of n inverter designed to hve the sme drive pilities s the logi gte whose logil effort we re lulting. A onsequene of Eqution 4.1 is tht the logil efforts ssoited with input groups sum in strightforwrd wy. The totl logil effort is the sum of the logil effort per input of every input to the logi gte. The logil effort of undle is the sum of the logil effort per input of every signl in the undle. Thus logi gte n e viewed s hving ertin totl logil effort tht n e lloted to its inputs ording to their ontriution to the gte s input pitne. 4. Clulting logil effort Definition 4. provides onvenient method for lulting the logil effort of logi gte. We hve ut to design gte tht hs the sme urrent drive hrteristis s referene inverter, lulte the input pitnes of eh signl, nd pply Eqution 4.1 to otin the logil effort. Beuse we ompute the logil effort s rtio of pitnes, the units we use to mesure pitne my e ritrry. This oservtion simplifies the lultions enormously. First, ssume tht ll trnsistors re of minimum length, so tht trnsistor s size is ompletely ptured y its width, w. The pitne of the trnsistor s gte is proportionl to w nd its ility to produe output urrent, or ondutne, is lso proportionl to w. In most CMOS proesses, pullup trnsistors must e wider thn pulldown trnsistors to hve the sme ondutne. = n = p is the rtio of PMOS to NMOS width in n inverter for equl ondutne. is the tul rtio of PMOS to NMOS width in n inverter. For simpliity, we will often ssume tht = =. Under this ssumption, n inverter will hve pulldown trnsistor of width w nd pullup trnsistor of width w, s shown in Figure 4.1, so the totl input pitne n e sid to e w. Inthis hpter, we will lso find generl epressions for logil effort s funtion of. In Chpter 9, we will onsider the enefits of hoosing 6=. Let us now design -input NAND gte so tht it hs the sme drive hrteristis s n inverter with pulldown of width 1 nd pullup of width. Figure 4.1 shows suh NAND gte. Beuse the two pulldown trnsistors of the NAND gte re in series, eh must hve twie the ondutne of the inverter pulldown trnsistor so tht the series onnetion hs ondutne equl to tht of the inverter pulldown trnsistor. Therefore, these trnsistors re twie s wide s the inverter pulldown trnsistor. This resoning ssumes tht trnsistors in series

5 4.. CALCULATING LOGICAL EFFORT () () () Figure 4.1: Simple gtes. () The referene inverter. () A two-input NAND gte. () A two-input NOR gte. oey Ohm s lw for resistors in series. By ontrst, eh of the two pullup trnsistors in prllel need e only s lrge s the inverter pullup trnsistor to hieve the sme drive s the referene inverter. Here we ssume tht if either input to the NAND gte is LOW, the output must e pulled HIGH, nd so the output drive of the NAND gte must mth tht of the inverter even if only one of the two pullups is onduting. We find the logil effort of the NAND gte in Figure 4.1 y etrting pitnes from the iruit shemti. The input pitne of one input signl is the sum of the width of the pulldown trnsistor nd the pullup trnsistor, or + = 4. The input pitne of the inverter with identil output drive is C inv = 1+ =. Aording to Eqution 4.1, the logil effort per input of the -input NAND gte is therefore g = 4=. Oserve tht oth inputs of the NAND gte hve identil logil efforts. Chpter 8 onsiders symmetri gte designs fvoring the logil effort of one input t the epense of nother. We designed the NOR gte in Figure 4.1 in similr wy. To otin the sme pulldown drive s the inverter, pulldown trnsistors one unit wide suffie. To otin the sme pullup drive, trnsistors four units wide re required, sine two of them in series must e equivlent to one trnsistor two units wide in the inverter. Summing the input pitne on one input, we find tht the NOR gte hs logil effort, g = 5=. This is lrger thn the logil effort of the NAND gte euse pullup trnsistors re less effetive t generting output urrent thn pulldown trnsistors. Were the two types of trnsistors similr, i.e., = 1, oth

6 64 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES Figure 4.: Simple gtes with 60 input pitne of 60 unit-sized trnsistors. NAND nd NOR gtes would oth hve logil effort of 1.5. All of the sizing lultions in this monogrph ompute the input pitne of gtes. This pitne is distriuted mong the trnsistors in the gte in the sme proportions s re used when omputing logil effort. For emple, Figure 4. shows n inverter, NAND, nd NOR gte, eh with input pitne equl to 60 unit-sized trnsistors. When designing logi gtes to produe the sme output drive s the referene inverter, we re modeling CMOS trnsistors s pure resistors. If the trnsistor is off, the resistor hs no ondutne; if the trnsistor is on, it hs ondutne proportionl to its width. To determine the ondutne of trnsistor network, the ondutnes of the trnsistors re omined using the stndrd rules for lulting the ondutne of resistor network ontining series nd prllel resistor onnetions. While this model is only pproimte, it hrterizes logi gte performne well enough to design fst strutures. More urte vlues for logil effort n e otined y simulting or mesuring test iruits, s disussed in Chpter 5. An importnt limittion of the model is tht it does not ount for veloity sturtion. The veloity of rriers, nd hene the urrent of trnsistor, normlly sles linerly with the eletri field ross the hnnel. When the field rehes ritil vlue, rrier veloity egins to sturte nd no longer inreses with field strength. The field ross single trnsistor is proportionl to V DD =L. In su-miron proesses, V DD is usully sled with L so tht n NMOS trnsistor in n inverter is on the orderline of veloity sturtion. PMOS trnsistors hve lower moility nd thus re less prone to veloity sturtion. Also, series NMOS trnsistors hve lower field ross eh trnsistor nd therefore re less veloity

7 4.4. ASYMMETRIC LOGIC GATES 65 sturted. The effet of veloity sturtion to rememer is tht series stks of NMOS trnsistors in su-miron proesses tend to hve less resistne thn suggested y the model. Thus, strutures with series NMOS trnsistors hve slightly lower logil effort thn our model predits. 4.4 Asymmetri logi gtes Unlike the NAND nd NOR gtes, not ll logi gtes indue the sme logil effort per input for ll inputs. Equl logil effort per input is onsequene of the symmetries of the logi gtes we hve studied thus fr. In this setion, we will nlyze n emple in whih the logil effort differs for different inputs. Figure 4. shows one form of nd-or-invert gte with n symmetri onfigurtion. The trnsistor widths in this gte hve een hosen so tht the output drive mthes the referene inverter in Figure 4.1: the pulldown struture is equivlent to single pulldown trnsistor of width 1 nd the pullup struture is equivlent to single pullup trnsistor of width. The totl logil effort of the gte, omputed using Eqution 4.1, is 17=. The logil effort of the distint inputs of the nd-or-invert gte n e lulted individully. The logil effort per input for inputs nd is 6= =.The logil effort of the symmetri input,, is5=. The input hs slightly lower logil effort thn the other inputs, refleting the ft tht the input presents less pitive lod thn the other inputs. Input is esier to drive thn the other two inputs. Asymmetries in the logil effort of inputs rise in severl different wys. The nd-or-invert gte is topologilly symmetri, giving rise to unequl logil efforts of its inputs. Topologilly symmetri gtes, suh s NAND nd NOR, n e uilt with unequl trnsistor sizes to mke them symmetri so s to redue the logil effort on some inputs, nd thus redue the logil effort long ritil pths in network. Other gtes, suh s XOR, hve oth symmetri nd symmetri forms, s disussed in Setion These tehniques re eplored further in Chpter Ctlog of logi gtes The tehniques for lulting logil effort re used in this setion to develop Tle 4.1. The epressions re slightly more generl thn those ehiited in erlier

8 66 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES Figure 4.: An symmetri nd-or-invert gte.

9 4.5. CATALOG OF LOGIC GATES 67 Gte type Logil Formul n = n = n =4 effort = = = n(n+) NAND totl 1+ 8/ 5 8 (n+) per input 1+ 4/ 5/ n(1+n) NOR totl 10/ n per input 5/ 7/ 1+ multipleer totl 4n d, s,,,, XOR, XNOR, prity totl n n (symmetri) per undle n n XOR, XNOR, prity totl (symmetri) per undle 4,4 6,1,6 8,16,16,8 mjority totl 1 (symmetri) per input 4 mjority totl 10 (symmetri) per input 4,4, C-element totl n per input n 4 lth totl 4 (dynmi) d,, n upper ounds totl n / 48 51/ 1+ n per undle 16/ 16 18/ 1+ Tle 4.1: Summry of lultions of the logil effort of logi gtes. setions in two wys. First, the epressions pply to logi gtes with n ritrry numer of inputs, n. Seond, they use prmeter for the rtio of p-type to n-type trnsistor widths, so s to permit lultion of logil effort for gtes frited with vrious CMOS proesses. Wheres the referene inverter in Figure 4.1 hs pullup-to-pulldown width rtio of : 1, rtio of : 1 is used throughout this setion. Eh logi gte will e designed to hve pulldown drive equivlent to n n-type trnsistor of width 1 nd pullup drive equivlent to p-type trnsistor of width.

10 68 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES NAND gte A NAND gte with n inputs, designed to hve the sme output drive s the referene inverter, will hve series onnetion of pulldown trnsistors, eh of width n, nd prllel onnetion of pullup trnsistors, eh of width. Using Eqution 4.1, the totl logil effort is: g tot = n(n + ) 1+ (4.) The logil effort per input is just 1=n of this vlue, euse the input pitne is eqully distriuted mong the n inputs. Tle 4.1 inludes the epressions for logil effort nd lultions for severl ommon ses: =, n =;;4. Note from the eqution tht the logil effort hnges only slightly for wide rnge of : when rnges from 1 to, the totl logil effort for n =rnges from to NOR gte The n-input NOR gte onsists of prllel onnetion of pulldown trnsistors, eh of width 1, nd series onnetion of pullup trnsistors, eh of width n. The totl logil effort is therefore: g tot = n(1 + n) 1+ (4.) Agin, the logil effort per input is just 1=n times this vlue. Tle 4.1 inludes emples of the logil effort of NOR gte. For CMOS proesses in whih >1, the logil effort of NOR gte is greter thn tht of NAND gte. If the CMOS frition proess were perfetly symmetri, so tht we ould hoose =1,then the logil effort of NAND nd NOR gtes would e equl Multipleers, tri-stte inverters An n-wy inverting multipleer is shown shemtilly in Figure 4.4. There re n dt inputs, d 1 :::d n,ndn undles of omplementry selet signls, s 1 :::s n. Eh dt inputis wired to four-trnsistorselet rm, whih is in turn onneted to the output. To selet input i, only undle s i is driven TRUE, whih enles urrent to flow through the pullup or pulldown strutures in the selet rm ssoited with d i.

11 4.5. CATALOG OF LOGIC GATES 69 s 1 s sn s 1 s sn d 1 d dn Figure 4.4: An n-wy multipleer. Eh rm of the multipleer hs dt input d i nd selet undle s i. The totl logil effort of multipleer is n(4+4)=(1 + ) = 4n. The logil effort per dt input is just (+)=(1 + ) =, nd the logil effort per selet undle is lso. Note tht the logil effort per input of multipleer does not depend on the numer of inputs. Although this property suggests tht lrge, fst, multipleers ould e uilt, stry pitne in lrge multipleers limits their growth. This prolem is nlyzed fully in Chpter 11. Also, inresing the numer of multipleer inputs tends to inrese the logil effort of the selet genertion logi. A single multipleer rm is sometimes lled tri-stte inverter. Whenmultipleer is distriuted ross us, the individul rms re often drwn seprtely s tri-stte inverters. Note tht the logil efforts of the s nd s inputs my differ XOR, XNOR, nd prity gtes Figure 4.5 shows n XOR gte with two inputs, nd, nd output. The gte hs two undled inputs; the undle ontins omplementry pir nd,nd the undle ontins nd. The totl logil effort of the gte is (8+8)=(1 + ) =8. The logil effort per input is just 1=4 this mount, or. The logil effort per input undle is just the sum of the logil effort per input of the two inputs in the undle, or 4. The struture shown in Figure 4.5 n e generlized to ompute the prity of n inputs. As n emple, Figure 4.6 shows -input XOR gte. The n-input gte

12 70 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES Figure 4.5: A two-input XOR gte, with input undles nd, nd output. will hve n 1 pulldown hins, eh with n trnsistors in series, eh of width n. There will e n 1 pullup hins, eh with n trnsistors in series, eh of width n. Thus the totl logil effort will e n 1 n(n + n)=(1 + ) = n n 1.The logil effort per input will e 1=(n) times this figure, or n n, nd the logil effort per input undle will e 1=n times the totl logil effort, or n n 1. For n = nd ove, symmetri strutures suh s the one shown in Figure 4.6 fil to yield lest logil effort. Figure 4.6 shows wy to shre some of the trnsistors in seprte pullup nd pulldown hins to redue the logil effort. Repeting the lultion, we see tht the totl logil effort is 4, whih is sustntil redution from 6, the totl logil effort of the symmetri struture in Figure 4.6. In the symmetri version, undles nd hve logil effort per undle of 6. Bundle hs logil effort of 1, whih is the sme s in the symmetri version euse no trnsistors onneted to or re shred in the symmetri gte. The XOR nd prity gtes n e ltered slightly to produe n inverted output: simply interhnge the nd onnetions. Note tht this trnsformtion does not hnge ny of the logil effort lultions Mjority gte Figure 4.7 shows two designs for n inverting -input mjority gte. Its output is LOW when two or more of its inputs re HIGH. The symmetri design is shown in Figure 4.7. The totl logil effort is (1 + 1)=(1 + ) = 1, distriuted evenly mong the inputs. The logil effort per input is therefore 4. Figure 4.7

13 4.5. CATALOG OF LOGIC GATES 71 () () Figure 4.6: Two designs for three-input prity gtes. () A symmetri design. () An symmetri design with redued logil effort.

14 7 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES shows n symmetri design, whih shres trnsistors s does the XOR design in Figure 4.6. The totl logil effort of this design is 10, nd it is unevenly distriuted mong the inputs. The input hs logil effort of, while the nd inputs hve logil efforts of 4 eh Adder rry hin Figure 4.8 shows one stge of ripple-rry hin in n dder. The stge epts rry C in nd delivers rry out in inverted form on C out. The inputs g nd k ome from the two its to e summed t this stge. The signl g is HIGH if this stge genertes new rry, foring C out = 0. Similrly, k is LOW if this stge kills inomming rries, foring C out =1. The totl logil effort of this gte is (5 + 5)=(1 + ) =5. The logil effort per input for C in is ; for the g input it is (1 + )=(1 + ); nd for the k input it is ( + )=(1 + ) Dynmi lth Figure 4.9 shows dynmi lth: when the lok signl is HIGH, nd its omplement is LOW, the gte output q is set to the omplement of the input d. The totl logil effort of this gte is 4; the logil effort per input for d is, nd the logil effort of the undle is lso. Altering the lth to mke it sttilly stle inreses its logil effort slightly (see Eerise 4-) Dynmi Muller C-element Figure 4.10 shows n inverting dynmi Muller C-element with two inputs. Although this gte is rrely seen in designs for synhronous systems, it is stple of synhronous system design. The ehvior of the gte is s follows: When oth inputs re HIGH, the output goes LOW; when oth inputs go LOW, the output goes HIGH. In other onditions, the output retins its previous vlue the C-element thus retins stte. The totl logil effort of this gte is 4, eqully divided etween the two inputs. An n-input C-element n e formed in the ovious wy, y mking series pullup nd pulldown hins of n trnsistors eh. The width of pulldown trnsistor is n, nd of pullup trnsistor is n. The totl logil effort is thus n(n + n)=(1 + ) =n, nd the logil effort per input is just n.

15 4.5. CATALOG OF LOGIC GATES 7 () () Figure 4.7: Two designs for three-input mjority gtes. () A symmetri design. () An symmetri design with redued logil effort.

16 74 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES g k C in C out g k Figure 4.8: A rry-propgtion gte. The rry rrives on C in nd leves on C out. The g input is HIGH if rry is generted t this stge, nd the k input is LOW if rry is killed t this stge. q d Figure 4.9: A dynmi lth with input d nd output q. The lok undle is.

17 4.5. CATALOG OF LOGIC GATES 75 Figure 4.10: A two-input inverting dynmi Muller C-element. The inputs re nd, nd the output is Upper ounds on logil effort It is esy to estlish n upper ound for the logil effort of gte with n inputs. For ny truth tle, onstrut gte with n rms, eh onsisting of series onnetion of n trnsistors, eh of whih reeives the true or omplement form of different input. For entries in the truth tle tht require LOW output, the series trnsistors in the orresponding rm re ll n-type pulldown trnsistors nd the series string ridges ground nd the logi gte output. The trnsistor gtes in the string reeive inputs in suh wy tht the series onnetion onduts urrent when the input onditions for the truth tle entry re met. For entries in the truth tle tht require HIGH output, the series trnsistors re ll p-type pullups nd the series string spns the positive power supply nd the logi gte output. The trnsistor gtes reeive the omplement of the pproprite input. To design suh gte to hve the sme output drive s the referene inverter, eh n-type trnsistor must hve width n, nd eh p-type trnsistor must hve width n. To ompute the worst-se logil effort, ssume tht 1 nd inputs re onneted only to p-type trnsistors, whih re lrger thn n-type trnsistors nd so offer more lod. Thus the worst-se input pitne is n n, nd the worst-se logil effort is therefore n n =(1 + ). This result shows tht in the worst se, the logil effort of logi gte grows eponentilly with the numer of inputs. These ounds re not prtiulrly tight, nd my perhps e improved. Any improvement will hinge on reduing the numer of trnsistors in gte y shring.

18 76 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES 4.6 Estimting prsiti dely Clulting the prsiti dely of logi gtes is not s esy s lulting logil effort. The prinipl ontriution to the prsiti pitne is the pitne of the diffused regions of trnsistors onneted to the output signl. The pitne of these regions will depend on their lyout geometry nd on proess prmeters. However, rude pproimtion n e otined y imgining tht trnsistor of width w hs diffused region of pitne equl to wc d ssoited with its soure nd n identil region ssoited with its drin. The onstnt C d is property of the frition proess nd the inverter lyout. This model llows us to ompute the prsiti dely of n inverter. The output signl is onneted to two diffused regions: the one ssoited with the pulldown of width 1 will hve pitne C d, nd the one ssoited with the pullup of width will hve pitne C d. The input pitne of the inverter is likewise proportionl to the trnsistor widths, ut with different onstnt of proportionlity hrteristi of trnsistor gte pitne. Thus the input pitne is (1 + )C g. The prsiti dely is the rtio of the prsiti pitne to the input pitne of the inverter, whih is just p inv = C d =C g. The two onstnts of proportionlity n e determined from lyout geometry nd proess prmeters (see Eerise 4-10). We shll dopt nominl vlue of p inv =1:0, whih is representtive of inverter designs. This quntity n e mesured from test iruits, s shown in Setion 5.1. We n estimte the prsiti dely of logi gtes from the inverter prmeters. The dely will e greter thn tht of n inverter y the rtio of the totl width of diffused regions onneted to the output signl to the orresponding width of n inverter, provided the logi gte is designed to hve the sme output drive s the inverter. Thus we hve p = P wd 1+! p inv (4.4) where w d is the width of trnsistors onneted to the logi gte s output. For this estimte to pply, we ssume tht trnsistor lyouts in the logi gtes re similr to those in the inverter. Note tht this estimte ignores other stry pitnes in logi gte, suh s ontriutions from wiring nd from diffused regions tht lie etween trnsistors tht re onneted in series. This pproimtion n e pplied to n n-input NAND gte, whih hs one pulldown trnsistor of width n nd n pullup trnsistors of width onneted to the output signl, so p = np inv. An n-input NOR gte likewise hs p = np inv.

19 4.7. PROPERTIES OF LOGICAL EFFORT 77 Gte type Formul Prsiti dely when p inv =1:0 n=1 n= n= n=4 inverter p inv 1 NAND np inv 4 NOR np inv 4 multipleer np inv XOR, XNOR, prity n n 1 p inv 4 1 mjority 6p inv 6 C-element np inv 4 lth p inv Tle 4.: Estimtes of the prsiti dely of logi gtes. An n-wy multipleer hs n pulldowns of width nd n pullups of width, so p =np inv. Tle 4. summrizes some of these results. The prsiti estimtion hs serious limittion in tht it predits liner sling of dely with numer of inputs. In tulity, the prsiti dely of series stk of trnsistors inreses qudrtilly with stk height euse of internl diffusion nd gte-soure pitnes. The Elmore dely model [9] hndles distriuted RC networks nd shows tht stks of more thn out four series trnsistors re est roken up into multiple stges of shorter stks. Sine prsitis re so geometrydependent, the est wy to find prsiti dely is to simulte iruits with etrted lyout dt. 4.7 Properties of logil effort The lultion of logil effort for logi gte is strightforwrd proess: Design the logi gte, piking trnsistor sizes tht mke it s good driver of output urrent s the referene inverter. The logil effort per input for prtiulr input is the rtio of the pitne of tht input to the totl input pitne of the referene inverter. The totl logil effort of the gte is the sum of the logil efforts of ll of its inputs. Tle 4.1 revels numer of interesting properties. The effet of iruit topology on logil effort is generlly more pronouned thn the effet of frition

20 78 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES tehnology. For CMOS with =, the totl logil effort for -input NAND nd NOR gtes is nerly, ut not quite, three. If CMOS were etly symmetri ( = 1), the totl logil effort for oth NAND nd NOR would e etly three; the symmetry of prtil CMOS proesses fvors NAND gtes over NOR gtes. In ontrst to the wek dependene on, the logil effort of gte depends strongly on the numer of inputs. For emple, the logil effort per input of n n-input NAND gte is (n + )=(1 + ), whih lerly inreses with n. When n dditionl input is dded to NAND gte, the logil effort of eh of the eisting inputs inreses through no fult of its own. Thus the totl logil effort of logi gte inludes term tht inreses s the squre of the numer of inputs; nd in the worst se, logil effort my inrese eponentilly with the numer of inputs. When mny inputs must e omined, this non-liner ehvior fores the designer to hoose refully etween single-stge logi gtes with mny inputs nd multiple-stge trees of logi gtes with fewer inputs per gte. Surprisingly, one logi gte espes super-liner growth in logil effort the multipleer. This property mkes it ttrtive for high fn-in seletors, whih re nlyzed in greter detil in Chpter 11. The logil effort of gtes overs wide rnge. A two-input XOR gte hs totl logil effort of 8, whih is very lrge ompred to the effort of NAND nd NOR of out. The XOR iruit is lso messy to ly out euse the gtes of its trnsistors interonnet with riss-ross pttern. Are the lrge logil effort nd the diffiulty of lyout relted in some fundmentl wy? Wheres the output of most other logi funtions hnges only for ertin trnsitions of the inputs, the XOR output hnges for every input hnge. Is its lrge logil effort relted in some wy to this property? The designs for logi gtes we hve shown in this hpter do not ehust the possiilities. In Chpter 8, logi gtes re designed with redued logil effort for ertin inputs tht n lower the overll dely of prtiulr pth through network. In Chpter 9, we onsider designs in whih the rising nd flling delys of logi gtes differ, whih sves spe in CMOS nd permits nlysis of rtioed NMOS designs with the method of logil effort. 4.8 Eerises 4-1 [0] Show tht Eqution 4.1 orresponds to the definition of logil effort given in Eqution.8.

21 4.8. EXERCISES 79 Figure 4.11: A stti Muller C-element. 4- [0] Modify the lth shown in Figure 4.9 so tht its output is sttilly stle, even when the lok is LOW. How ig should the trnsistors e? Wht is the logil effort of the new iruit? 4- [0] In fshion similr to Eerise 4-, modify the dynmi C-element so tht its output is stti. How ig should the trnsistors e? Wht is the logil effort of the new iruit? 4-4 [0] Another wy to onstrut stti C-element is shown in Figure Wht reltive trnsistor sizes should e used? Wht is the logil effort of the gte? 4-5 [0] Figure 4.8 shows n dder element tht inverts the polrity of the rry signl. A different design will e required for stges tht ept omplemented rry input nd generte true rry output. Design suh iruit nd lulte the logil effort of eh input. 4-6 [10] In mny CMOS proesses the rtio of pullup to pulldown ondutne,, is greter thn. How high does hve to e efore the logil effort of NOR is twie tht of NAND? 4-7 [0] The hoie of trnsistor sizes for the inverter of Figure 4.1 ws influ-

22 80 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES + Figure 4.1: A two-stge XOR iruit. s d q s Figure 4.1: An inverting us driver iruit, equivlent to the funtion of tri-stte inverter. ened y the vlue of. Epress the est pullup nd pulldown trnsistor sizes in n inverter s funtion of to otin minimum dely in two-inverter pir. Consider rising nd flling delys seprtely. 4-8 [0] Compre the logil effort of two-stge XOR iruit suh s shown in Figure 4.1 with tht of the single stge XOR of Figure 4.4. Under wht irumstnes is eh perferle? 4-9 [0] Figure 4.1 shows design for n inverting us driver tht hieves the sme effet s tri-stte inverter. Compre the logil effort of the two iruits. Under whit irumstnes is eh perferle? 4-10 [5] Mesure the gte nd diffusion pitnes of your proess. From these vlues, estimte p inv.