Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here


 Griffin Fletcher
 2 years ago
 Views:
Transcription
1 Sequential Logic Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here " E.g., 35 cents vending = cents + cents + cents + 5 cents " Or, 25 cents + cents = 35 cents. Multiple ways are possible. State requires memory remembering the past... Memory in logic Smallest element is bit of memory Use logic gates to create a bit memory Yet, combinational logic (using gates) depends only on present inputs! Fundamental building block: RS Latch bit of history through feedback of gates 43 RS latch Two NOR gates With feedback Input R,S control writing a or in state Output Current state ( or ) Beware of the feedback! Complement of current state 44
2 RS latch Let s see how it operates! Write a value into the bit state. 45 RS latch When R=, S=, Q(t)= 46 2
3 RS latch When R=, S=, Q(t)= 47 RS latch When R=, S=, Q(t)= 48 3
4 RS latch When R=, S=, Q(t)= 49 RS latch When R=, S=, Q(t)= 5 4
5 RS latch When R=, S= 5 RS latch When R=, S=, and Q(t)= 52 5
6 RS latch When R=, S=, and Q(t)= 53 RS latch What happens if R=S= 54 6
7 RS latch R S Q(t) Q(t+) Q (t+) 55 RS latch R S Q(t) Q(t+) Q (t+) 56 7
8 RS latch truth table Inputs Outputs R S Q(t) Q(t+) Invalid Invalid Storage (R=, S=) Set to (S=) Reset to (R=) Outputs will track any changes in the inputs! R=, S= must be avoided. Desirable to control when to capture input state. 57 Consider RS latch over time Time (t) R S Q(t) Q(t+)
9 Time (t) R S Q(t) Q(t+) Time (t) R S Q(t) Q(t+)
10 Time (t) R S Q(t) Q(t+) Time (t) R S Q(t) Q(t+)
11 Time (t) R S Q(t) Q(t+) Time (t) R S Q(t) Q(t+)
12 Time (t) R S Q(t) Q(t+) D latch Controls when to capture data input Same data outputs as the RS latch One signal (bit) for data input 66 2
13 D latch Note that we have an RS latch in the backend of this design 67 D latch R Inverter for D input with C S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 68 3
14 D latch C=, D= R S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 69 D latch C=, D= R S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 7 4
15 D latch C=, D= Q(t)= R S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 7 D latch C=, D= Q(t)= R S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 72 5
16 D latch R latched mode C D Q(t) Q(t) Q(t) S transparent mode 73 D latch D C D Latch Q Q 74 6
17 D latch D Q D Latch C Q D C Q 75 D flipflop (DFF) Two cascaded D latches; C input of the second is inverted This is a negative edge (aka falling edge ) triggered DFF 76 7
18 D flipflop D C DFF Q Q 77 D flipflop Q D Q DFF transparent storage transparent storage C Q D C data value at falling edge Q Q 78 8
19 State Elements RS latch R,S control mode (reset, set, storage) Q,Q track R and S R=, S= invalid D latch C controls mode (=latched, =transparent) D is data input ( copied during transparent) Signal value triggered: Q,Q track D when C= Guarantees R=,S= can not be done D flipflop (falling or negative edge triggered) Two cascaded D latches C= means st latch transparent, 2 nd latched C= means st latch latched, 2 nd transparent Output changes on falling edge (C: =>) D flipflop (rising or positive edge triggered) Same as falling edge triggered Output changes on rising edge (C: =>) Example circuits and clocking Suppose we want to: bit value A stored in a D flipflop bit value B stored in a D flipflop bit value C stored in a D flipflip Do bit addition of A and B, producing C C = A + B What is the circuit? Need three D flipflops Need one bit adder 84 9
20 Example circuits and clocking A C B How quickly can this produce a new sum C=A+B? Suppose D flipflop: Each latch is 2ns Adder: With ripple carries is 4ns Example circuits and clocking 2
21 Example circuits and clocking Propagation delay = 2ns + 4ns + 2ns = 8ns Read A,B Compute A+B Write C How often can a new sum be produced? Every 8ns! How do we control when to write C? Clock! Example circuits and clocking falling edge Read A,B Compute A+B Write C 2
22 Example circuits and clocking falling edge falling edge 8ns between falling edges Read A,B Compute A+B Write C Clock Frequency Clock frequency is how many edges (falling) per second In our example, how many edges per second? clock frequency Convenient unit of measurements Hertz = Hz = Cycles Per Second = second / 8ns between edges = 9 ns per second / 8ns = 25,, edges per second MegaHertz = MHz = Millions of Cycles Per Second GigaHertz = GHz = Billions of Cycles Per Second For our example, it s 25 MHz clock frequency 9 22
23 Clock Frequency Suppose delay between edges was.5ns What is the clock frequency? Clock frequency = second / time between edges = second /.5ns = 9 ns per second /.5ns = 2,,, edges per second = 2 MHz clock frequency = 2. GHz clock frequency 9 Example circuits and clocking Is there any difference in the delay with this one? In fact, sequential logic often looks like this
24 Example circuits and clocking Now, suppose we want to build a 4bit counter? Counter increments by for a clock pulse (falling edge event) 4 bit adders 4 bit D flipflops What s the circuit? How often to pulse the clock (increment counter)? 93 Example circuits and clocking Recall: The flipflops are edge triggered  assuming falling edge (negative) How often can an edge event happen? No more frequent than the maximum propagation delay Let s compute the delay  assume 2ns for latch to stabilize and 4ns for adder 24
25 Example circuits and clocking Values of output bits must all be stable I.e., can t pulse the clock (increment) until all four bits are computed Adder circuit is ripplecarry: Must wait for carries 4ns per adder 4bit adder thus, 4 * 4ns = 6ns for the adder Flipflops Must wait for st latch of last bit to stabilize (others done in parallel) Must wait for 2 nd latch of all bits to stabilize (all done in parallel) thus, 2ns + 2ns = 4ns Overall delay = 6ns + 4ns = 2ns. Clock pulse is 2ns. 95 Example circuits and clocking Can we build a counter with just flipflops? What s the propagation delay? 96 25
ECE 301 Digital Electronics
ECE 301 Digital Electronics Latches and FlipFlops (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and
More informationChapter 5: Sequential Circuits (LATCHES)
Chapter 5: Sequential Circuits (LATCHES) Latches We focuses on sequential circuits, where we add memory to the hardware that we ve already seen Our schedule will be very similar to before: We first show
More informationLatches, the D FlipFlop & Counter Design. ECE 152A Winter 2012
Latches, the D FlipFlop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationSequential Circuits. Chapter 4 S. Dandamudi
Sequential Circuits Chapter 4 S. Dandamudi Outline Introduction Clock signal Propagation delay Latches SR latch Clocked SR latch D latch JK latch Flip flops D flip flop JK flip flop Example chips Example
More informationFlipFlops. Revision of lecture notes written by Dr. Timothy Drysdale
FlipFlops Revision of lecture notes written by Dr. Timothy Drysdale Objectives of Lecture The objectives of this lecture are: to discuss the difference between combinational and sequential logic as well
More informationBasic Bit Memory: Latches and Flip Flops
Basic Bit Memory: Latches and Flip Flops Topics: 1. General description of bit memory, also called a memory cell. 2. Definition of sequential and combinational circuits. Memory devices are sequential devices.
More informationChapter 14 Sequential logic, Latches and FlipFlops
Chapter 14 Sequential logic, Latches and FlipFlops Flops Lesson 2 Sequential logic circuit, Flip Flop and Latch Introduction Ch14L2"Digital Principles and Design", Raj Kamal, Pearson Education, 2006
More informationChapter  5 FLIPFLOPS AND SIMPLE FLIPFLOP APPLICATIONS
Chapter  5 FLIPFLOPS AND SIMPLE FLIPFLOP APPLICATIONS Introduction : Logic circuit is divided into two types. 1. Combinational Logic Circuit 2. Sequential Logic Circuit Definition : 1. Combinational
More informationLogic Design. Flip Flops, Registers and Counters
Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and
More informationClocks. Sequential Logic. A clock is a freerunning signal with a cycle time.
Clocks A clock is a freerunning signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high
More informationCHAPTER 11 LATCHES AND FLIPFLOPS
CHAPTER 11 LATCHES AND FLIPFLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 SetReset Latch 11.3 Gated D Latch 11.4 EdgeTriggered D FlipFlop 11.5 SR FlipFlop
More informationApplications of EdgeTriggered D Flipflop
Applications of EdgeTriggered D Flipflop 1. Data Storage using Dflipflop A Multiplexer based ParalleltoSerial converter needs to have stable parallel data at its inputs as it converts it to serial
More informationSequential Circuits Sequential circuits combinational circuits clocked sequential circuits gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
More informationLatches and flipflops
CSE4: Components and Design Techniques for Digital Systems Latches and flipflops Tajana Simunic osing Sources: Where we are now What we ve covered so far Combinational circuits: Chap,2 HW#5 out What comes
More informationIn Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current
Module 12 In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current inputs. The following topics will be on sequential
More informationCombinational and Sequential Circuits.
Combinational and Sequential Circuits. Basically, sequential circuits have memory and combinational circuits do not. Here is a basic depiction of a sequential circuit. All sequential circuits contain combinational
More informationSAMPLE OF THE STUDY MATERIAL PART OF CHAPTER 5. Combinational & Sequential Circuits
SAMPLE OF THE STUD MATERIAL PART OF CHAPTER 5 5. Introduction Digital circuits can be classified into two types: Combinational digital circuits and Sequential digital circuits. 5.2 Combinational Digital
More informationLecture 9: Flipflops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flipflops and latches Lecture 9: Flipflops Professor Peter Cheung Department of EEE, Imperial
More informationREGISTERS. Consists of a set of flipflops (each flipflop stores one bit of information)
REGISTERS Sequential circuit used to store binary word Consists of a set of flipflops (each flipflop stores one bit of information) External gates may be used to control the inputs of the flipflops:
More informationExperiment # 8 Latches And Flip Flops Characteristics
Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 8 Latches And Flip Flops Characteristics
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4bit ripplethrough decade counter with a decimal readout display. Such a counter
More informationSequential Logic Circuits Part I (Memory Element)
Sequential Logic Circuits Sequential Logic Circuits Part I (Memory Element) CIT 595 Spring 2010 Output depends on stored information (current state) and may be on current inputs Example: state = Score
More informationSEQUENTIAL CIRCUITS. Block diagram. Flip Flop. SR Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
More informationLecture 10. Latches and FlipFlops
Logic Design Lecture. Latches and FlipFlops Prof. Hyung Chul Park & Seung Eun Lee Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly
More informationSequential Logic. SR Latch
n 2/24/3 Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly remember certain previous inputs, or it might distill (encode) the
More informationENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 19 Sequential Circuits: Latches Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine
More informationECE380 Digital Logic
ECE38 Digital Logic FlipFlops, egisters and Counters: Latches Dr. D. J. Jackson Lecture 24 torage elements Previously, we have considered combinational circuits where the output values depend only on
More information1) For a RS flip flop constructed out of NAND gates complete the following table. R S Q Q\ State name Q Q\
Sequential logic tutorial Flip Flops 1) For a RS flip flop constructed out of NAND gates complete the following table R S Q Q\ State name 0 0 1 1 0 1 0 1 1 0 1 0 1 1 Q Q\ 2) Complete the following timing
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationChapter 3 :: Sequential Logic Design
Chapter 3 :: Sequential Logic Design Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Copyright 2007 Elsevier 3 Bistable Circuit Fundamental building block of other state
More informationIE1204 Digital Design L8: Memory Elements: Latches and FlipFlops. Counter
IE1204 igital esign L8: Memory Elements: Latches and FlipFlops. Counter Elena ubrova KTH / ICT / ES dubrova@kth.se This lecture BV pp. 383418, 469471 IE1204 igital esign, HT14 2 Sequential System a(t)
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop. describe how such a flipflop can be SET and RESET. describe the disadvantage
More informationDesign Example: Counters. Design Example: Counters. 3Bit Binary Counter. 3Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
More informationSequential Circuits: Latches and FlipFlops
Sequential Circuits: Latches and FlipFlops Sequential circuits Output depends on current input and past sequence of input(s) How can we tell if the input is current or from the past? A clock pulse can
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationCHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS This chapter in the book includes: Objectives Study Guide 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing and Timing Charts 13.3 State
More informationEE 110 Practice Problems for Exam 2: Solutions, Fall 2008
EE 110 Practice Problems for Exam 2: Solutions, Fall 2008 1. Circle T (true) or F (false) for each of these Boolean equations. (a). T FO An 8to1 multiplexer requires 2 select lines. (An 8to1 multiplexer
More informationBINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
More informationChapter 14 Sequential logic, Latches and FlipFlops
Chapter 14 Sequential logic, Latches and FlipFlops Flops Lesson 6  Flip Flop and Latch Ch14L6"igital Principles and esign", Raj Kamal, Pearson Education, 2006 2  FlipFlop + ve edge triggered Output
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. PuJen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits PuJen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationKarnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g.
Karnaugh Maps Yet another way of deriving the simplest Boolean expressions from behaviour. Easier than using algebra (which can be hard if you don't know where you're going). Example A B C X 0 0 0 0 0
More informationFlipFlops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 FlipFlops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech  3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationLesson 12 Sequential Circuits: FlipFlops
Lesson 12 Sequential Circuits: FlipFlops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
More information1. A Sequential Parity Checker
Chapter 13: Analysis of Clocked Sequential Circuits 1. A Sequential Parity Checker When binary data is transmitted or stored, an extra bit (called a parity bit) is frequently added for purposes of error
More informationDigital Design, Kyung Hee Univ. Spring, Chapter 5. Synchronous Sequential Logic
Chapter 5. Synchronous Sequential Logic 1 5.1 Introduction Electronic products: ability to send, receive, store, retrieve, and process information in binary format Dependence on past values of inputs Sequential
More informationDigital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian Email: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief Email: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An nbit register
More informationLatches and Flipflops
Latches and Flipflops Latches and flipflops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0
More informationAnalysis of Clocked (Synchronous) Sequential Circuits
Analysis of Clocked (Synchronous) Sequential Circuits Now that we have flipflops and the concept of memory in our circuit, we might want to determine what a circuit is doing. The behavior of a clocked
More informationSequential Circuits: Latches & FlipFlops
ESD I Lecture 3.b Sequential Circuits: Latches & FlipFlops 1 Outline Memory elements Latch SR latch D latch FlipFlop SR flipflop D flipflop JK flipflop T flipflop 2 Introduction A sequential circuit
More informationECE 223 Digital Circuits and Systems. Synchronous Logic. M. Sachdev. Dept. of Electrical & Computer Engineering University of Waterloo
ECE 223 Digital Circuits and Systems Synchronous Logic M. Sachdev Dept. of Electrical & Computer Engineering University of Waterloo Sequential Circuits Combinational circuits Output = f (present inputs)
More informationLecture 8: Flipflops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flipflops and latches Lecture 8: Flipflops Professor Peter Cheung Department of EEE, Imperial
More informationModule 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits
Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Objectives In this lecture you will learn the delays in following circuits Motivation Negative DLatch SR Latch
More informationSlides for Lecture 23
Slides for Lecture 23 ENEL 353: Digital Circuits Fall 213 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 1 November, 213 ENEL 353 F13
More informationUnit 4 Session  15 FlipFlops
Objectives Unit 4 Session  15 FlipFlops Usage of D flipflop IC Show the truth table for the edgetriggered D flipflop and edgetriggered JK flipflop Discuss some of the timing problems related to
More informationLecture 2. Introduction to Sequential Circuits
21 Lecture 2 Introduction to Sequential Circuits 1 Youpyo Hong, ongguk University 22 igital Circuits Combinational circuits  Outputs are determined by current inputs only.  Memory is not included.
More informationLatches and Flipflops
Latches and Flipflops Latches and flipflops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0
More informationLecture 22: Sequential Circuits. Sequential Circuits. Characteristic Table, SR Latch. SR Latch (Clocked) Latches:
Lecture 22: Sequential Circuits Latches: SR D JK FlipFlops Memory Sequential Circuits In sequential circuits, new state depends on not only the input, but also on the previous state. Devices like registers
More informationFigure 2.4(f): A T flip flop
If the T input is in 0 state (i.e., J = K = 0) prior to a clock pulse, the Q output will not change with the clock pulse. On the other hand, if the T input is in 1 state (i.e., J = K = 1) prior to a clock
More informationSequential Circuits: Latches & FlipFlops
Sequential Circuits: Latches & FlipFlops Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc
More informationLECTURE #11: FlipFlops and Basic Sequential Design EEL 3701: Digital Logic and Computer Systems Based on lecture notes by Dr. Eric M.
LECTURE #: FlipFlops and Basic Sequential Design EEL 370: Digital Logic and Computer Systems Based on lecture notes by Dr. Eric M. Schwartz Problem with Enabled Latches:  Consider an SR Latch controlling
More informationCSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap 5, App. A& B) Number representations Boolean algebra OP and PO Logic
More informationLatches and FlipFlops
Latches and FlipFlops Introduction to sequential logic Latches SR Latch Gated SR Latch Gated Latch FlipFlops JK Flipflop Flipflop T Flipflop JK MasterSlave Flipflop Preset and Clear functions 7474
More informationTheory of Logic Circuits. Laboratory manual. Exercise 3
Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices
More informationChapter 5 Latch and flipflop
257 Chapter 5 Latch and flipflop «from the ground up I2013b  Copyright Daniele Giacomini  appunti2@gmail.com http://a3.informaticalibera.net 5.1 Propagation delay..................................
More informationBasic bistable element. Chapter 6. Latches vs. flipflops. Flipflops
Basic bistable element hapter 6 It is a circuit having two stable conditions (states). It can be used to store binary symbols. FlipFlops and Simple FlipFlop Applications.. Huang, 24 igital Logic esign
More informationOverview. Ripple Counter Synchronous Binary Counters
Counters Overview Ripple Counter Synchronous Binary Counters Design with D FlipFlops Design with JK FlipFlops Serial Vs. Parallel Counters Updown Binary Counter Binary Counter with Parallel Load BCD
More informationSynchronous Sequential Logic. Logic and Digital System Design  CS 303 Erkay Savaş Sabanci University
Synchronous Sequential Logic Logic and Digital System Design  S 33 Erkay Savaş Sabanci University Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs
More informationTransistors. The Digital Logic Level. Boolean Algebra truth tables are very cumbersome introduce notation to capture only 1 s: Gates 2/7/2013
The Digital Logic Level Transistors lowest level just above transistors digital circuits collections of gates and wires only deal with 0 s and s described by Boolean algebra a transistor is a switch with
More informationCHAPTER TEN. 10.1 New Truth Table Symbols. 10.1.1 Edges/Transitions. Memory Cells
CHAPTER TEN Memory Cells The previous chapters presented the concepts and tools behind processing binary data. This is only half of the battle though. For example, a logic circuit uses inputs to calculate
More informationCombinational circuits: ALU
Combinational circuits: ALU ALU is a combinational circuit outputs depend only on inputs operations performed AND OR ADD SUB SLT Zero (a == b) This is an ARITHMETIC/logic unit (Fig. 4.21) What about multiplication?
More informationSequential Logic Latches & Flipflops
Sequential Logic Latches & Flipflops Introduction Memory Elements PulseTriggered Latch SR Latch Gated SR Latch Gated D Latch EdgeTriggered Flipflops SR Flipflop D Flipflop JK Flipflop T Flipflop
More informationCounters. Nonsynchronous (asynchronous) counters A 2bit asynchronous binary counter High
Counters Learning objectives Understanding the operation and characteristics of asynchronous and synchronous counters Analyze counter circuits and counter timing diagrams Determine the sequence of a counter
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationChapter 8. Sequential Circuits for Registers and Counters
Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters TFF Basic Counting element State
More informationToday. Sequential logic Latches Flipflops Counters. Andrew H. Fagg: Embedded RealTime Systems: Sequential Logic
Today Sequential logic Latches Flipflops Counters Time Until now: we have essentially ignored the issue of time We have assumed that our digital logic circuits perform their computations instantaneously
More informationFlipFlops. Outline: 2. Timing noise
Outline: 2. Timing noise FlipFlops Signal races, glitches FPGA example ( assign bad) Synchronous circuits and memory Logic gate example 4. FlipFlop memory RSlatch example D and JK flipflops Flipflops
More information16 Latches and FlipFlops
6 Latches and FlipFlops Latches and flipflops are used as memory (storage) elements in sequential logic (FSMs, counters). Latches are controlled (gated) by clock signal levels (logic state control).
More informationRecap & Perspective. Sequential Logic Circuits & Architecture Alternatives. Register Operation. Building a Register. Timing Diagrams.
Sequential Logic Circuits & Architecture Alternatives Recap & Perspective COMP 251 Computer Organization and Architecture Fall 2009 So Far: ALU Implementation Next: Register Implementation Register Operation
More informationCS 226: Digital Logic Design
CS 226: Digital Logic Design 0 1 1 I S 0 1 0 S Department of Computer Science and Engineering, Indian Institute of Technology Bombay. 1 of 44 Objectives In this lecture we will introduce: 1. Synchronous
More informationArithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See P&H 2.4 (signed), 2.5, 2.6, C.6, and Appendix C.
Arithmetic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H 2.4 (signed), 2.5, 2.6, C.6, and Appendix C.6 Goals for today Binary (Arithmetic) Operations Onebit and fourbit
More informationAn astable multivibrator acts as an oscillator (clock generator) while a monostable multivibrator can be used as a pulse generator.
Concepts In sequential logic, the outputs depend not only on the inputs, but also on the preceding input values... it has memory. Memory can be implemented in 2 ways: Positive feedback or regeneration
More informationUnit 3 Combinational MOS Logic Circuits
Unit 3 ombinational MOS Logic ircuits LATH Latch It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its input
More informationLecture 9: FlipFlops, Registers, and Counters
Lecture 9: FlipFlops, Registers, and Counters 1. T FlipFlops toggles its output on a rising edge, and otherwise keeps its present state. 1.1. Since the toggle from high to low to high takes two clock
More informationECE380 Digital Logic
ECE38 igital Logic FlipFlops, Registers and Counters: FlipFlops r.. J. Jackson Lecture 25 Flipflops The gated latch circuits presented are level sensitive and can change states more than once during
More informationSynchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic 5 Outline! Sequential Circuits! Latches! FlipFlops! Analysis of Clocked Sequential Circuits! State Reduction and Assignment! Design Procedure 52 Sequential Circuits!
More informationCSEE 3827: Fundamentals of Computer Systems. Latches and Flip Flops
EE 3827: Fundamentals of omputer ystems Latches and Flip Flops ombinational v. sequential logic Inputs ombinational circuit Outputs Inputs ombinational circuit next state Outputs current state torage elements
More informationFinal Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flipflop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
More informationLab 1 Physics 430 Laboratory Manual 1. LAB 1 Logic Gates, Flip Flops and Registers
Lab Physics 430 Laboratory Manual LAB Logic Gates, Flip Flops and Registers In this first lab we assume that you know a little about logic gates and using them. The first experiment is an exericse to help
More informationChapter 5 Bistable memory devices. Copyright The McGrawHill Companies, Inc. Permission required for reproduction or display.
Chapter 5 Bistable memory devices Copyright The McGrawHill Companies, Inc. Permission required for reproduction or display. Digital circuits Combinational Sequential Logic gates Decoders, MUXes, Adders,
More information3 FlipFlops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.
3 FlipFlops Flipflops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory
More informationModeling Latches and Flipflops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
More informationTopic Notes: Sequential Circuits
Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 opic Notes: Sequential Circuits We have seen many examples of what we can do with combinational logic taking a set of
More informationDIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
More information1. Realization of gates using Universal gates
1. Realization of gates using Universal gates Aim: To realize all logic gates using NAND and NOR gates. Apparatus: S. No Description of Item Quantity 1. IC 7400 01 2. IC 7402 01 3. Digital Trainer Kit
More informationDIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flipflops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC
More informationCHAPTER 4. Sequential Logic design principles
HAPTE 4 Sequential Logic design principles Logic circuits are defined into two types, combinational and sequential. A combinational logic circuit is one whose outputs depend only on its current inputs.
More informationECE 331 Digital System Design
ECE 331 Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #21) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More information