# Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here

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1 Sequential Logic Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here " E.g., 35 cents vending = cents + cents + cents + 5 cents " Or, 25 cents + cents = 35 cents. Multiple ways are possible. State requires memory remembering the past... Memory in logic Smallest element is bit of memory Use logic gates to create a -bit memory Yet, combinational logic (using gates) depends only on present inputs! Fundamental building block: RS Latch -bit of history through feedback of gates 43 RS latch Two NOR gates With feedback Input R,S control writing a or in state Output Current state ( or ) Beware of the feedback! Complement of current state 44

2 RS latch Let s see how it operates! Write a value into the -bit state. 45 RS latch When R=, S=, Q(t)= 46 2

3 RS latch When R=, S=, Q(t)= 47 RS latch When R=, S=, Q(t)= 48 3

4 RS latch When R=, S=, Q(t)= 49 RS latch When R=, S=, Q(t)= 5 4

5 RS latch When R=, S= 5 RS latch When R=, S=, and Q(t)= 52 5

6 RS latch When R=, S=, and Q(t)= 53 RS latch What happens if R=S= 54 6

7 RS latch R S Q(t) Q(t+) Q (t+) 55 RS latch R S Q(t) Q(t+) Q (t+) 56 7

8 RS latch truth table Inputs Outputs R S Q(t) Q(t+) Invalid Invalid Storage (R=, S=) Set to (S=) Reset to (R=) Outputs will track any changes in the inputs! R=, S= must be avoided. Desirable to control when to capture input state. 57 Consider RS latch over time Time (t) R S Q(t) Q(t+)

9 Time (t) R S Q(t) Q(t+) Time (t) R S Q(t) Q(t+)

10 Time (t) R S Q(t) Q(t+) Time (t) R S Q(t) Q(t+)

11 Time (t) R S Q(t) Q(t+) Time (t) R S Q(t) Q(t+)

12 Time (t) R S Q(t) Q(t+) D latch Controls when to capture data input Same data outputs as the RS latch One signal (bit) for data input 66 2

13 D latch Note that we have an RS latch in the back-end of this design 67 D latch R Inverter for D input with C S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 68 3

14 D latch C=, D= R S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 69 D latch C=, D= R S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 7 4

15 D latch C=, D= Q(t)= R S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 7 D latch C=, D= Q(t)= R S Note that R, S inputs always get opposite values when C= When C=, S=R= RS latch remembers the previous value 72 5

16 D latch R latched mode C D Q(t) Q(t-) Q(t-) S transparent mode 73 D latch D C D Latch Q Q 74 6

17 D latch D Q D Latch C Q D C Q 75 D flip-flop (D-FF) Two cascaded D latches; C input of the second is inverted This is a negative edge (aka falling edge ) triggered D-FF 76 7

18 D flip-flop D C D-FF Q Q 77 D flip-flop Q D Q D-FF transparent storage transparent storage C Q D C data value at falling edge Q Q 78 8

19 State Elements RS latch R,S control mode (reset, set, storage) Q,Q track R and S R=, S= invalid D latch C controls mode (=latched, =transparent) D is data input ( copied during transparent) Signal value triggered: Q,Q track D when C= Guarantees R=,S= can not be done D flip-flop (falling or negative edge triggered) Two cascaded D latches C= means st latch transparent, 2 nd latched C= means st latch latched, 2 nd transparent Output changes on falling edge (C: =>) D flip-flop (rising or positive edge triggered) Same as falling edge triggered Output changes on rising edge (C: =>) Example circuits and clocking Suppose we want to: -bit value A stored in a D flip-flop -bit value B stored in a D flip-flop -bit value C stored in a D flip-flip Do -bit addition of A and B, producing C C = A + B What is the circuit? Need three D flip-flops Need one bit adder 84 9

20 Example circuits and clocking A C B How quickly can this produce a new sum C=A+B? Suppose D flip-flop: Each latch is 2ns Adder: With ripple carries is 4ns Example circuits and clocking 2

21 Example circuits and clocking Propagation delay = 2ns + 4ns + 2ns = 8ns Read A,B Compute A+B Write C How often can a new sum be produced? Every 8ns! How do we control when to write C? Clock! Example circuits and clocking falling edge Read A,B Compute A+B Write C 2

22 Example circuits and clocking falling edge falling edge 8ns between falling edges Read A,B Compute A+B Write C Clock Frequency Clock frequency is how many edges (falling) per second In our example, how many edges per second? clock frequency Convenient unit of measurements Hertz = Hz = Cycles Per Second = second / 8ns between edges = 9 ns per second / 8ns = 25,, edges per second MegaHertz = MHz = Millions of Cycles Per Second GigaHertz = GHz = Billions of Cycles Per Second For our example, it s 25 MHz clock frequency 9 22

23 Clock Frequency Suppose delay between edges was.5ns What is the clock frequency? Clock frequency = second / time between edges = second /.5ns = 9 ns per second /.5ns = 2,,, edges per second = 2 MHz clock frequency = 2. GHz clock frequency 9 Example circuits and clocking Is there any difference in the delay with this one? In fact, sequential logic often looks like this

24 Example circuits and clocking Now, suppose we want to build a 4-bit counter? Counter increments by for a clock pulse (falling edge event) 4 -bit adders 4 -bit D flip-flops What s the circuit? How often to pulse the clock (increment counter)? 93 Example circuits and clocking Recall: The flip-flops are edge triggered -- assuming falling edge (negative) How often can an edge event happen? No more frequent than the maximum propagation delay Let s compute the delay -- assume 2ns for latch to stabilize and 4ns for adder 24

25 Example circuits and clocking Values of output bits must all be stable I.e., can t pulse the clock (increment) until all four bits are computed Adder circuit is ripple-carry: Must wait for carries 4ns per adder 4-bit adder thus, 4 * 4ns = 6ns for the adder Flip-flops Must wait for st latch of last bit to stabilize (others done in parallel) Must wait for 2 nd latch of all bits to stabilize (all done in parallel) thus, 2ns + 2ns = 4ns Overall delay = 6ns + 4ns = 2ns. Clock pulse is 2ns. 95 Example circuits and clocking Can we build a counter with just flip-flops? What s the propagation delay? 96 25

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