Sequential Logic. SR Latch


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1 n 2/24/3 Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly remember certain previous inputs, or it might distill (encode) the prior inputs into a smaller amount of information called state The state is a set of bits that contain all the information about the past necessary to determine the future behavior of the circuit State elements Bistable circuit SR Latch D Latch D Flipflop n SR Latch One of the simplest sequential circuits is the SR (Set/ Reset) latch It is composed of 2 crosscoupled NOR gates It has 2 inputs (S, R) and 2 outputs ( and ) When the set input (S) is (and R = ), is set to Set makes the output () to When the reset input (R) is (and S = ), is reset to Reset makes the output () to R N SR Latch Symbol R S N2 S n 2 n
2 n 2/24/3 SR Latch Analysis Consider the four possible cases: a) S =, R = b) S =, R = c) S =, R = d) S =, R = n 3 SR Latch Analysis a) S =, R = : then = and = R N S N2 b) S =, R = : then = and = R N S N2 n 4 n 2
3 n 2/24/3 SR Latch Analysis c) S =, R = : then = prev and = prev We got Memory! prev = prev = R N R N N2 S S N2 d) S =, R = : then = and = Invalid state: NOT R S N N2 n 5 SR Latch Recap SR latch stores one bit of state Where is it stored? SR latch can control the state with S and R inputs SR latch generates the invalid state when S = and R = n 6 n 3
4 n 2/24/3 D Latch D latch solves the problem of the SR latch D latch blocks the invalid state when S = and R = D latch separates when and what the state should be changed D latch has 2 inputs (, D) and 2 outputs (, ) controls when the output changes D (data input) controls what the output changes to Avoids invalid case ( NOT when both S and R are ) D Latch Symbol D n 7 D Latch Internal & Operation D latch operation When =, D passes through to (D latch is transparent) When =, holds its previous value (D latch is opaque) D D R S R S D D X D S R X prev prev prev prev n 8 n 4
5 n 2/24/3 D Latch Waveform When evaluating latch, it would be confusing if you think previous and current value things For good intuition, think with waveform When =, D latch transfers input data (D) to output () When =, D latch maintains its previous value n 9 D FlipFlop In digital logic design, it is very convenient if we can store input data at a certain moment (not during the whole time interval like D latch) D flipflop provides that functionality changes only on the rising edge of When rises from to, D passes through to Otherwise, holds its previous value Thus, a flipflop is called an edgetriggered device because it is activated on the clock edge D FlipFlop Symbols D n n 5
6 n 2/24/3 D FlipFlop Internal Circuit Two backtoback latches (L and L2) controlled by complementary clocks When = L is transparent L2 is opaque D passes through to N When = L2 is transparent L is opaque N passes through to D D L N D L2 Thus, on the edge of the clock (when rises from to ) D effectively passes through to n D FlipFlop Note that input data should not be changed around the clock edge for D flipflop to work correctly D D L N D L2 n 2 n 6
7 n 2/24/3 D FlipFlop So, D flipflop has the effect of sampling the current input data at the rising edge of the clock Note again that input data should not be changed around the clock edge for D flipflop to work correctly n 3 Registers An Nbit register is a set of N flipflops that share a common input, so that all bits of the register are updated at the same time You can say Nbit flipflops or Nbit register Registers are the key building block of sequential circuits D D D D D 3: 4 4 3: D 2 D 2 D 3 D 3 n 4 n 7
8 n 2/24/3 Enabled FlipFlops Enabled flipflips are useful when we wish to load a new value into a flipflop only during some of the time, rather than on every clock edge Enabled flipflop has one more input (EN) The enable input (EN) controls when new data (D) is stored When EN =, D passes through to on the clock edge When EN =, the flipflop retains its previous state Internal Circuit Symbol EN D D D EN n 5 Resettable FlipFlops Resettable flipflops are useful when we want to force a known state (i.e., ) into some flipflops in a system when we first turn it on Resettable flipflop has Reset input When Reset is active, is reset to When Reset is deactivated, the flipflop behaves like an ordinary D flipflop Resettable flipflop D Reset Symbols r There are two types of resettable flipflops Synchronous resettable FF resets at the clock edge only Asynchronous resettable FF resets immediately when Reset is active Asynchronously resettable flipflop requires changing the internal circuitry of the flipflop Synchronously resettable flipflop D Reset Internal Circuit D n 6 n 8
9 n 2/24/3 Settable FlipFlops Settable flipflops are also useful when we want to force a known state (i.e., ) into some flipflops in a system when we first turn it on Settable flipflop has Set input When Set is active, is set to When Set is deactivated, the flipflop behaves like an ordinary D flipflop They comes in two flavors: Synchronous settable and Asynchronous settable Symbols D Set s n 7 Registers n A register is a group of flipflops. An nbit register is made of n flipflips and can store n bits A register may have additional combinational gates to perform certain operations n 9
10 n 2/24/3 4Bit Register A simple 4bit register can be made with 4 DFF Data is loaded in parallel Common Clock At each positiveedge, 4 bits are loaded in parallel Previous data is overwritten Entering data is called loading Common Clear Asynchronous activelow clear When Clear =, all FFs are cleared; i.e. is stored. 4Bit Register (cont.) uestion: How to modify this register to enable/disable loading new data (overwriting previous)? n
11 n 2/24/3 4Bit Register (cont.) uestion: How to modify this register to enable/disable loading new data (overwriting previous)? Answer: When Load=, the clock input to the FFs will never take a transition ( to, to ), no new data will be loaded. When Load=, normal data loading takes place This is called clock gating 4Bit Register (cont.) Clock Skew Problem: It results from clock gating. n
12 n 2/24/3 4Bit Register (cont.) Better Solution: Register with Parallel Load Use a 2x MUX as shown: n : Why a DFF output is feedback? 4Bit Register (cont.) A 4bit Parallel Load Register When Load =, the data is not changed (no loading) When Load =, the data is loaded in parallel at the rising edge (+ve) n load n clock n 2
13 n 2/24/3 Shift Registers n A shift register is a register which shifts its content (right, left, or both) Made of flipflops with common clock Useful to load data serially 4bit Shift Register A simple 4bit shift register can be made with 4 DFF Common Clock At each positiveedge, bit is shifted in Rightmost bit is discarded Which direction this register is shifting? n 3
14 n 2/24/3 Using Shift Register (Examples) Serial Addition Shift Register with Parallel Load Two control inputs (shift, load) Each stage consists of DFF OR gate Three AND gates AND to enable shift AND to enable load AND for no change Idea: Use a MUX to implement more functions (see next slides) i à i D D D 2 D 3 n Serial Input à n i à i ; i=,,3 n 4
15 n 2/24/3 Universal Shift Register uestion: Design a Universal Shift Register with the following capabilities: A clear control to clear the register to A clock to synchronize the operations A shiftright control (associated with serial in/out) A shiftleft control (associated with serial in/out) A parallelload control (to parallel load n bits) nparallel output lines A control signal to leave register unchanged Universal Shift Register (cont.) n 5
16 n 2/24/3 Universal Shift Register (cont.) How does it work? 4 DFF and 4 MUXs with selection S,S S S =, FF output is feedback to its input S S =, FF input comes from left FF or serialin (shiftright) S S =, FF input comes from right FF or serialin (shiftleft) S S =, parallel data transferred in Applications: Parallel Serial conversions Arithmetic multiplication/division Delaying input sequence Counters Counter: A register (sequential circuit) that goes through a predetermined sequence of states upon the application of input (clock or other source) pulses Binary Counter: The sequence of the states follows the binary number sequence (e.g. à à à à etc.) nbit binary counter requires n flipflops counts from to 2 n  Sequences can be binary, BCD, random, etc. Counting can be up, down A modulon counter goes through values,,2,, (n) e.g. modulo up counter counts:,, 9 Two Types of Counters: Ripple counter (asynchronous): Flipflop output transition serves as source for triggering the other flipflops Synchronous counter: common clock for all flipflops (same design procedure) n 6
17 n 2/24/3 Ripple Counters Instead of having a common clock signal to all Flip Flops, in a Ripple counter the output of one stage (Flip Flop) is connected to the clock input of the next stage T or JK flip flops are used for this construction because of their capability to flip their stored bits (J=K=T=) Clock is connected to the least significant bit Flip flops are negative edgetriggered (clock is bubbled) are active when the clock signal is falling (high to low) Flip flops invert their stored bits, when the input clock signal goes from high () to low () n clock pulses n Logic n clear n J n C n n n K n R n J n C n n n K n R n J n C n n n K n R n J n C n n n K n R n n n 2 n 3 Ripple Counters (cont.) 3 2 n clock pulses n J n C n n n K n R n n. n. n. n. n. n. n. n. n J n C n n n K n R n J n C n n n 2 n : How to make it count down? n 2: What if we use positiveedge FF? n 3: What if we use instead of? n 4: Is this counter asynchronous? Why? n Logic n clear n n K n R n J n C n n n K n R n 3 n 7
18 n 2/24/3 Ripple Counters with TFF/DFF Alternative implementation of a 4bit ripple counter using TFF and DFF For a DFF, connecting to D makes it to toggle at each clock! n Src: Mano s Textbook Ripple Counters Advantages: Simple hardware Disadvantages: Asynchronous delay dependent Good for low power circuits n 8
19 n 2/24/3 Synchronous Counters Common clock to all FFs Design following the same design procedure for synchronous sequential circuits (see slides 4_3) Important: Study the examples in slides 4_3 Counters have a regular pattern Alternatively, counters can be designed without following the procedure (algorithmically, hierarchically) 4bit Synchronous Binary Counter When EN = à No change When EN = Least significant bit (A ) toggles at every clock Other FFs toggle when all lower FFs are equal to (e.g. à ) uestion: What will happen if we use a negative edge triggered FF? n Building Bigger Counter n Clock n A n A n A n A n En n A 2 n A 3 n CO n En n A 2 n A 3 n CO n CO n 9
20 n 2/24/3 4bit Synchronous Binary Counter with DFF When En =, feed back same value When En =, increment the saved value at each clock n Increment er n + n A3 n Y3 n A2 n Y2 n A n Y n A n Y n D3 n 3 n D2 n 2 n D n n D n n symbol XORs act like an adder EN = à EN = à Tip: XOR + DFF = TFF Arbitrary Count Sequence Problem: Design a counter that has a repeated sequence of 6 states, as listed in table. In this sequence, flipflops B and C repeat the binary count,,, while flipflop A alternates between and every three counts. n Notes: Only 6 states (Module6), are missing Follow the usual design procedure Present State Next State A B C A B C n 2
21 n 2/24/3 Arbitrary Count Sequence State Table Assuming JK flipflops Present State Next State Flipflop Inputs A B C A B C JA KA JB KB JC KC X X X X X X X X X X X X X X X X x x Arbitrary Count Sequence Input Equations BC A x x x x x n JA = B BC A x x x x n JB = C BC A x x x x n JC = B BC A x x x x x n KA = B BC A x x x x x x n KB = BC A x x x x x x n KC = n 2
22 n 2/24/3 n Arbitrary Count Sequence Unused States n Logic n JA = B n JB = C n JC = B n clock n KA = B n KB = n KC = n J A n A n C n K n A A n J B n B n C n K n B B n J C n C n C n K n C C n n n n n n n n n ) What if the counter finds itself in state or state? Will the counter be able to proceed (count) normally afterward? How? n 2) Is this circuit safe or reliable? Summary Registers and Counters are versatile sequential circuits Registers Parallel Load Registers Shift Registers Universal Shift Registers Counters Ripple counters Synchronous counters n 22
23 n 2/24/3 Finite State Machine (FSM) Finite state machine (FSM) is composed of 2 components: registers and combinational logic Register represents one of the finite number of states Kbit register can represent one of a finite number (2 K ) of unique states An initial state (in register) is assigned based on reset input at the (rising or falling) edge of clock The next state may change depending on the current state as the next input comes in Based on the current state (and input), output is determined via combinational logic n 45 FSM uick Example Vending machine You are asked to design a vending machine to sell cokes. Suppose that a coke costs 3TL The machine takes only TL coins How would you design a logic with inputs and output? reset TL State TL State State 3 / coke out State 2 TL n 46 n 23
24 n 2/24/3 Finite State Machine (FSM) FSM is composed of State register Stores the current state Loads the next state at the clock edge Combinational logic Computes the next state based on current state and input Computes the outputs based on current state (and input) Inputs Next State Logic C L Current State Next State S S Next State Current State Current State Output Logic C L Outputs Outputs This slide is the Moore FSM example n 47 Finite State Machines (FSMs) Next state is determined by the current state and the inputs Two types of FSMs differ in the output logic Moore FSM: outputs depend only on the current state Mealy FSM: outputs depend on the current state and inputs Moore FSM inputs M next state logic k next state k state output logic N outputs Mealy FSM inputs M next state logic k next state k state output logic N outputs n 48 n 24
25 n 2/24/3 Moore and Mealy Edward F. Moore, Together with Mealy, developed automata theory, the mathematical underpinnings of state machines, at Bell Labs. Not to be confused with Intel founder Gordon Moore Published a seminal article, Gedankenexperiments on Sequential Machines in 956 George H. Mealy Published A Method of Synthesizing Sequential Circuits in 955 Wrote the first Bell Labs operating system for the IBM 74 computer n 49 Finite State Machine Example Let s design a simplified traffic light controller Traffic sensors (sensing human traffic): T A, T B Each sensor becomes TRUE if students are present Each sensor becomes FALSE if students are NOT present (i.e., the street is empty) Lights: L A, L B Each light receives digital inputs specifying whether it should be green, yellow, or red Academic Labs L A T A Bravado Blvd. T B T B Dining Hall L B L A T A L B Fields Ave. Dorms T A T B Inputs: clk, Reset, T A, T B Outputs: L A, L B Traffic Light Controller Reset L A L B n 5 n 25
26 n 2/24/3 FSM State Transition Diagram Moore FSM Circles represent states Arcs represent transitions between states Outputs are labeled in each state Reset T A Academic Labs L A T A Bravado Blvd. T B T B Dining Hall L B T A L B L A Fields Ave. Dorms S L A : green L B : red L A : red L B : yellow T A S L A : yellow L B : red L A : red L B : green T B T B n 5 FSM State Transition Table Reset S L A : green L B : red T A TA S L A : yellow L B : red Current State Inputs Next State S T A T B S' S X S S X S S X X L A : red L B : yellow T B T B L A : red L B : green X X X X S n 52 n 26
27 n 2/24/3 FSM Encoded State Transition Table Current State Inputs Next State State Encoding S S S S T A T B S' S' X X X X X X X X S' = S S S' = S S T A + S S T B n 53 FSM Output Table Reset T A TA S L A : green L B : red S L A : yellow L B : red Current State Outputs S S L A L A L B L B L A : red L B : yellow T B T B L A : red L B : green Output Encoding green yellow red L A = S L = S B L A = S S L B = S S n 54 n 27
28 n 2/24/3 FSM Schematic: State Register S' S S' r Reset S state register n 55 FSM Schematic: Next State Logic S' S T A T B S S S' r Reset S inputs next state logic state register S' = S S S' = S S T A + S S T B n 56 n 28
29 n 2/24/3 FSM Schematic: Output Logic L A S' S L A T A S' r S L B T B Reset S S L B inputs next state logic state register output logic outputs L A = S L A = S S L B = S L B = S S n 57 FSM Timing Diagram Reset S L A : green L B : red T A TA S L A : yellow L B : red L A : red L B : yellow T B T B L A : red L B : green Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle Reset T A T B n next state n current state S' : S : L A:?????? S () S () () () S () S () S () S () () () S () Green () Yellow () Red () Green () L B:?? Red () Green () Yellow () Red () t (sec) n 58 n 29
30 n 2/24/3 FSM State Encoding In the previous example, the state and output encodings were selected arbitrarily Different choice would have resulted in a different circuit Commonly used encoding methods Binary encoding Each state is represented as a binary number For example, to represent four states, we need 2 bits (,,, ) Onehot encoding A separate bit is used for each state Only one bit is HIGH at once (onehot) For example, to represent four states, we need 4 bits (,,, ) So, it requires more flipflops But, it often results in simpler next state and output logic n 59 Moore vs. Mealy FSM Two types of FSMs differ in the output logic Moore FSM: outputs depend only on the current state Mealy FSM: outputs depend on the current state and the inputs Moore FSM inputs M next state logic k next state k state output logic N outputs Mealy FSM inputs M next state logic k next state k state output logic N outputs n 6 n 3
31 n 2/24/3 Snail Example There is a snail The snail crawls down a paper tape with s and s on it The snail smiles whenever the last four numbers it has crawled over are Design Moore and Mealy FSMs of the snail s brain n 6 State Transition Diagrams () Moore FSM: arcs indicate input reset S S S4 Mealy FSM: arcs indicate input/output / reset / / / S / / S / n 62 / n 3
32 n 2/24/3 Moore FSM State Transition Table Current State Inputs Next State S A S' Moore FSM S S S S reset S S S S S4 S S S4 S4 S S4 n 63 Moore FSM State Transition Table reset Moore FSM S S S4 Current State Inputs Next State S 2 S S A S' 2 S' S' State Encoding S S S4 S' 2 = S S A S' = S S A + S S + S 2 A S' = S 2 S S A + S S A n 64 n 32
33 n 2/24/3 Moore FSM Output Table reset Moore FSM S S S4 S S S4 Current State Output S 2 S S Y Y = S 2 n 65 Moore FSM Schematic S' 2 = S S A S' = S S A + S S + S 2 A S' = S 2 S S A + S S A A S' 2 S 2 Y S' S Y = S 2 S' S Reset S S 2 S n 66 n 33
34 n 2/24/3 Mealy FSM State Transition and Output Table Mealy FSM / reset / / / S S / / / / Current State Inputs Next State Output S A S' Y S S S S S S S S S n 67 Mealy FSM State Transition and Output Table Mealy FSM / reset / / / S S / / / / State Encoding S S S' = S S + S S A S' = S S A + S S A + S S A Y = S S A Current State Input Next State Output S S A S' S' Y n 68 n 34
35 n 2/24/3 Mealy FSM Schematic A S' S Y S' = S S + S S A S' = S S A + S S A + S S A Y = S S A S' Reset S S S n 69 Moore and Mealy Timing Diagram Moore FSM Mealy FSM reset reset / / / / S S S4 S S / / / / Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle Reset A S Y S Moore Machine?? S S S4 S4 S Mealy Machine?? S S S S S Y n 7 n 35
36 n 2/24/3 Difference between Moore and Mealy A Moore machine typically has more states than a Mealy machine for a given problem A Mealy machine s output rises a cycle sooner because it responds to the input rather than waiting for the state change When choosing your FSM design style, consider when you want your outputs to respond n 7 Identify inputs and outputs FSM Design Procedure Sketch a state transition diagram Write a state transition table Select state encodings For a Moore machine Rewrite the state transition table with the state encodings Write the output table For a Mealy machine Rewrite the combined state transition table and output table with the state encodings Write Boolean equations for the next state and output logic Sketch the circuit schematic n 72 n 36
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