Sequential Logic. SR Latch

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Sequential Logic. SR Latch"

Transcription

1 n 2/24/3 Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly remember certain previous inputs, or it might distill (encode) the prior inputs into a smaller amount of information called state The state is a set of bits that contain all the information about the past necessary to determine the future behavior of the circuit State elements Bistable circuit SR Latch D Latch D Flip-flop n SR Latch One of the simplest sequential circuits is the SR (Set/ Reset) latch It is composed of 2 cross-coupled NOR gates It has 2 inputs (S, R) and 2 outputs ( and ) When the set input (S) is (and R = ), is set to Set makes the output () to When the reset input (R) is (and S = ), is reset to Reset makes the output () to R N SR Latch Symbol R S N2 S n 2 n

2 n 2/24/3 SR Latch Analysis Consider the four possible cases: a) S =, R = b) S =, R = c) S =, R = d) S =, R = n 3 SR Latch Analysis a) S =, R = : then = and = R N S N2 b) S =, R = : then = and = R N S N2 n 4 n 2

3 n 2/24/3 SR Latch Analysis c) S =, R = : then = prev and = prev We got Memory! prev = prev = R N R N N2 S S N2 d) S =, R = : then = and = Invalid state: NOT R S N N2 n 5 SR Latch Recap SR latch stores one bit of state Where is it stored? SR latch can control the state with S and R inputs SR latch generates the invalid state when S = and R = n 6 n 3

4 n 2/24/3 D Latch D latch solves the problem of the SR latch D latch blocks the invalid state when S = and R = D latch separates when and what the state should be changed D latch has 2 inputs (, D) and 2 outputs (, ) controls when the output changes D (data input) controls what the output changes to Avoids invalid case ( NOT when both S and R are ) D Latch Symbol D n 7 D Latch Internal & Operation D latch operation When =, D passes through to (D latch is transparent) When =, holds its previous value (D latch is opaque) D D R S R S D D X D S R X prev prev prev prev n 8 n 4

5 n 2/24/3 D Latch Waveform When evaluating latch, it would be confusing if you think previous and current value things For good intuition, think with waveform When =, D latch transfers input data (D) to output () When =, D latch maintains its previous value n 9 D Flip-Flop In digital logic design, it is very convenient if we can store input data at a certain moment (not during the whole time interval like D latch) D flip-flop provides that functionality changes only on the rising edge of When rises from to, D passes through to Otherwise, holds its previous value Thus, a flip-flop is called an edge-triggered device because it is activated on the clock edge D Flip-Flop Symbols D n n 5

6 n 2/24/3 D Flip-Flop Internal Circuit Two back-to-back latches (L and L2) controlled by complementary clocks When = L is transparent L2 is opaque D passes through to N When = L2 is transparent L is opaque N passes through to D D L N D L2 Thus, on the edge of the clock (when rises from to ) D effectively passes through to n D Flip-Flop Note that input data should not be changed around the clock edge for D flip-flop to work correctly D D L N D L2 n 2 n 6

7 n 2/24/3 D Flip-Flop So, D flip-flop has the effect of sampling the current input data at the rising edge of the clock Note again that input data should not be changed around the clock edge for D flip-flop to work correctly n 3 Registers An N-bit register is a set of N flip-flops that share a common input, so that all bits of the register are updated at the same time You can say N-bit flip-flops or N-bit register Registers are the key building block of sequential circuits D D D D D 3: 4 4 3: D 2 D 2 D 3 D 3 n 4 n 7

8 n 2/24/3 Enabled Flip-Flops Enabled flip-flips are useful when we wish to load a new value into a flip-flop only during some of the time, rather than on every clock edge Enabled flip-flop has one more input (EN) The enable input (EN) controls when new data (D) is stored When EN =, D passes through to on the clock edge When EN =, the flip-flop retains its previous state Internal Circuit Symbol EN D D D EN n 5 Resettable Flip-Flops Resettable flip-flops are useful when we want to force a known state (i.e., ) into some flip-flops in a system when we first turn it on Resettable flip-flop has Reset input When Reset is active, is reset to When Reset is deactivated, the flip-flop behaves like an ordinary D flip-flop Resettable flip-flop D Reset Symbols r There are two types of resettable flipflops Synchronous resettable FF resets at the clock edge only Asynchronous resettable FF resets immediately when Reset is active Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop Synchronously resettable flipflop D Reset Internal Circuit D n 6 n 8

9 n 2/24/3 Settable Flip-Flops Settable flip-flops are also useful when we want to force a known state (i.e., ) into some flip-flops in a system when we first turn it on Settable flip-flop has Set input When Set is active, is set to When Set is deactivated, the flip-flop behaves like an ordinary D flip-flop They comes in two flavors: Synchronous settable and Asynchronous settable Symbols D Set s n 7 Registers n- A register is a group of flip-flops. An n-bit register is made of n flip-flips and can store n bits A register may have additional combinational gates to perform certain operations n 9

10 n 2/24/3 4-Bit Register A simple 4-bit register can be made with 4 D-FF Data is loaded in parallel Common Clock At each positive-edge, 4 bits are loaded in parallel Previous data is overwritten Entering data is called loading Common Clear Asynchronous active-low clear When Clear =, all FFs are cleared; i.e. is stored. 4-Bit Register (cont.) uestion: How to modify this register to enable/disable loading new data (overwriting previous)? n

11 n 2/24/3 4-Bit Register (cont.) uestion: How to modify this register to enable/disable loading new data (overwriting previous)? Answer: When Load=, the clock input to the FFs will never take a transition ( to, to ), no new data will be loaded. When Load=, normal data loading takes place This is called clock gating 4-Bit Register (cont.) Clock Skew Problem: It results from clock gating. n

12 n 2/24/3 4-Bit Register (cont.) Better Solution: Register with Parallel Load Use a 2x MUX as shown: n : Why a D-FF output is feedback? 4-Bit Register (cont.) A 4-bit Parallel Load Register When Load =, the data is not changed (no loading) When Load =, the data is loaded in parallel at the rising edge (+ve) n load n clock n 2

13 n 2/24/3 Shift Registers n- A shift register is a register which shifts its content (right, left, or both) Made of flip-flops with common clock Useful to load data serially 4-bit Shift Register A simple 4-bit shift register can be made with 4 D-FF Common Clock At each positive-edge, bit is shifted in Rightmost bit is discarded Which direction this register is shifting? n 3

14 n 2/24/3 Using Shift Register (Examples) Serial Addition Shift Register with Parallel Load Two control inputs (shift, load) Each stage consists of D-FF OR gate Three AND gates AND to enable shift AND to enable load AND for no change Idea: Use a MUX to implement more functions (see next slides) i à i D D D 2 D 3 n Serial Input à n i- à i ; i=,,3 n 4

15 n 2/24/3 Universal Shift Register uestion: Design a Universal Shift Register with the following capabilities: A clear control to clear the register to A clock to synchronize the operations A shift-right control (associated with serial in/out) A shift-left control (associated with serial in/out) A parallel-load control (to parallel load n bits) n-parallel output lines A control signal to leave register unchanged Universal Shift Register (cont.) n 5

16 n 2/24/3 Universal Shift Register (cont.) How does it work? 4 D-FF and 4 MUXs with selection S,S S S =, FF output is feedback to its input S S =, FF input comes from left FF or serial-in (shift-right) S S =, FF input comes from right FF or serial-in (shift-left) S S =, parallel data transferred in Applications: Parallel Serial conversions Arithmetic multiplication/division Delaying input sequence Counters Counter: A register (sequential circuit) that goes through a predetermined sequence of states upon the application of input (clock or other source) pulses Binary Counter: The sequence of the states follows the binary number sequence (e.g. à à à à etc.) n-bit binary counter requires n flip-flops counts from to 2 n - Sequences can be binary, BCD, random, etc. Counting can be up, down A modulo-n counter goes through values,,2,, (n-) e.g. modulo- up counter counts:,, 9 Two Types of Counters: Ripple counter (asynchronous): Flip-flop output transition serves as source for triggering the other flip-flops Synchronous counter: common clock for all flip-flops (same design procedure) n 6

17 n 2/24/3 Ripple Counters Instead of having a common clock signal to all Flip Flops, in a Ripple counter the output of one stage (Flip Flop) is connected to the clock input of the next stage T or JK flip flops are used for this construction because of their capability to flip their stored bits (J=K=T=) Clock is connected to the least significant bit Flip flops are negative edge-triggered (clock is bubbled) are active when the clock signal is falling (high to low) Flip flops invert their stored bits, when the input clock signal goes from high () to low () n clock pulses n Logic n clear n J n C n n n K n R n J n C n n n K n R n J n C n n n K n R n J n C n n n K n R n n n 2 n 3 Ripple Counters (cont.) 3 2 n clock pulses n J n C n n n K n R n n. n. n. n. n. n. n. n. n J n C n n n K n R n J n C n n n 2 n : How to make it count down? n 2: What if we use positive-edge FF? n 3: What if we use instead of? n 4: Is this counter asynchronous? Why? n Logic n clear n n K n R n J n C n n n K n R n 3 n 7

18 n 2/24/3 Ripple Counters with T-FF/D-FF Alternative implementation of a 4-bit ripple counter using T-FF and D-FF For a D-FF, connecting to D makes it to toggle at each clock! n Src: Mano s Textbook Ripple Counters Advantages: Simple hardware Disadvantages: Asynchronous delay dependent Good for low power circuits n 8

19 n 2/24/3 Synchronous Counters Common clock to all FFs Design following the same design procedure for synchronous sequential circuits (see slides 4_3) Important: Study the examples in slides 4_3 Counters have a regular pattern Alternatively, counters can be designed without following the procedure (algorithmically, hierarchically) 4-bit Synchronous Binary Counter When EN = à No change When EN = Least significant bit (A ) toggles at every clock Other FFs toggle when all lower FFs are equal to (e.g. à ) uestion: What will happen if we use a negative edge triggered FF? n Building Bigger Counter n Clock n A n A n A n A n En n A 2 n A 3 n CO n En n A 2 n A 3 n CO n CO n 9

20 n 2/24/3 4-bit Synchronous Binary Counter with D-FF When En =, feed back same value When En =, increment the saved value at each clock n Increment er n + n A3 n Y3 n A2 n Y2 n A n Y n A n Y n D3 n 3 n D2 n 2 n D n n D n n symbol XORs act like an adder EN = à EN = à Tip: XOR + D-FF = T-FF Arbitrary Count Sequence Problem: Design a counter that has a repeated sequence of 6 states, as listed in table. In this sequence, flip-flops B and C repeat the binary count,,, while flip-flop A alternates between and every three counts. n Notes: Only 6 states (Module-6), are missing Follow the usual design procedure Present State Next State A B C A B C n 2

21 n 2/24/3 Arbitrary Count Sequence State Table Assuming JK flip-flops Present State Next State Flip-flop Inputs A B C A B C JA KA JB KB JC KC X X X X X X X X X X X X X X X X x x Arbitrary Count Sequence Input Equations BC A x x x x x n JA = B BC A x x x x n JB = C BC A x x x x n JC = B BC A x x x x x n KA = B BC A x x x x x x n KB = BC A x x x x x x n KC = n 2

22 n 2/24/3 n Arbitrary Count Sequence Unused States n Logic n JA = B n JB = C n JC = B n clock n KA = B n KB = n KC = n J A n A n C n K n A A n J B n B n C n K n B B n J C n C n C n K n C C n n n n n n n n n ) What if the counter finds itself in state or state? Will the counter be able to proceed (count) normally afterward? How? n 2) Is this circuit safe or reliable? Summary Registers and Counters are versatile sequential circuits Registers Parallel Load Registers Shift Registers Universal Shift Registers Counters Ripple counters Synchronous counters n 22

23 n 2/24/3 Finite State Machine (FSM) Finite state machine (FSM) is composed of 2 components: registers and combinational logic Register represents one of the finite number of states K-bit register can represent one of a finite number (2 K ) of unique states An initial state (in register) is assigned based on reset input at the (rising or falling) edge of clock The next state may change depending on the current state as the next input comes in Based on the current state (and input), output is determined via combinational logic n 45 FSM uick Example Vending machine You are asked to design a vending machine to sell cokes. Suppose that a coke costs 3TL The machine takes only TL coins How would you design a logic with inputs and output? reset TL State TL State State 3 / coke out State 2 TL n 46 n 23

24 n 2/24/3 Finite State Machine (FSM) FSM is composed of State register Stores the current state Loads the next state at the clock edge Combinational logic Computes the next state based on current state and input Computes the outputs based on current state (and input) Inputs Next State Logic C L Current State Next State S S Next State Current State Current State Output Logic C L Outputs Outputs This slide is the Moore FSM example n 47 Finite State Machines (FSMs) Next state is determined by the current state and the inputs Two types of FSMs differ in the output logic Moore FSM: outputs depend only on the current state Mealy FSM: outputs depend on the current state and inputs Moore FSM inputs M next state logic k next state k state output logic N outputs Mealy FSM inputs M next state logic k next state k state output logic N outputs n 48 n 24

25 n 2/24/3 Moore and Mealy Edward F. Moore, Together with Mealy, developed automata theory, the mathematical underpinnings of state machines, at Bell Labs. Not to be confused with Intel founder Gordon Moore Published a seminal article, Gedanken-experiments on Sequential Machines in 956 George H. Mealy Published A Method of Synthesizing Sequential Circuits in 955 Wrote the first Bell Labs operating system for the IBM 74 computer n 49 Finite State Machine Example Let s design a simplified traffic light controller Traffic sensors (sensing human traffic): T A, T B Each sensor becomes TRUE if students are present Each sensor becomes FALSE if students are NOT present (i.e., the street is empty) Lights: L A, L B Each light receives digital inputs specifying whether it should be green, yellow, or red Academic Labs L A T A Bravado Blvd. T B T B Dining Hall L B L A T A L B Fields Ave. Dorms T A T B Inputs: clk, Reset, T A, T B Outputs: L A, L B Traffic Light Controller Reset L A L B n 5 n 25

26 n 2/24/3 FSM State Transition Diagram Moore FSM Circles represent states Arcs represent transitions between states Outputs are labeled in each state Reset T A Academic Labs L A T A Bravado Blvd. T B T B Dining Hall L B T A L B L A Fields Ave. Dorms S L A : green L B : red L A : red L B : yellow T A S L A : yellow L B : red L A : red L B : green T B T B n 5 FSM State Transition Table Reset S L A : green L B : red T A TA S L A : yellow L B : red Current State Inputs Next State S T A T B S' S X S S X S S X X L A : red L B : yellow T B T B L A : red L B : green X X X X S n 52 n 26

27 n 2/24/3 FSM Encoded State Transition Table Current State Inputs Next State State Encoding S S S S T A T B S' S' X X X X X X X X S' = S S S' = S S T A + S S T B n 53 FSM Output Table Reset T A TA S L A : green L B : red S L A : yellow L B : red Current State Outputs S S L A L A L B L B L A : red L B : yellow T B T B L A : red L B : green Output Encoding green yellow red L A = S L = S B L A = S S L B = S S n 54 n 27

28 n 2/24/3 FSM Schematic: State Register S' S S' r Reset S state register n 55 FSM Schematic: Next State Logic S' S T A T B S S S' r Reset S inputs next state logic state register S' = S S S' = S S T A + S S T B n 56 n 28

29 n 2/24/3 FSM Schematic: Output Logic L A S' S L A T A S' r S L B T B Reset S S L B inputs next state logic state register output logic outputs L A = S L A = S S L B = S L B = S S n 57 FSM Timing Diagram Reset S L A : green L B : red T A TA S L A : yellow L B : red L A : red L B : yellow T B T B L A : red L B : green Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle Reset T A T B n next state n current state S' : S : L A:?????? S () S () () () S () S () S () S () () () S () Green () Yellow () Red () Green () L B:?? Red () Green () Yellow () Red () t (sec) n 58 n 29

30 n 2/24/3 FSM State Encoding In the previous example, the state and output encodings were selected arbitrarily Different choice would have resulted in a different circuit Commonly used encoding methods Binary encoding Each state is represented as a binary number For example, to represent four states, we need 2 bits (,,, ) One-hot encoding A separate bit is used for each state Only one bit is HIGH at once (one-hot) For example, to represent four states, we need 4 bits (,,, ) So, it requires more flip-flops But, it often results in simpler next state and output logic n 59 Moore vs. Mealy FSM Two types of FSMs differ in the output logic Moore FSM: outputs depend only on the current state Mealy FSM: outputs depend on the current state and the inputs Moore FSM inputs M next state logic k next state k state output logic N outputs Mealy FSM inputs M next state logic k next state k state output logic N outputs n 6 n 3

31 n 2/24/3 Snail Example There is a snail The snail crawls down a paper tape with s and s on it The snail smiles whenever the last four numbers it has crawled over are Design Moore and Mealy FSMs of the snail s brain n 6 State Transition Diagrams () Moore FSM: arcs indicate input reset S S S4 Mealy FSM: arcs indicate input/output / reset / / / S / / S / n 62 / n 3

32 n 2/24/3 Moore FSM State Transition Table Current State Inputs Next State S A S' Moore FSM S S S S reset S S S S S4 S S S4 S4 S S4 n 63 Moore FSM State Transition Table reset Moore FSM S S S4 Current State Inputs Next State S 2 S S A S' 2 S' S' State Encoding S S S4 S' 2 = S S A S' = S S A + S S + S 2 A S' = S 2 S S A + S S A n 64 n 32

33 n 2/24/3 Moore FSM Output Table reset Moore FSM S S S4 S S S4 Current State Output S 2 S S Y Y = S 2 n 65 Moore FSM Schematic S' 2 = S S A S' = S S A + S S + S 2 A S' = S 2 S S A + S S A A S' 2 S 2 Y S' S Y = S 2 S' S Reset S S 2 S n 66 n 33

34 n 2/24/3 Mealy FSM State Transition and Output Table Mealy FSM / reset / / / S S / / / / Current State Inputs Next State Output S A S' Y S S S S S S S S S n 67 Mealy FSM State Transition and Output Table Mealy FSM / reset / / / S S / / / / State Encoding S S S' = S S + S S A S' = S S A + S S A + S S A Y = S S A Current State Input Next State Output S S A S' S' Y n 68 n 34

35 n 2/24/3 Mealy FSM Schematic A S' S Y S' = S S + S S A S' = S S A + S S A + S S A Y = S S A S' Reset S S S n 69 Moore and Mealy Timing Diagram Moore FSM Mealy FSM reset reset / / / / S S S4 S S / / / / Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle Reset A S Y S Moore Machine?? S S S4 S4 S Mealy Machine?? S S S S S Y n 7 n 35

36 n 2/24/3 Difference between Moore and Mealy A Moore machine typically has more states than a Mealy machine for a given problem A Mealy machine s output rises a cycle sooner because it responds to the input rather than waiting for the state change When choosing your FSM design style, consider when you want your outputs to respond n 7 Identify inputs and outputs FSM Design Procedure Sketch a state transition diagram Write a state transition table Select state encodings For a Moore machine Rewrite the state transition table with the state encodings Write the output table For a Mealy machine Rewrite the combined state transition table and output table with the state encodings Write Boolean equations for the next state and output logic Sketch the circuit schematic n 72 n 36

Lecture 10. Latches and Flip-Flops

Lecture 10. Latches and Flip-Flops Logic Design Lecture. Latches and Flip-Flops Prof. Hyung Chul Park & Seung Eun Lee Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly

More information

Logic Design. Flip Flops, Registers and Counters

Logic Design. Flip Flops, Registers and Counters Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and

More information

Overview. Ripple Counter Synchronous Binary Counters

Overview. Ripple Counter Synchronous Binary Counters Counters Overview Ripple Counter Synchronous Binary Counters Design with D Flip-Flops Design with J-K Flip-Flops Serial Vs. Parallel Counters Up-down Binary Counter Binary Counter with Parallel Load BCD

More information

Tutorial 1: Chapter 1

Tutorial 1: Chapter 1 Tutorial 1: hapter 1 1. Figure 1.1 shows the positive edge triggered D flip flop, determine the output of Q 0, assume output is initially LOW. Figure 1.1 2. For the positive edge-triggered J-K flip-flop

More information

Analysis of Clocked (Synchronous) Sequential Circuits

Analysis of Clocked (Synchronous) Sequential Circuits Analysis of Clocked (Synchronous) Sequential Circuits Now that we have flip-flops and the concept of memory in our circuit, we might want to determine what a circuit is doing. The behavior of a clocked

More information

Sequential Circuits. Chapter 4 S. Dandamudi

Sequential Circuits. Chapter 4 S. Dandamudi Sequential Circuits Chapter 4 S. Dandamudi Outline Introduction Clock signal Propagation delay Latches SR latch Clocked SR latch D latch JK latch Flip flops D flip flop JK flip flop Example chips Example

More information

CS 226: Digital Logic Design

CS 226: Digital Logic Design CS 226: Digital Logic Design 0 1 1 I S 0 1 0 S Department of Computer Science and Engineering, Indian Institute of Technology Bombay. 1 of 44 Objectives In this lecture we will introduce: 1. Synchronous

More information

Latches and flip-flops

Latches and flip-flops CSE4: Components and Design Techniques for Digital Systems Latches and flip-flops Tajana Simunic osing Sources: Where we are now What we ve covered so far Combinational circuits: Chap,2 HW#5 out What comes

More information

Module-3 SEQUENTIAL LOGIC CIRCUITS

Module-3 SEQUENTIAL LOGIC CIRCUITS Module-3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.

More information

In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current

In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current Module 12 In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the current inputs. The following topics will be on sequential

More information

Chapter 3. Sequential Logic Design. Copyright 2013 Elsevier Inc. All rights reserved.

Chapter 3. Sequential Logic Design. Copyright 2013 Elsevier Inc. All rights reserved. Chapter 3 Sequential Logic Design 1 Figure 3.1 Cross-coupled inverter pair 2 Figure 3.2 Bistable operation of cross-coupled inverters 3 Figure 3.3 SR latch schematic 4 Figure 3.4 Bistable states of SR

More information

Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here

Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here Sequential Logic Output depends on sequence of previous inputs Sequence of previous this is history History is a state that captures how you got here " E.g., 35 cents vending = cents + cents + cents +

More information

Digital Logic Design Sequential circuits

Digital Logic Design Sequential circuits Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register

More information

Digital Design, Kyung Hee Univ. Spring, Chapter 5. Synchronous Sequential Logic

Digital Design, Kyung Hee Univ. Spring, Chapter 5. Synchronous Sequential Logic Chapter 5. Synchronous Sequential Logic 1 5.1 Introduction Electronic products: ability to send, receive, store, retrieve, and process information in binary format Dependence on past values of inputs Sequential

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

More information

Introduction to Logic Design with VHDL

Introduction to Logic Design with VHDL EECE 379 : DESIGN OF DIGITAL AND MICROCOMPUTER SYSTEMS 2000/2001 WINTER SESSION, TERM 1 Introduction to Logic Design with VHDL This chapter reviews the design of combinational and sequential logic and

More information

Synchronous Sequential Logic

Synchronous Sequential Logic Chapter 5 Synchronous Sequential Logic 5- Outline! Sequential Circuits! Latches! Flip-Flops! Analysis of Clocked Sequential Circuits! State Reduction and Assignment! Design Procedure 5-2 Sequential Circuits!

More information

Module 3: Floyd, Digital Fundamental

Module 3: Floyd, Digital Fundamental Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental

More information

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1 WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits

More information

Applications of Edge-Triggered D Flip-flop

Applications of Edge-Triggered D Flip-flop Applications of Edge-Triggered D Flip-flop 1. Data Storage using D-flip-flop A Multiplexer based Parallel-to-Serial converter needs to have stable parallel data at its inputs as it converts it to serial

More information

Combinational and Sequential Circuits.

Combinational and Sequential Circuits. Combinational and Sequential Circuits. Basically, sequential circuits have memory and combinational circuits do not. Here is a basic depiction of a sequential circuit. All sequential circuits contain combinational

More information

Chapter 5 Synchronous Sequential Logic 5-1 Sequential Circuits

Chapter 5 Synchronous Sequential Logic 5-1 Sequential Circuits Chapter 5 Synchronous Sequential Logic 5-1 Sequential Circuits Every digital system is likely to have combinational circuits, most systems encountered in practice also include storage elements, which require

More information

EE 110 Practice Problems for Final Exam: Solutions

EE 110 Practice Problems for Final Exam: Solutions EE 1 Practice Problems for Final Exam: Solutions 1. Finite State Machines: Sequence Recognizer You want to build a finite state machine that will recognize the sequence x = and output the sequence z =

More information

Counters & Shift Registers Chapter 8 of R.P Jain

Counters & Shift Registers Chapter 8 of R.P Jain Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with and without

More information

Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

More information

Lecture 8: Flip-flops

Lecture 8: Flip-flops Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 8: Flip-flops Professor Peter Cheung Department of EEE, Imperial

More information

Flip-Flops. Revision of lecture notes written by Dr. Timothy Drysdale

Flip-Flops. Revision of lecture notes written by Dr. Timothy Drysdale Flip-Flops Revision of lecture notes written by Dr. Timothy Drysdale Objectives of Lecture The objectives of this lecture are: to discuss the difference between combinational and sequential logic as well

More information

V. Sequential network design State-machine structure (Mealy) output depends on state and input. typically edge-triggered D flip-flops

V. Sequential network design State-machine structure (Mealy) output depends on state and input. typically edge-triggered D flip-flops V. Sequential network design State-machine structure (Mealy) output depends on state and input typically edge-triggered D flip-flops V. Sequential network design State-machine structure (Moore) output

More information

Latches and Flip-flops

Latches and Flip-flops Latches and Flip-flops Latches and flip-flops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0

More information

Mealy and Moore Machines. ECE 152A Winter 2012

Mealy and Moore Machines. ECE 152A Winter 2012 Mealy and Moore Machines ECE 52A Winter 202 Reading Assignment Brown and Vranesic 8 Synchronous Sequential Circuits 8.3 Mealy State Model February 22, 202 ECE 52A - Digital Design Principles 2 Reading

More information

Counters In this lesson, the operation and design of Synchronous Binary Counters will be studied.

Counters In this lesson, the operation and design of Synchronous Binary Counters will be studied. Counters In this lesson, the operation and design of Synchronous Binary Counters will be studied. Synchronous Binary Counters (SBC) Description and Operation In its simplest form, a synchronous binary

More information

Lecture 9: Flip-flops

Lecture 9: Flip-flops Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 9: Flip-flops Professor Peter Cheung Department of EEE, Imperial

More information

Chapter 5: Sequential Circuits (LATCHES)

Chapter 5: Sequential Circuits (LATCHES) Chapter 5: Sequential Circuits (LATCHES) Latches We focuses on sequential circuits, where we add memory to the hardware that we ve already seen Our schedule will be very similar to before: We first show

More information

EE 110 Practice Problems for Exam 2: Solutions, Fall 2008

EE 110 Practice Problems for Exam 2: Solutions, Fall 2008 EE 110 Practice Problems for Exam 2: Solutions, Fall 2008 1. Circle T (true) or F (false) for each of these Boolean equations. (a). T FO An 8-to-1 multiplexer requires 2 select lines. (An 8-to-1 multiplexer

More information

Basic bistable element. Chapter 6. Latches vs. flip-flops. Flip-flops

Basic bistable element. Chapter 6. Latches vs. flip-flops. Flip-flops Basic bistable element hapter 6 It is a circuit having two stable conditions (states). It can be used to store binary symbols. Flip-Flops and Simple Flip-Flop Applications.. Huang, 24 igital Logic esign

More information

Latches and Flip-flops

Latches and Flip-flops Latches and Flip-flops Latches and flip-flops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0

More information

Mealy and Moore Type Finite State Machines

Mealy and Moore Type Finite State Machines Mealy and Moore Type Finite State Machines Objectives There are two basic ways to design clocked sequential circuits. These are using: 1. Mealy Machine, which we have seen so far. 2. Moore Machine. The

More information

Sequential Logic Implementation

Sequential Logic Implementation Sequential Logic Implementation Models for representing sequential circuits Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous

More information

Synchronous Sequential Logic

Synchronous Sequential Logic Synchronous Sequential Logic Ranga Rodrigo August 6, 2009 State Diagram The information available in a state table can be represented algebraically in the form of a state diagram. In this type of a diagram,

More information

Figure 2.4(f): A T flip flop

Figure 2.4(f): A T flip flop If the T input is in 0 state (i.e., J = K = 0) prior to a clock pulse, the Q output will not change with the clock pulse. On the other hand, if the T input is in 1 state (i.e., J = K = 1) prior to a clock

More information

Counters and Decoders

Counters and Decoders Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

More information

Lesson 12 Sequential Circuits: Flip-Flops

Lesson 12 Sequential Circuits: Flip-Flops Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability

More information

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation

More information

Figure 2.1(a) Bistable element circuit.

Figure 2.1(a) Bistable element circuit. 3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),

More information

Design of Digital Systems II Sequential Logic Design Principles (1)

Design of Digital Systems II Sequential Logic Design Principles (1) Design of Digital Systems II Sequential Logic Design Principles (1) Moslem Amiri, Václav Přenosil Masaryk University Resource: Digital Design: Principles & Practices by John F. Wakerly Introduction Logic

More information

Chapter 12. Algorithmic State Machine

Chapter 12. Algorithmic State Machine Chapter 12 Algorithmic State Machine 12.0 Introduction In Chapter 10, we introduced two models of synchronous sequential network, which are Mealy and Moore machines. In this chapter, we would like to introduce

More information

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction

More information

Chapter 8. Sequential Circuits for Registers and Counters

Chapter 8. Sequential Circuits for Registers and Counters Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters T-FF Basic Counting element State

More information

Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops ESD I Lecture 3.b Sequential Circuits: Latches & Flip-Flops 1 Outline Memory elements Latch SR latch D latch Flip-Flop SR flip-flop D flip-flop JK flip-flop T flip-flop 2 Introduction A sequential circuit

More information

Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann

Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7- Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users

More information

Lecture 7: Sequential Networks

Lecture 7: Sequential Networks Lecture 7: Sequential Networks CSE 14: Components and Design Techniques for Digital Systems Fall 214 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1 What is a sequential

More information

Final Exam review: chapter 4 and 5. Supplement 3 and 4

Final Exam review: chapter 4 and 5. Supplement 3 and 4 Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much

More information

Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS

Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS Introduction : Logic circuit is divided into two types. 1. Combinational Logic Circuit 2. Sequential Logic Circuit Definition : 1. Combinational

More information

ECE 331 Digital System Design

ECE 331 Digital System Design ECE 331 Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #21) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,

More information

Memory Elements. Combinational logic cannot remember

Memory Elements. Combinational logic cannot remember Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic

More information

Edge-Triggered D-type Flip-flop

Edge-Triggered D-type Flip-flop Edge-Triggered D-type Flip-flop The transparent D-type flip-flop is written during the period of time that the write control is active. However there is a demand in many circuits for a storage device (flip-flop

More information

Latches and Flip-Flops

Latches and Flip-Flops Latches and Flip-Flops Introduction to sequential logic Latches SR Latch Gated SR Latch Gated Latch Flip-Flops JK Flip-flop Flip-flop T Flip-flop JK Master-Slave Flip-flop Preset and Clear functions 7474

More information

REGISTERS. Consists of a set of flip-flops (each flip-flop stores one bit of information)

REGISTERS. Consists of a set of flip-flops (each flip-flop stores one bit of information) REGISTERS Sequential circuit used to store binary word Consists of a set of flip-flops (each flip-flop stores one bit of information) External gates may be used to control the inputs of the flip-flops:

More information

SAMPLE OF THE STUDY MATERIAL PART OF CHAPTER 5. Combinational & Sequential Circuits

SAMPLE OF THE STUDY MATERIAL PART OF CHAPTER 5. Combinational & Sequential Circuits SAMPLE OF THE STUD MATERIAL PART OF CHAPTER 5 5. Introduction Digital circuits can be classified into two types: Combinational digital circuits and Sequential digital circuits. 5.2 Combinational Digital

More information

Synchronous Sequential Circuit Review

Synchronous Sequential Circuit Review Synchronous Sequential Circuit Review Steps 2 4/3/29 Page 3 Derivation of JK Excitation Table JK Characteristic Table JK Excitation Table J K Q Q+ Q+ Q J K 4/3/29 Page 4 Flip-Flop Excitation Tables Q+

More information

ECE 223 Digital Circuits and Systems. Synchronous Logic. M. Sachdev. Dept. of Electrical & Computer Engineering University of Waterloo

ECE 223 Digital Circuits and Systems. Synchronous Logic. M. Sachdev. Dept. of Electrical & Computer Engineering University of Waterloo ECE 223 Digital Circuits and Systems Synchronous Logic M. Sachdev Dept. of Electrical & Computer Engineering University of Waterloo Sequential Circuits Combinational circuits Output = f (present inputs)

More information

CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS

CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS CHAPTER IX-1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249-275 FROM MANO AN KIME CHAPTER IX-2 INTROUCTION -INTROUCTION Like combinational building blocks, we can also develop

More information

Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops Sequential Circuits: Latches & Flip-Flops Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc

More information

Experiment # 8 Latches And Flip Flops Characteristics

Experiment # 8 Latches And Flip Flops Characteristics Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 8 Latches And Flip Flops Characteristics

More information

Lecture 2. Introduction to Sequential Circuits

Lecture 2. Introduction to Sequential Circuits 2-1 Lecture 2 Introduction to Sequential Circuits 1 Youpyo Hong, ongguk University 2-2 igital Circuits Combinational circuits - Outputs are determined by current inputs only. - Memory is not included.

More information

Chapter #8: Finite State Machine Design Finite State Machine Design

Chapter #8: Finite State Machine Design Finite State Machine Design Contemporary Logic esign Finite State Machine esign Chapter #8: Finite State Machine esign 8. - 8.2 Finite State Machine esign R.H. Katz Transparency o. 4- Chapter Overview Concept of the State Machine

More information

Sequential Circuits Sequential circuits combinational circuits clocked sequential circuits gate delay

Sequential Circuits Sequential circuits combinational circuits clocked sequential circuits gate delay Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit

More information

Lecture 9: Flip-Flops, Registers, and Counters

Lecture 9: Flip-Flops, Registers, and Counters Lecture 9: Flip-Flops, Registers, and Counters 1. T Flip-Flops toggles its output on a rising edge, and otherwise keeps its present state. 1.1. Since the toggle from high to low to high takes two clock

More information

Sequential Circuits: Latches and Flip-Flops

Sequential Circuits: Latches and Flip-Flops Sequential Circuits: Latches and Flip-Flops Sequential circuits Output depends on current input and past sequence of input(s) How can we tell if the input is current or from the past? A clock pulse can

More information

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters: Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary

More information

CHAPTER 6 DESIGN OF SEQUENTIAL LOGIC CIRCUITS IN QCA

CHAPTER 6 DESIGN OF SEQUENTIAL LOGIC CIRCUITS IN QCA 6 CHAPTER 6 DESIGN OF SEQUENTIAL LOGIC CIRCUITS IN QCA 6. INTRODUCTION The logic circuits whose outputs at any instant of time depend not only on the present inputs but also on the past outputs are known

More information

Chapter 5. Sequential Logic

Chapter 5. Sequential Logic Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;

More information

CS311 Lecture: Sequential Circuits

CS311 Lecture: Sequential Circuits CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce

More information

Unit 3 Combinational MOS Logic Circuits

Unit 3 Combinational MOS Logic Circuits Unit 3 ombinational MOS Logic ircuits LATH Latch It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its input

More information

Flip-Flops, Registers, Counters, and a Simple Processor

Flip-Flops, Registers, Counters, and a Simple Processor June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number

More information

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

More information

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012 Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

Sequential Logic Design Principles.Clocked Synchronous State-Machine Analysis and Synthesis

Sequential Logic Design Principles.Clocked Synchronous State-Machine Analysis and Synthesis Sequential Logic Design Principles.Clocked Synchronous State-Machine Analysis and Synthesis Doru Todinca Department of Computers Politehnica University of Timisoara Outline Clocked Synchronous State-Machine

More information

Counter/shift-register model. State machine model (cont d) General state machine model

Counter/shift-register model. State machine model (cont d) General state machine model CSE 37 Spring 26 Introduction to igital esign Lecture 8: Moore and Mealy Machines Last Lecture Finite State Machines Today Moore and Mealy Machines Counter/shift-register model Values stored in registers

More information

7. Sequential Circuits - Combinational vs. Sequential Circuits - 7. Sequential Circuits - State (2) - 7. Sequential Circuits - State (1) -

7. Sequential Circuits - Combinational vs. Sequential Circuits - 7. Sequential Circuits - State (2) - 7. Sequential Circuits - State (1) - Sistemas Digitais I LESI - 2º ano Lesson 7 - Sequential Systems Principles Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática - Combinational vs. Sequential Circuits - Logic circuits are

More information

Basic Bit Memory: Latches and Flip Flops

Basic Bit Memory: Latches and Flip Flops Basic Bit Memory: Latches and Flip Flops Topics: 1. General description of bit memory, also called a memory cell. 2. Definition of sequential and combinational circuits. Memory devices are sequential devices.

More information

IE1204 Digital Design L8: Memory Elements: Latches and Flip-Flops. Counter

IE1204 Digital Design L8: Memory Elements: Latches and Flip-Flops. Counter IE1204 igital esign L8: Memory Elements: Latches and Flip-Flops. Counter Elena ubrova KTH / ICT / ES dubrova@kth.se This lecture BV pp. 383-418, 469-471 IE1204 igital esign, HT14 2 Sequential System a(t)

More information

Today. Sequential logic Latches Flip-flops Counters. Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic

Today. Sequential logic Latches Flip-flops Counters. Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic Today Sequential logic Latches Flip-flops Counters Time Until now: we have essentially ignored the issue of time We have assumed that our digital logic circuits perform their computations instantaneously

More information

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital

More information

ECE 301 Digital Electronics

ECE 301 Digital Electronics ECE 301 Digital Electronics Latches and Flip-Flops (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and

More information

1) For a RS flip flop constructed out of NAND gates complete the following table. R S Q Q\ State name Q Q\

1) For a RS flip flop constructed out of NAND gates complete the following table. R S Q Q\ State name Q Q\ Sequential logic tutorial Flip Flops 1) For a RS flip flop constructed out of NAND gates complete the following table R S Q Q\ State name 0 0 1 1 0 1 0 1 1 0 1 0 1 1 Q Q\ 2) Complete the following timing

More information

Sequential Logic Design Principles.Latches and Flip-Flops

Sequential Logic Design Principles.Latches and Flip-Flops Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch

More information

Sequential Logic Circuits Part I (Memory Element)

Sequential Logic Circuits Part I (Memory Element) Sequential Logic Circuits Sequential Logic Circuits Part I (Memory Element) CIT 595 Spring 2010 Output depends on stored information (current state) and may be on current inputs Example: state = Score

More information

CHAPTER 11 LATCHES AND FLIP-FLOPS

CHAPTER 11 LATCHES AND FLIP-FLOPS CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

More information

1. A Sequential Parity Checker

1. A Sequential Parity Checker Chapter 13: Analysis of Clocked Sequential Circuits 1. A Sequential Parity Checker When binary data is transmitted or stored, an extra bit (called a parity bit) is frequently added for purposes of error

More information

Digital Circuits Laboratory LAB no. 9. Flip flops

Digital Circuits Laboratory LAB no. 9. Flip flops (FF) are sequential logic circuits with 2 distinct stable states. hey have control inputs that cause the outputs to switch from one stable state to the other. hey are circuits with memory, because one

More information

DIGITAL SYSTEM DESIGN LAB

DIGITAL SYSTEM DESIGN LAB EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flip-flops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC

More information

COMPUTER ENGINEERING PROGRAM

COMPUTER ENGINEERING PROGRAM Learning Objectives COMPUTER ENGINEERING PROGRAM California Polytechnic State University CPE 169 Experiment 8 Basic Binary Counter Design Using Sequential Logic 1. Digital Systems Design To design and

More information

CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS

CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS This chapter in the book includes: Objectives Study Guide 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing and Timing Charts 13.3 State

More information

Chapter 6 Registers and Counter

Chapter 6 Registers and Counter Chapter 6 Registers and Counter The filp-flops are essential component in clocked sequential circuits. Circuits that include filp-flops are usually classified by the function they perform. Two such circuits

More information

CHAPTER 12 REGISTERS AND COUNTERS

CHAPTER 12 REGISTERS AND COUNTERS CHAPTER 12 REGISTERS AND COUNTERS This chapter in the book includes: Objectives Study Guide 12.1 Registers and Register Transfers 12.2 Shift Registers 12.3 Design of Binary Counters 12.4 Counters for Other

More information

TUTORIAL 1: Overview of a Digital Logic

TUTORIAL 1: Overview of a Digital Logic Questions 3 TUTORIAL : Overview of a Digital Logic. Fill in the terms for the definition. Term Definition i) Being continuous or having continuous values. ii) iii) iv) v) vi) A basic logic operation in

More information

28. Minimize the following using Tabular method. f(a, b, c, d, e)= m(0,1,9,15,24,29,30) + d(8,11,31) 29. Minimize the following using K-map method.

28. Minimize the following using Tabular method. f(a, b, c, d, e)= m(0,1,9,15,24,29,30) + d(8,11,31) 29. Minimize the following using K-map method. Unit-1 1. Show Karnaugh map for equation Y = F(A,B,C) = S m(1, 2, 3, 6, 7) 2. Show Karnaugh map for equation Y = F(A,B,C,D) = S m(1, 2, 3, 6, 8, 9, 10, 12, 13, 14) 3. Give SOP form of Y = F(A,B,C,D) =

More information