# Unit 3 Combinational MOS Logic Circuits

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1 Unit 3 ombinational MOS Logic ircuits

2 LATH

3 Latch It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its input Symbols are often labeled data and enable/clock ( and ) S R n+1 X 0 n Hold Reset Set ircuit Symbol Function Table

4 locked Latch Simplest clocked latch of practical importance is the locked latch S R It means that both active 1 inputs at R and S can t occur. Notice we ve reversed S and R so when is 1 is 1.

5 Transparency The devices that we have looked so far are transparent That is when = 1 the output follows the input There will be a slight lag between them t t t When the clock gate opens, changes in input take effect at outputs transparency. Also known as leveltriggered.

6 Propagation elay, set-up and hold (for transparent circuits) Propagation delay: Time taken for any change at inputs to affect outputs (change on to change on ). Setup time: ata on inputs must be held steady for at least this time before the clock changes. Hold time: ata on inputs must be held steady for at least this time after the clock changes.

7 locked Latch Timing iagram clock clock enables input to be seen output follows input in here

8 Latches - Summary Two cross-coupled NOR gates form an SR (set and reset) latch A clocked SR latch has an additional input that controls when setting and resetting can take place A latch has a single data input the output is held when the clock input is a zero the input is copied to the output when the clock input is a one The output of the clocked latches is transparent The output of the clocked latch can be represented by the following behaviour n+1 X 0 n Hold Reset Set

9 Latches and Flip Flops Terms are sometimes used confusingly: A latch is not clocked whereas a flip-flop is clocked. A clocked latch can therefore equally be referred to as a flip flop (SR flip flop, flip flop). However, as we shall see, all practical flip flops are edge-triggered on the clock pulse. Sometimes latches are included within flip flops as a sub-type.

10 Flip-flops Propagation elay Will the output of the following circuit ever be a 1? A B B A The brief pulse or glitch in the output is caused by the propagation delay of the signals through the gates

11 Latches and Flip Flops locked latches are level triggered. While the clock is high, inputs and thus outputs can change. This is not always desirable. A Flip Flop is edge-triggered either by the leading or falling edge of the clock pulse. Ideally, it responds to the inputs only at a particular instant in time. It is not transparent.

12 -type Latch Timing Review S The high part represents active 1, the low part active t t t

13 Positive edge-triggered Flip-flop Timing ~ initially unknown

14 Master Slave Flip-flop A negative edge triggered flip-flop Master Slave Y On the negative edge of the clock, the master captures the input and the slave outputs it.

15 The master-slave Flip-flop Master P Slave P No matter how long the clock pulse, both circuits cannot be active at the same time.

16 -type Positive Edge Triggered Flipflop LK S R The most economical flip-flop - uses fewest gates

17 JK Flip-flop J The most versatile of the flip-flops Has two data inputs (J and K) o not have an undefined state like SR flip-flops When J & K both equal 1 the output toggles on the active clock edge Most JK flip-flops based on the edge-triggered principle K +ve edge triggered JK flip-flop The column indicates +ve edge triggering (usually omitted) J K n n Hold Reset Set 1 1 n Toggle X X X n Hold

18 Example JK circuit J k A E K B F ~ Assume = 0, ~ = 1, K = 1 Gate B is disabled ( = 0, F = 1) Make J = 1 to change circuit, when k = 1, all inputs to A = 1, E goes to 0, makes = 1 Now and F are both 1 so ~ = 0 and the circuit has toggled. J K n n Hold Reset Set 1 1 n Toggle X X X n Hold

19 Timing diagram for JK Flip-flop Negative Edge Triggered clock J K toggle J=K=1 hold J=K=0 reset J= 0 K=1 set J= 1 K=0

20 lock Pulse The JK flip flop seems to solve all the problems associated with both inputs at 1. However the clock rise/fall is of finite duration. If the clock pulse takes long enough, the circuit can toggle. For the JK flip flop it is assumed the pulse is quick enough for the circuit to change only once. ideal / actual edge pulse

21 JK from Flip-flop J K LK

22 Summary Flip flops are circuits controlled by a clock. Triggered on the edge of the pulse to avoid races with both inputs at 1 during the clock pulse. Because oder ic s have a s all propagatio delay races ca still occur. The master-slave configuration solves this problem by having only master or slave active at any one time.

23 What you should be able to do Explain the difference between combinational and sequential circuits Explain the basic operation of SR and latches. Explain the operation of SR and JK flip flops. Explain the operation of master-slave flip flops. raw simple timing diagrams for clocked latches and edgetriggered flip flops. efine setup and hold times for a transparent latch.

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The 555 Timer The 555 Timer is a versatile and widely used device which can be configured as a mono-stable One-Shot or as an Astable multivibrator. An Astable multivibrator is known as an Oscillator which

### 0 0 Q(t) No change 0 0 Q(t) No change Reset Reset Set Set 1 1 Qt () Complement 1 1? Undefined

T-68 Flip-Flop haracteristic Table (a) JK Flip-Flop (b) Flip-Flop J K (t ) Operation (t ) Operation (t) No change (t) No change eset eset et et t () omplement? Undefined (c) Flip-Flop (d) T Flip-Flop (t

### Lesson 14 Design of Sequential Circuits Using D Flip-Flops

Lesson 4 esign of Sequential Circuits Using Flip-Flops. esign Procedure This lesson is another example of it all coming together. In this lesson, you will learn how to design state machines out of flip-flops