Supplementary Material

Transcription

1 Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering Giorgio Dell Erba 1,2, Alessandro Luzio 1, Dario Natali 1,2, Juhwan Kim 4, Dongyoon Khim 4, Dong- Yu Kim 4, Yong-Young Noh 3,*, Mario Caironi 1,* (1) Center for Nano Science and Istituto Italiano di Tecnologia, Via Pascoli 70/3, Milano, Italy (2) Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza L. da Vinci 32, Milano, Italy (3) Department of Energy and Materials Engineering, Dongguk University, 26 Pil-dong, 3-ga, Junggu, Seoul, , Republic of Korea (4) Heeger Center for Advanced Materials, School of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), 261 Cheomdan-gwagiro, Buk-gu, Gwangju , Republic of Korea *Corresponding author: mario.caironi@iit.it, yynoh@dongguk.edu. Supplementary Material D-Latch A latch is an electronic device generally used to store one bit of information. The D-Latch is used to capture the logic level of the DATA line when the clock input is high and store it when clock input is low. As discussed in the main text, through the optimization of unipolarized n-type transistors, we are able to developed complementary pass-transistor logic. A D-Latch implemented with this kind of logic consists in 8 transistors, accordingly with the circuit layout in Figure SM1(a). The Figure SM1(b) show the dynamic characterization of a single D-Latch. The D-Latch has two working phases, transparent and opaque. The device is defined transparent when CK is high (CK low); the transmission gate TG1 acts as a short circuit while TG2 as an open circuit. Consequently, the DATA input is inverted twice, by INV1 and INV2, and then transmitted to the output node OUT. In this phase, every modification of the DATA line is reported directly to the output. During the opaque phase CK is low (CK is high) hence TG1 is an open circuit while TG2 is a short, therefore closing the loop that forces the output node OUT to be the input of INV1. This

2 positive feedback loop is responsible for the memory effect; the output state is retained by the same loop (e.g. if OUT= 1 then OUTINV1= 0 and then OUTINV2=OUT= 1 ). Any change in the DATA line during the opaque phase does not affect the output of the D-Latch. D-Flip-Flop The Master-Slave D-Flip-Flop is one of the basic memory circuit in digital electronics, consisting in two D-Latch working with opposite clock signals (Fig. SM2(a)). The architecture is called masterslave since the second D-Latch changes its state only if the first one does. In his pass-transistor logic implementation, the D-Flip Flop consists of 16 transistors. Referring to Figure SM2(a), since the two D-Latch are enabled by opposite clock signals, while D-Latch 1 is transparent D-Latch 2 is opaque and vice versa. For this reason, only when a fallingedge of the clock signal occurs the instant value of the input data is sampled by D-Latch 1, that passing from transparent to opaque stores the sampled data in his feedback loop, and inverted by D- Latch 2 in transparent phase. The resulting output is showed in Figure SM2(b). To underline the proper operation of the device, we measured the single D-Latches while the whole circuit was on (supply and clock signals connected to the whole circuit). For D-Latch 1, a 50Hz square wave and a 20Hz clock were fed to the DATA and CK node respectively, while the output was measured on the inverted output Q 1. For D-Latch 2, the 50Hz square wave was fed to Q 1 ; output was measured on Q 2 node. Output waveforms (Fig. SM2(c) and SM2(d)) show D-Latch 1 and D- Latch 2 correctly working both in transparent, allowing the input to pass to the output (inverted in this case), and opaque phase, acting as a memory element preserving the input state at the clock switch.

3 Figure SM1. (a) Pass transistor logic D-Latch circuit layout and (b) output waveforms with 50Hz data input and 20Hz clock signal

4 Figure SM2. (a) Master-Slave D-Flip-Flop circuit layout and (b) his working demonstration in response to a random signal with a 20Hz clock. (c) Response to a 50Hz signal with 20Hz clock of the D-Latch 1 and (d) D-Latch 2 blocks of the D-Flip-Flop. Aspect ratios of transistors are Wp/Lp = 2mm/20μm and Wn/Ln = 6mm/20μm.

5 Figure SM3. Optical microscope picture of the chip consisting in 4 D-Flip-Flops and 9 Inverters.

6 % level 45 OUT [V] % level t RISE =34.2 s Time [ s] Figure SM4. Enlarged view of a single rising edge of Figure 2(d) for rise-time extimation

7 IN [V] OUT [V] Time [ms] Figure SM5. Logic Inverter dynamic characterization for a 1kHz input square wave.