ECE 301 Digital Electronics
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1 ECE 301 Digital Electronics Latches and Flip-Flops (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.
2 Brief introduction to Sequential Logic Circuits Spring 2011 ECE Digital Electronics 2
3 Sequential Logic Circuits The output of a sequential logic circuit is dependent not only on the present inputs, but also on the past sequence of the inputs. A sequential logic circuit must remember the past history of the inputs. It does this using basic memory elements. Latches Flip-Flops Spring 2011 ECE Digital Electronics 3
4 Sequential Logic Circuits inputs Combinational Logic Circuit Memory outputs Spring 2011 ECE Digital Electronics 4
5 Basic Memory Elements Spring 2011 ECE Digital Electronics 5
6 Basic Memory Elements Latch Clock input is level sensitive. Flip-Flop Output can change multiple times during a clock cycle. Output changes while clock is active. Clock input is edge sensitive. Output can change only once during a clock cycle. Output changes on clock transition. Spring 2011 ECE Digital Electronics 6
7 Basic Memory Elements Both latches and flip-flops use feedback to achieve memory. Spring 2011 ECE Digital Electronics 7
8 Feedback Circuit with 2 Stable States What is the problem with this circuit? Spring 2011 ECE Digital Electronics 8
9 Latches Spring 2011 ECE Digital Electronics 9
10 Set-Reset (SR) Latch A Set-Reset Latch has two inputs Set (S) input Reset (R) input It can be constructed from two cross-coupled NOR gates or two cross-coupled NAND gates. It has three modes of operation Set: Latch output set to 1 (Q + = 1) Reset: Latch output reset to 0 (Q + = 0) Store: Latch output does not change (Q + = Q) Spring 2011 ECE Digital Electronics 10
11 SR Latch: using NOR gates A B NOR 0 X X' 1 X 0 Feedback NOR gates Spring 2011 ECE Digital Electronics 11
12 SR Latch: Set (S = 1, R = 0) A B NOR 0 X X' 1 X P = Q' 0 1 Spring 2011 ECE Digital Electronics 12
13 SR Latch: Reset (S = 0, R = 1) A B NOR 0 X X' 1 X P = Q' 1 0 Spring 2011 ECE Digital Electronics 13
14 SR Latch: Store (S = 0, R = 0) Initial Condition: P = 0, Q = 1 A B NOR 0 X X' 1 X P = Q' 0 1 Spring 2011 ECE Digital Electronics 14
15 SR Latch: Store (S = 0, R = 0) Initial Condition: P = 1, Q = 0 A B NOR 0 X X' 1 X P = Q' 0 0 Spring 2011 ECE Digital Electronics 15
16 SR Latch: Behavior Present value Next value S R Q Q not allowed If S = 1 (Set), Q + = 1 If R = 1 (Reset), Q + = 0 If S = R = 0, Q + = Q (no change) S = R = 1 is not allowed. Spring 2011 ECE Digital Electronics 16
17 SR Latch: Improper Operation P Q Spring 2011 ECE Digital Electronics 17
18 SR Latch: Symbol always complementary Q' S Q SR Latch Q R Q' Spring 2011 ECE Digital Electronics 18
19 SR Latch: Timing Diagram store set store reset Q' Q ε = propagation delay of the latch Spring 2011 ECE Digital Electronics 19
20 SR Latch: Characteristic Equation Q = present state Q + = next state Characteristic Equation: Q + = S + R'.Q (S.R = 0) Spring 2011 ECE Digital Electronics 20
21 SR Latch: using NAND gates A B NAND 0 X 1 1 X X' S' R' Q Q not allowed Spring 2011 ECE Digital Electronics 21
22 Gated D Latch A Gated D Latch has two inputs Gate (G) input Data (D) input It can be constructed from an SR Latch and additional logic gates. It has the following behavior G = 1: D is passed to Q (Q + = D) G = 0: Q remains unchanged (Q + = Q) Also referred to as a transparent latch. Spring 2011 ECE Digital Electronics 22
23 Gated D Latch: Circuit and Timing NOR gates Spring 2011 ECE Digital Electronics 23
24 Gated D Latch: Symbol and Truth Table No invalid inputs! Spring 2011 ECE Digital Electronics 24
25 Gated D Latch: Characteristic Equation Characteristic Equation: Q + = G'.Q + G.D Spring 2011 ECE Digital Electronics 25
26 Gated D Latch: using NAND gates S' R' NAND gates Spring 2011 ECE Digital Electronics 26
27 Flip-Flops Spring 2011 ECE Digital Electronics 27
28 D Flip-Flop A D Flip-Flop has two inputs Clock (Ck) --- denoted by the small arrowhead Data (D) The output of the D Flip-Flop changes in response to the clock input only. not in response to a change in the D input The D Flip-Flop is edge-triggered not level-sensitive Positive (or rising) edge-triggered: 0 1 Negative (or falling) edge-triggered: 1 0 Spring 2011 ECE Digital Electronics 28
29 D Flip-Flop Characteristic Equation: Q + = D Spring 2011 ECE Digital Electronics 29
30 D Flip-Flop: Timing Diagram Which clock edge is the D flip-flop triggered on? Spring 2011 ECE Digital Electronics 30
31 D Flip-Flop (master-slave) Gated D Latches Enabled on opposite levels of the clock Spring 2011 ECE Digital Electronics 31
32 D Flip-Flop: Timing Diagram Which clock edge is the D flip-flop triggered on? Spring 2011 ECE Digital Electronics 32
33 D Flip-Flop: Setup and Hold Times Setup time Hold time Propagation delay Spring 2011 ECE Digital Electronics 33
34 D Flip-Flop: Minimum Clock Period Spring 2011 ECE Digital Electronics 34
35 Questions? Spring 2011 ECE Digital Electronics 35
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