E20 Reverse engineering on a CMOS image sensor

Transcription

1 MEMS AND MICROSENSORS /2016 E20 Reverse engineering on a CMOS image sensor Paolo Minotti 20/01/2016 In this class we will learn how to infer some parameters of a CMOS sensor for digital imaging, starting from its datasheet. We will appreciate how to perform a sort of reverse engineering: starting from few assumptions on some technology parameters, we will try to extract some performance parameters of the sensor and we will compare them with the ones declared in the datasheet. Some of these considerations will involve also some timing issues related to the readout of CMOS image sensors. PROBLEM The datasheet of a commercial CMOS image sensor is attached in Fig. 5. In particular, we are interested in the 46 fps operating mode. A block diagram of the image sensor is reported in Fig. 1. Some technology parameters are reported in Table 1. You are asked to check if you get the conversion gain, the full-well charge, dark noise, dynamic range and maximum signal-to-noise ratios given by the manufacturer. Assuming that one fourth of the power dissipated by the sensor is due to the current required to bias the in-pixel amplifiers, find the gate width required to get a transconductance of the source follower adequate to reach a rise time (of the signal at the output node, when connected to the readout electronics) in the order of one third of the time available to readout each pixel. 1

2 Figure 1: Block diagram of the considered sensor. PART 1: REVERSE ENGINEERING Given the assumptions on the technology, we can immediately estimate the integration capacitance. We know that in a 3T topology, usually, the main contribution to the integration capacitance is due to the photodiode itself, whose depletion capacitance is much higher than the input capacitance of the in-pixel amplifier. We can first estimate the width of the depletion region of the photodiode as x dep = 2ε Si qn A ( φbi +V rev ), AssuminG a 1 V built in voltage and the maximum reverse bias voltage that can be applied (3.3 V), one gets a depletion width of 2.6 µm. The depletion capacitance of the photodiode can be thus estimated as C PD = ε Si A PD x dep, 2

3 Table 1: Technology parameters. Pixel topology 3T APS Fill factor 65% Doping concentration of p-epylayer N A cm 3 Doping concentration of n + layer N D cm 3 Parasitic capacitance of the column bus C col 0.1 pf/mm Minimum dimension 150 nm NMOS gain factor µ n C ox 100 µa/v 2 where A PD is the active area of the photodiode, which is lower than the area of the pixel, due to the fill factor limitation. With the mumbers provided, we get: C PD = ε Si A PD = ε ( ) 2 Si µm = 0.77 ff. x dep 2.6 µm The conversion gain (CG) of a pixel is defined as the ratio between the output voltage variation per unit electron-hole pair (EHP): In our case C int C PD and we get CG = V out = q. N ph C int CG = q = 207 µv/e ff The datasheet declares the conversion gain in terms of LSB/e. With the 46 fps operating mode, the resolution of the system in terms of bits is 12. We can thus extrapolate the LSB: LSB = V DD 2 N bi t Hence, the conversion gain expressed in LSB is CG LSB = CG LSB = = 3.3 V = 805 µv µv/e = 0.26 LSB/e. 805 µv/lsb which is three times higher than the expected. This is acceptable, as too many assumptions/guesses have been made to estimate the photodiode capacitance. The full-well charge (FWC) can be easily estimated: FW C = N max = V DDC int q 3.3 V 0.77 ff = = e, q 3

4 which is a little bit higher than the value declared in the datasheet. This error is acceptable, too: the full-well charge of a standard pn-photodiode depends on the non-linear behavior of the depletion capacitance, which was not taken into account during our computations. To estimate dark current noise, we can determine dark current shot noise and reset noise. Dark current shot noise can be evaluated as σ dark = i dark q t int,dark, where i dark/q is the 41 e/s parameter provided in the datasheet, while t int,dark is the dark current integration time. To be precise, dark current integration time is independent from the photons integration time, but depends on the time interval fromn the reset of the photodiode and its readout. Hence, we can estimate the dark current integration time as the inverse of the frame rate (46 fps), i.e. 22 ms. The dark current shot noise is thus 1 e rms. On the other hand, reset noise can be estimated as σ reset = kb TC int q = 11 e rms, which gives an overall dark noise (DN) of 11 electrons rms, strongly dominated by reset noise. The datasheet declares an 8.6 electrons (rms) dark noise, probably reduced thanks to a correlated double sampling technique. Take note that the dark current expressed in amperes is equal to: i dark = 41 e/s q = 6.5 aa, an extremely low value, likely due to the adoption of a very good CMOS technology, suitably optimized for imaging. The dynamic range of the sensor can be easily estimated: DR db = 20log 10 ( FW C DN ) = 20log 10 ( ) = 63 db, slightly higher than the one declared in the datasheet, in agreement with all the assumed approximations. The maximum signal-to-noise ratio can be easily estimated as SNR max,db = 20log 10 ( FW C FW C ) = 20log 10 FW C = 42 db, in close agreement with the value provided in the datasheet. PART 2: TIMING ISSUES The datasheet states that the output interface consists of 16 LVDS (low-voltage differential signaling) outputs (see Fig. 2). We can thus infer that the pixels ( = 8 MPixel) are readout with 16 independent readout circuits, each one with its own readout electronics. In other words, we can divide the matrix in 16 sub-sectors which are readout in parallel. The 4

5 Figure 2: Sub-sectors representation. frame rate is 46 fps. This corresponds to a 21.7 ms time interval. This time integral should be divided between the three phases needed for photons detection in a 3T pixel: reset, integration and readout. The reset phase (which occurs in parallel for all the pixels) can be neglected: assuming a 1 kω on-resistance of the reset switch and assuming a 1 ff capacitance of the integration node, the time constant is 1 ps; hence, few picoseconds are sufficient to guarantee the reset of the integration capacitances. The remaining time should be divided between the integration phase and the readout phase. Let s assume a 1 ms integration time; this is negligible with respect to the total time (21.7 ms). For sake of simplicity, we ll completely neglect the integration time. With all these considerations, the maximum readout time of each pixel is equal to 1 t pi x = F R N pi x 16 = t f r ame N pi x 16 = 41 ns. If one wanted to take into account also the integration time, the maximum allowed readout time would be lower, given by the differencve between t f r ame and t int. The maximum read- 5

6 Figure 3: Time diagram of the readout process. out time of each pixel would be thus equal to t pi x = t f r ame t int N pi x A time diagram is reported in Fig. 3. Please note that n pi x depends on the parallelization of the readout process, and may be lower than the total number of the pixels! The total power consumption of the sensor, extrapolated from datasheet values, is i tot = 16 P V DD = 272 ma. Assuming that the total current used to bias the source followers is one fourth of the total, and since there are 16 independents readout interfaces, the bias current allocated for each of the 16 readout circuits is i bi as = 1 i tot = 4.3 ma The required width of the source follower is related with its transconductance, that determines the transient behavior of the readout chain. In fact, the output node of a pixel, when connected to the column bus (to be readout) can be well approximated as an RC network: the resistance is mainly given by the transconductance of the source follower, while the capacitance is given by the whole capacitance of the columns bus. A schematic of the circuit is reported in Fig. 4. Assuming that the matrix is divided into 16 adjacent rectangular (long. 6

7 Figure 4: Schematic representation of the readout of, e.g., pixel #32. and thin) sub-sectors (see Fig. 2), the length of each column bus is approximately equal to the height of the sensor, i.e. H sens = N pi x,h l pi x = µm = 13.7 mm. Hence the column bus capacitance can be estimated as C col = C col H sens = 0.1 pf/mm 13.7 mm = 1.37 pf. In order to have a rise time equal to one third of the total readout available time for each pixel, and considering that the rise time is 5 times the RC constant of the network, the required transconductance of the in-pixel amplifier is given by the following equation: 5τ = 5 1 g m C col = 1 3 t pi x 7

8 Hence: As g m = 15C col t pi x = 500 µa/v 2. g m = 2µ n C ox the required width-over-length ratio is equal to: W L i bi as, W L = gm 2 = µ n C oxi bi as Assuming a minimum length, i.e. L = 150 nm, the corresponding width is W = W L L = 44 nm, which is lower than the minimum dimension allowed by the technology. This means that a transistor with minimum dimensions (150 nm / 150 nm) plenty fulfils the timing requirements. 8

9 PRODUCT SHEET CMV8000 AREA SCAN SENSORS The CMV8000 is a global shutter CMOS image sensor with 3360 by 2496 pixels in a 4/3 optical format. The image array consists of 5.5 um by 5.5 um pipelined global shutter pixels, which allow exposure during read out while performing CDS operation reducing fixed pattern and dark noise significantly. The CMV8000 has 16 digital LVDS outputs (serial) each running at 600 Mbps, which results in 104 fps frame rate at full resolution in 10-bit mode. Higher frame rates can be achieved in row-windowing mode or row-subsampling mode. A 12-bit per pixel mode is available at reduced frame rates. SPECIFICATIONS Part status Pre-production Resolution 8MP (H) x 2496 (V) Pixel size 5.5 x 5.5 Optical format 4/3" Shutter type Global shutter Frame rate 104 fps (10 bit) 46 fps (12 bit) Output interface 16 LVDS 600 Mbps Sensitivity 5.56 V/lux.s Conversion gain LSB/e- Full well charge e- Dark noise 8.6 e- (RMS) Dynamic range 61 db SNR max 41,3 db Parasitic light sensitivity 1/20000 Extended dynamic range Yes, up to 90 db Dark current 41.2 e-/s (25 C) Fixed pattern noise < 1 LSB (<0,1% of full swing) Chroma Mono and RGB Supply voltage 1,8V / 3,3V Power 900 mw Operating temperature range -30 to +70 degc RoHS compliance Yes Package 107 pins upga CMOSIS takes care to ensure the accuracy of the information contained in this document but reserves the right to change specifications without notice. Page 1/2 Figure 5: Datasheet of a commercial CMOS image sensor: CMV800 from CMOSIS ( 9