TYPICAL APPLICATION LTC7543/LTC8143 LTC7543/LTC Multiplying DAC Has Easy 3-Wire Serial Interface. Integral Nonlinearity over Temperature

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1 TYPICAL APPLICATION V IN Multiplying DAC Has Easy -Wire Serial Interface 5V Integral Nonlinearity over Temperature.0 CLOCK DATA LOAD V DD R FB STB LTC5 LTC8 LD DGND AGND pf + LT 09 V OT 5/8 TA0 INTEGRAL NONLINEARITY () T A = 85 C T A = 5 C T A = 0 C DIGITAL INPT CODE 5/8 TA0 6-66

2 ABSOLTE MAXIMM RATINGS W W W V DD to AGND V to V V DD to DGND V to V AGND to DGND... V DD + 0.5V DGND to AGND... V DD + 0.5V Digital Inputs to DGND V to (V DD + 0.5V) V OT, V OT to AGND V to (V DD + 0.5V) to AGND, DGND... ±5V V RFB to AGND, DGND... ±5V Maximum Junction Temperature C Operating Temperature Range... 0 C to 85 C Storage Temperature Range C to 50 C Lead Temperature (Soldering, 0 sec) C PACKAGE/ORDER INFORMATION AGND STB LD NC (LTC5) SRO (LTC8) STB TOP VIEW 6 R FB 5 V DD CLR DGND STB 0 STB 9 LD N PACKAGE 6-LEAD PDIP SW PACKAGE 6-LEAD PLASTIC SO WIDE T JMAX = 50 C, θ JA = 00 C/ W (N) T JMAX = 50 C, θ JA = 0 C/ W (SW) W ORDER PART NMBER LTC5GKN LTC5KN LTC5GKSW LTC5KSW LTC8EN LTC8FN LTC8ESW LTC8FSW Consult factory for Military grade parts. ACCRACY CHARACTERISTICS (LTC5) V DD = 5V, = 0V, V OT = V OT = AGND = DGND =0V, T A = T MIN to T MAX, unless otherwise specified. LTC5GK LTC5K SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Resolution Bits INL Integral Nonlinearity (Note ) ±0.5 ±0.5 (Relative Accuracy) DNL Differential Nonlinearity Guaranteed Monotonic, T MIN to T MAX ±0.5 ±0.5 GE Gain Error (Note ) T A = 5 C ± ± T MIN to T MAX ± ± Gain Temperature Coefficient (Note ) 5 5 ppm/ C ( Gain/ Temp) I LKG Output Leakage Current (Note ) T A = 5 C ± ± na T MIN to T MAX ±0 ±0 na Zero-Scale Error T A = 5 C ±0.006 ±0.006 T MIN to T MAX ±0.06 ±0.06 PSRR Power Supply Rejection Ratio V DD = 5V ±5% ±0.000 ±0.00 ±0.000 ±0.00 %/% 6-6

3 ACCRACY CHARACTERISTICS V DD = 5V, = 0V, V OT = V OT = AGND = DGND = 0V, T A = T MIN to T MAX, unless otherwise specified. LTC8E LTC8F SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Resolution Bits INL Integral Nonlinearity (Note ) ±0.5 ± (Relative Accuracy) DNL Differential Nonlinearity Guaranteed Monotonic, T MIN to T MAX ±0.5 ± GE Gain Error (Note ) T A = 5 C ± ± T MIN to T MAX ± ± Gain Temperature Coefficient (Note ) 5 5 ppm/ C ( Gain/ Temp) I LKG Output Leakage Current (Note ) T A = 5 C ±5 ±5 na T MIN to T MAX ±5 ±5 na Zero-Scale Error T A = 5 C ±0.0 ±0.0 T MIN to T MAX ±0.5 ±0.5 PSRR Power Supply Rejection Ratio V DD = 5V ±5% ±0.000 ±0.00 ±0.000 ±0.00 %/% ELECTRICAL CHARACTERISTICS (LTC8) V DD = 5V, = 0V, V OT = V OT = AGND = DGND = 0V, T A = T MIN to T MAX, unless otherwise specified. ALL GRADES SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Reference Input R REF Input Resistance (Note 5) 8 5 kω AC Performance (Note ) Output Current Settling Time (Notes 6, ) 0.5 µs Multiplying Feedthrough Error = ±0V, 0kHz Sinewave 0.8 mv P-P Digital-to-Analog Glitch Energy (Notes 6, 8) 0 nv-sec THD Total Harmonic Distortion (Note 9) 08 9 db Output Noise Voltage Density (Note 0) nv/ Hz Analog Outputs (Note ) C OT Output Capacitance DAC Register Loaded to All s C OT pf C OT 0 60 pf DAC Register Loaded to All 0s C OT 0 60 pf C OT pf Digital Inputs V IH Digital Input High Voltage. V V IL Digital Input Low Voltage 0.8 V I IN Digital Input Current V IN = 0V to V DD 0.00 ± µa C IN Digital Input Capacitance (Note ), V IN = 0V 8 pf Digital Outputs: SRO (LTC8 Only) V OH Digital Output High I OH = 00µA V V OL Digital Output Low I OL =.6mA 0. V 6-68

4 ELECTRICAL CHARACTERISTICS V DD = 5V, = 0V, V OT = V OT = AGND = DGND = 0V, T A = T MIN to T MAX, unless otherwise specified. ALL GRADES SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Timing Characteristics (Note ) t DS Serial Input to Strobe Setup Time STB sed as the Strobe 50 5 ns t DS (t STB = 80ns) STB sed as the Strobe 0 5 ns t DS STB sed as the Strobe 0 0 ns t DS STB sed as the Strobe 0 0 ns t DH Serial Input to Strobe Hold Time STB sed as the Strobe 0 0 ns t DH (t STB = 80ns) STB sed as the Strobe 50 5 ns t DH STB sed as the Strobe ns t DH STB sed as the Strobe ns t Serial Input Data Pulse Width 80 ns t STB, t STB, Strobe Pulse Width (Note ) 80 ns t STB, t STB t STB, t STB, Strobe Pulse Width (Note ) 80 ns t STB, t STB t LD, t LD Load Pulse Width 0 ns t ASB Strobed into Input Register 0 ns to Load DAC Register Time t CLR Clear Pulse Width 80 ns SRO Timing Characteristics (LTC8 Only) t PD STB, STB, STB Strobe to SRO C L = 50pF 0 0 ns Propagation Delay t PD STB to SRO Propagation Delay C L = 50pF ns Power Supply V DD Supply Voltage V I DD Supply Current Digital Inputs = 0V or V DD 0. ma Digital Inputs = V IH or V IL ma The denotes specifications which apply over the full operating temperature range. Note : ±0.5 = ±0.0% of full scale. Note : sing internal feedback resistor. Note : Guaranteed by design, not subject to test. Note : I OT with DAC register loaded with all 0s or I OT with DAC register loaded with all s. Note 5: Typical temperature coefficient is 00ppm/ C. Note 6: load = 00Ω in parallel with pf. Note : To 0.0% for a full-scale change, measured from falling edge of LD or LD. Note 8: = 0V. DAC register contents changed from all 0s to all s or from all s to all 0s. Note 9: = 6V RMS at khz. DAC register loaded with all s. Note 0: Calculation from e n = KTRB where: K = Boltzmann constant (J/K ); R = resistance (Ω); T = resistor temperature ( K); B = bandwidth (Hz). Note : Minimum high time for STB, STB, STB. Minimum low time for STB. Note. Minimum low time for STB, STB, STB. Minimum high time for STB. 6-69

5 BLOCK DIAGRAM W 5 6 R FB 0k V DD DECODER AGND CLR LD 5 LD 9 CLR LOAD BIT (MSB) BIT BIT BIT BIT DAC REGISTER () STB STB STB 8 0 CLK OT INPT -BIT SHIFT REGISTER IN STB 6 SRO 5/8 BD LTC8 ONLY DGND W W TI I G DIAGRA STROBE INPT STB, STB, STB (INVERT FOR STB) t DS t DS t DS t DS t DH t DH t DH t DH t STB t STB t STB t STB t STB t STB t STB t STB t PREVIOS WORD BIT MSB BIT BIT BIT t ASB LD, LD t LD t LD t PD t PD SRO (LTC8 ONLY) BIT (MSB) PREVIOS WORD BIT BIT BIT BIT (MSB) CRRENT WORD 5/8 TD0 6-0

6 TRTH TABLES Table. Input Register CONTROL INPTS Input Register Operation STB STB STB STB (LTC8: SRO Operation) 0 0 Serial Data Bit on Loaded into Input 0 0 Register, MSB First (LTC8: Data Bit or Appears on 0 0 SRO Pin After Clocked Bits) X X X No Input Register Operation X X X (LTC8: No SRO Operation) X X 0 X X X X Table. DAC Register CONTROL INPTS CLR LD LD DAC Register Operation 0 X X Reset DAC Register to All 0s (Asynchronous Operation; No Effect on Input Register) X No DAC Register Operation X 0 0 Load DAC Register with the Contents of Input Register TYPICAL APPLICATIONS nipolar Operation (-Quadrant Multiplication) 0V TO 0V 5V µp 0.µF TO NEXT DAC FOR DAISY-CHAINING (LTC8) STB CLR V DD R FB STB 5 LD LTC5 6 SRO (LTC8) LTC8 9 LD 8 STB STB DGND AGND pf + LT09 V OT 0V TO 5/8 TA0 nipolar Binary Code Table DIGITAL INPT BINARY NMBER IN ANALOG OTPT DAC REGISTER V OT MSB (095/096) (08/096) = / (/096) V 6-

7 TYPICAL APPLICATIONS Bipolar Operation (-Quadrant Multiplication) 0V TO 0V 5V 0.µF V DD 5 6 R FB pf R R (LOGIC INPTS OMITTED FOR CLARITY) LTC5 LTC8 + / LT R 0k + / LT V OT DGND AGND 5/8 TA0 Bipolar Offset Binary Code Table DIGITAL INPT BINARY NMBER IN ANALOG OTPT DAC REGISTER V OT MSB (0/08) (/08) V 0 (/08) (08/08) = RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC5 Complete Serial I/O V -Bit DAC 5V to 5V Single Supply in 8-Pin SO and PDIP LTC5/LTC5/LTC5 Complete Serial I/O V -Bit DACs V/5V Single Supply in 8-Pin SO and PDIP LTC5A Parallel I/O Mulitplying -Bit DAC -Bit Wide Input LTC80 Serial Mulitplying -Bit DAC 8-Pin SO and PDIP 6-

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