Basics of Energy & Power Dissipation

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1 Basics of Energy & Power Dissipation ecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary Basic Concepts Dynamic power Static power Time, Energy, Power Tradeoffs Activity model for power estimation v Combinational and sequential logic Outline (2) 1

2 Reading CMOS#Power:_switching_and_leakage Goal: Understand v The sources of power dissipation in combinational and sequential circuits v Power vs. energy v Options for controlling power/energy dissipation (3) Where Does the Power Go in CMOS? Dynamic Power Consumption v Caused by switching transitions à cost of switching state Static Power Consumption v Caused by leakage currents in the absence of any switching activity Vin Vdd PMOS Vout NMOS Ground Power consumption per transistor changes with each technology generation v No longer reducing at the same rate v What happens to power density? AMD Trinity APU (4) 2

3 n-channel MOSFET GATE SOURCE GATE DRAIN t ox SOURCE DRAIN BODY V gs < V t transistor off - V t is the threshold voltage V gs > V t transistor on Impact of threshold voltage v Higher V t, slower switching speed, lower leakage v ower V t, faster switching speed, higher leakage Actual physics is more complex but this will do for now! (5) Abstracting Energy Behavior How can we abstract energy consumption for a digital device? Consider the energy cost of charge transfer Modeled as an on/off resistance V in V out 1 V in PMOS V out 1 NMOS Modeled as an output capacitance Ground (6) 3

4 Switch from one state to another To perform computation, we need to switch from one state to another ogic 1: Cap is charged + - Connect the cap to GND thorough an ON NMOS Connect the cap to VCC thorough an ON PMOS ogic : Cap is discharged The logic dictates whether a node capacitor will be charged or discharged. (7) Dynamic Power Dynamic power is used in charging and discharging the capacitances in the CMOS circuit. Voltage VDD VDD VDD i DD C i DD C T Input to CMOS inverter Time Output Capacitor Charging Output Capacitor Discharging C = load capacitance (8) 4

5 Switching Delay V out t RC V s = (1 e ) τ = RC Charging to logic 1 (9) Switching Delay V out t RC V c = Ve Discharging to logic (1) 5

6 Switching Energy C is the load capacitance Energy drawn from supply : d C E vdd = v out i vdd (t)v DD dt =V DD dt = C dt V DD 2 dv out = C VDD Energy stored in capacitor : ( ) V d C E C = v DD out i c (t)v out dt = v dt out dt = C v out dv out = 1 2 C V 2 DD ( ) Energy dissipated in resistor : E R = E vdd E C = 1 2 C V 2 DD Also,E R = i 2 R (t)rdt = i R (t) V v DD out Rdt = R => Independent of R V DD ( ) dt d C v out Energy dissipated per transition? ( V DD v out )dt = 1 2 C V 2 DD Courtesy: Prof. A. Roychowdhury (11) Power Vs. Energy Power(watts) P2 P1 P Same Energy = area under the curve Power(watts) P Time Time Energy is a rate of expenditure of energy v One joule/sec = one watt Both profiles use the same amount of energy at different rates or power (12) 6

7 Dynamic Power vs. Dynamic Energy Dynamic power: consider the rate at which switching (energy dissipation) takes place Voltage VDD VDD VDD i DD C i DD C T Input to CMOS inverter Time Output Capacitor Charging activity factor = fraction of total capacitance that switches each cycle! P dynamic = α C $ # & F " 2 % Output Capacitor Discharging Delay = k C ( V t ) 2 (13) a b c a b c Charge as a State Variable x y x y For computation we should be able to identify if each of the variable (a,b,c,x,y) is in a 1 or a state. We could have used any physical quantity to do that Voltage Current Electron spin Orientation of magnetic field All nodes have some capacitance associated with them We choose voltage distinguish between a and a 1. ogic 1: Cap is charged + - ogic : Cap is discharged (14) 7

8 Higher evel Blocks Vdd Vdd A A B Vdd B C A C A B B A B C A B C (15) Gate Power Dissipation Switching activity depends on the input pattern and combinational logic Consider a à 1 transition on the output of a gate p p 1 Probability gate output was Probability gate output is 1 p = N p 2 n 1 = N 1 N = number of s in the 2 n truth table Example: (16) 8

9 AU Energy Consumption Binvert CarryIn Operation B i n v e r t O p e r a t i o n C a r y I n a b CarryIn AU ess CarryOut Result a 1 a1 b1 CarryIn AU1 ess CarryOut Result1 b 2 1 R e s u l t e s s 3 a2 b2 CarryIn AU2 ess CarryOut CarryIn Result2 C a r r y O u t Can we count the number of transitions in each 1-bit AU for an operation? a31 b31 CarryIn AU31 ess Result31 Set Overflow Can we estimate static power? Computing per operation energy (17) Closer ook: A 4-bit Ripple Adder A3 B3 A2 B2 A1 B1 A B Carry Cin S3 S2 Critical Path = D XOR +4*(D AND +D OR ) for 4-bit ripple adder (9 gate levels) For an N-bit ripple adder Critical Path Delay ~ 2(N-1)+3 = (2N+1) Gate delays Activity (and therefore power) is a function of the input data values! S1 S (18) 9

10 Implications cond input clk Combinational ogic clk clk What if I halved the frequency? What if I lower the voltage? How can I reduce the capacitance? We will see later that these two are interrelated!! P dynamic = α C $ # & F " 2 % (19) Static Power Technology scaling has caused transistors to become smaller and smaller. As a result, static power has become a substantial portion of the total power. SOURCE GATE DRAIN Gate eakage Junction eakage Sub-threshold eakage P static = I static (2) 1

11 Energy-Delay Interaction Energy or delay Delay V DD Energy Power State Delay decreases with supply voltage but energy/power increases! P dynamic = α C $ # & F " 2 % Energy-Delay Product (EDP) Target of optimization V DD Delay = k C ( V t ) 2 (21) Static Energy-Delay Interaction leakage or delay leakage delay V th SOURCE GATE DRAIN t ox Delay = k C ( V t ) 2 Static energy increases exponentially with decrease in threshold voltage Delay increases with threshold voltage (22) 11

12 Temperature Dependence As temperature increases static power increases 1 P static = N K design I leakage Supply voltage #Transistors Technology Dependent Normalized eakage Current I leakage = F(Temp) 1 J. Butts and G. Sohi, A Static Power Model for Architects, MICRO 2 (23) The World Today Yesterdayà scaling to minimize time (max F)! P dynamic = α C $ # & F " 2 % Delay = k C ( V t ) 2 Maximum performance (minimum time) is too expensive in terms of power v Imaging scaling voltage by.7 and frequency by 1.5 à how does dynamic power scale? Today: trade/balance performance for power efficiency (24) 12

13 Transistor size v Affects capacitance (C ) Factors Affecting Power Rise times and fall times (delay) v Affects short circuit power (not in this course) Threshold voltage v Affects leakage power Temperature v Affects leakage power Switching activity v Frequency (F) and number of switching transistors ( α )! P dynamic = α C $ V # & F Delay = k C dd " 2 % ( V t ) 2 Vin Vdd PMOS NMOS Ground (25) Vout ow Power Design: Options?! P dynamic = α C $ # & F " 2 % Delay = k C ( V t ) 2 Reduce v Increases gate delay v Note that this means it reduces the frequency of operation of the processor! Compensate by reducing threshold voltage? v Increase in leakage power Reduce frequency v Computation takes longer to complete v Consumes more energy (but less power) if voltage is not scaled (26) 13

14 Example HW Only (Boost) SWVisible CPU P-state Pb Voltage (V) 1 Freq (MHz) 24 Pb P P P P P AMD Trinity A1-58 APU: 1W TDP (27) Optimizing Power vs. Energy Maximize battery life! minimize energy Thermal envelopes! minimize peak power Example: (28) 14

15 Modeling Component Energy Per-use energies can be estimated from Gate level designs and analyses Circuit-level designs and analyses Implementation and measurement There are various open-source tools for analysis Mentor, Cadence, Synopsys, etc. Hardware Design Technology Parameters Circuit-level Estimation Tool Estimation Results: Area, Energy, Timing, etc. (29) Datapath Elements CPU/Core Co-Processor 1 $ $1 $ $1 SIMD Registers XMM XMM1 $31 $31 XMM15 AU Multiply Divide FP AU Vector AU Hi o Can we measure (offline) the average energy consumed by each component? Can we measure (offline) the average energy consumed by each component? (3) 15

16 A Simple Power Model for Processors Per instruction energy measurements v Permits a software model of energy consumption of a program v Execution time use to assess power requirements A first order model of energy consumption for software v A table of energy consumption per instruction v More on this later! (31) What About Wires? umped RC Model R line = r l Resistance per unit length 1 2 C line τ = 1 2 rc l C line C line = c l Capacitance per unit length We will not directly address delay or energy expended in the interconnect in this class v Simple architecture model: lump the energy/power with the source component (32) 16

17 Summary Two major classes of energy/power dissipation static and dynamic Managing energy is different from managing power à leads to different solutions Technology plays a major role in determining relative costs Energy of components are often estimated using approximate models of switching activity (33) Explain the difference between energy dissipation and power dissipation Study Guide Distinguish between static power dissipation and dynamic power dissipation What is the impact of threshold voltage on the delay and energy dissipation? As you increase the supply voltage what is the behavior of the delay of logic elements? Why? As you increase the supply voltage what is the behavior of static and dynamic energy and static and dynamic power of logic elements? (34) 17

18 Study Guide (cont.) Do you expect the -1 and 1- transitions at the output of a gate to dissipate the same amount of energy? For a mobile device, would you optimize power or energy? Why? What are the consequences of trying to optimize one or the other? Why does the energy dissipation of a 32-bit integer adder depend on the input values? If I double the processor clock frequency and run the same program will it take less or more energy? (35) Study Guide (cont.) When the chip gets hotter, does it dissipate more or less energy? Why? How can you reduce dynamic energy of a combinational logic circuit? How can you reduce static energy of a combinational logic circuit? (36) 18

19 Glossary Dynamic Energy Dynamic Power oad capacitance Static Energy Static Power Time constant Threshold voltage Switching delay Switching energy (37) 19

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