Basics of Energy & Power Dissipation


 Bartholomew Webster
 1 years ago
 Views:
Transcription
1 Basics of Energy & Power Dissipation ecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary Basic Concepts Dynamic power Static power Time, Energy, Power Tradeoffs Activity model for power estimation v Combinational and sequential logic Outline (2) 1
2 Reading CMOS#Power:_switching_and_leakage Goal: Understand v The sources of power dissipation in combinational and sequential circuits v Power vs. energy v Options for controlling power/energy dissipation (3) Where Does the Power Go in CMOS? Dynamic Power Consumption v Caused by switching transitions à cost of switching state Static Power Consumption v Caused by leakage currents in the absence of any switching activity Vin Vdd PMOS Vout NMOS Ground Power consumption per transistor changes with each technology generation v No longer reducing at the same rate v What happens to power density? AMD Trinity APU (4) 2
3 nchannel MOSFET GATE SOURCE GATE DRAIN t ox SOURCE DRAIN BODY V gs < V t transistor off  V t is the threshold voltage V gs > V t transistor on Impact of threshold voltage v Higher V t, slower switching speed, lower leakage v ower V t, faster switching speed, higher leakage Actual physics is more complex but this will do for now! (5) Abstracting Energy Behavior How can we abstract energy consumption for a digital device? Consider the energy cost of charge transfer Modeled as an on/off resistance V in V out 1 V in PMOS V out 1 NMOS Modeled as an output capacitance Ground (6) 3
4 Switch from one state to another To perform computation, we need to switch from one state to another ogic 1: Cap is charged +  Connect the cap to GND thorough an ON NMOS Connect the cap to VCC thorough an ON PMOS ogic : Cap is discharged The logic dictates whether a node capacitor will be charged or discharged. (7) Dynamic Power Dynamic power is used in charging and discharging the capacitances in the CMOS circuit. Voltage VDD VDD VDD i DD C i DD C T Input to CMOS inverter Time Output Capacitor Charging Output Capacitor Discharging C = load capacitance (8) 4
5 Switching Delay V out t RC V s = (1 e ) τ = RC Charging to logic 1 (9) Switching Delay V out t RC V c = Ve Discharging to logic (1) 5
6 Switching Energy C is the load capacitance Energy drawn from supply : d C E vdd = v out i vdd (t)v DD dt =V DD dt = C dt V DD 2 dv out = C VDD Energy stored in capacitor : ( ) V d C E C = v DD out i c (t)v out dt = v dt out dt = C v out dv out = 1 2 C V 2 DD ( ) Energy dissipated in resistor : E R = E vdd E C = 1 2 C V 2 DD Also,E R = i 2 R (t)rdt = i R (t) V v DD out Rdt = R => Independent of R V DD ( ) dt d C v out Energy dissipated per transition? ( V DD v out )dt = 1 2 C V 2 DD Courtesy: Prof. A. Roychowdhury (11) Power Vs. Energy Power(watts) P2 P1 P Same Energy = area under the curve Power(watts) P Time Time Energy is a rate of expenditure of energy v One joule/sec = one watt Both profiles use the same amount of energy at different rates or power (12) 6
7 Dynamic Power vs. Dynamic Energy Dynamic power: consider the rate at which switching (energy dissipation) takes place Voltage VDD VDD VDD i DD C i DD C T Input to CMOS inverter Time Output Capacitor Charging activity factor = fraction of total capacitance that switches each cycle! P dynamic = α C $ # & F " 2 % Output Capacitor Discharging Delay = k C ( V t ) 2 (13) a b c a b c Charge as a State Variable x y x y For computation we should be able to identify if each of the variable (a,b,c,x,y) is in a 1 or a state. We could have used any physical quantity to do that Voltage Current Electron spin Orientation of magnetic field All nodes have some capacitance associated with them We choose voltage distinguish between a and a 1. ogic 1: Cap is charged +  ogic : Cap is discharged (14) 7
8 Higher evel Blocks Vdd Vdd A A B Vdd B C A C A B B A B C A B C (15) Gate Power Dissipation Switching activity depends on the input pattern and combinational logic Consider a à 1 transition on the output of a gate p p 1 Probability gate output was Probability gate output is 1 p = N p 2 n 1 = N 1 N = number of s in the 2 n truth table Example: (16) 8
9 AU Energy Consumption Binvert CarryIn Operation B i n v e r t O p e r a t i o n C a r y I n a b CarryIn AU ess CarryOut Result a 1 a1 b1 CarryIn AU1 ess CarryOut Result1 b 2 1 R e s u l t e s s 3 a2 b2 CarryIn AU2 ess CarryOut CarryIn Result2 C a r r y O u t Can we count the number of transitions in each 1bit AU for an operation? a31 b31 CarryIn AU31 ess Result31 Set Overflow Can we estimate static power? Computing per operation energy (17) Closer ook: A 4bit Ripple Adder A3 B3 A2 B2 A1 B1 A B Carry Cin S3 S2 Critical Path = D XOR +4*(D AND +D OR ) for 4bit ripple adder (9 gate levels) For an Nbit ripple adder Critical Path Delay ~ 2(N1)+3 = (2N+1) Gate delays Activity (and therefore power) is a function of the input data values! S1 S (18) 9
10 Implications cond input clk Combinational ogic clk clk What if I halved the frequency? What if I lower the voltage? How can I reduce the capacitance? We will see later that these two are interrelated!! P dynamic = α C $ # & F " 2 % (19) Static Power Technology scaling has caused transistors to become smaller and smaller. As a result, static power has become a substantial portion of the total power. SOURCE GATE DRAIN Gate eakage Junction eakage Subthreshold eakage P static = I static (2) 1
11 EnergyDelay Interaction Energy or delay Delay V DD Energy Power State Delay decreases with supply voltage but energy/power increases! P dynamic = α C $ # & F " 2 % EnergyDelay Product (EDP) Target of optimization V DD Delay = k C ( V t ) 2 (21) Static EnergyDelay Interaction leakage or delay leakage delay V th SOURCE GATE DRAIN t ox Delay = k C ( V t ) 2 Static energy increases exponentially with decrease in threshold voltage Delay increases with threshold voltage (22) 11
12 Temperature Dependence As temperature increases static power increases 1 P static = N K design I leakage Supply voltage #Transistors Technology Dependent Normalized eakage Current I leakage = F(Temp) 1 J. Butts and G. Sohi, A Static Power Model for Architects, MICRO 2 (23) The World Today Yesterdayà scaling to minimize time (max F)! P dynamic = α C $ # & F " 2 % Delay = k C ( V t ) 2 Maximum performance (minimum time) is too expensive in terms of power v Imaging scaling voltage by.7 and frequency by 1.5 à how does dynamic power scale? Today: trade/balance performance for power efficiency (24) 12
13 Transistor size v Affects capacitance (C ) Factors Affecting Power Rise times and fall times (delay) v Affects short circuit power (not in this course) Threshold voltage v Affects leakage power Temperature v Affects leakage power Switching activity v Frequency (F) and number of switching transistors ( α )! P dynamic = α C $ V # & F Delay = k C dd " 2 % ( V t ) 2 Vin Vdd PMOS NMOS Ground (25) Vout ow Power Design: Options?! P dynamic = α C $ # & F " 2 % Delay = k C ( V t ) 2 Reduce v Increases gate delay v Note that this means it reduces the frequency of operation of the processor! Compensate by reducing threshold voltage? v Increase in leakage power Reduce frequency v Computation takes longer to complete v Consumes more energy (but less power) if voltage is not scaled (26) 13
14 Example HW Only (Boost) SWVisible CPU Pstate Pb Voltage (V) 1 Freq (MHz) 24 Pb P P P P P AMD Trinity A158 APU: 1W TDP (27) Optimizing Power vs. Energy Maximize battery life! minimize energy Thermal envelopes! minimize peak power Example: (28) 14
15 Modeling Component Energy Peruse energies can be estimated from Gate level designs and analyses Circuitlevel designs and analyses Implementation and measurement There are various opensource tools for analysis Mentor, Cadence, Synopsys, etc. Hardware Design Technology Parameters Circuitlevel Estimation Tool Estimation Results: Area, Energy, Timing, etc. (29) Datapath Elements CPU/Core CoProcessor 1 $ $1 $ $1 SIMD Registers XMM XMM1 $31 $31 XMM15 AU Multiply Divide FP AU Vector AU Hi o Can we measure (offline) the average energy consumed by each component? Can we measure (offline) the average energy consumed by each component? (3) 15
16 A Simple Power Model for Processors Per instruction energy measurements v Permits a software model of energy consumption of a program v Execution time use to assess power requirements A first order model of energy consumption for software v A table of energy consumption per instruction v More on this later! (31) What About Wires? umped RC Model R line = r l Resistance per unit length 1 2 C line τ = 1 2 rc l C line C line = c l Capacitance per unit length We will not directly address delay or energy expended in the interconnect in this class v Simple architecture model: lump the energy/power with the source component (32) 16
17 Summary Two major classes of energy/power dissipation static and dynamic Managing energy is different from managing power à leads to different solutions Technology plays a major role in determining relative costs Energy of components are often estimated using approximate models of switching activity (33) Explain the difference between energy dissipation and power dissipation Study Guide Distinguish between static power dissipation and dynamic power dissipation What is the impact of threshold voltage on the delay and energy dissipation? As you increase the supply voltage what is the behavior of the delay of logic elements? Why? As you increase the supply voltage what is the behavior of static and dynamic energy and static and dynamic power of logic elements? (34) 17
18 Study Guide (cont.) Do you expect the 1 and 1 transitions at the output of a gate to dissipate the same amount of energy? For a mobile device, would you optimize power or energy? Why? What are the consequences of trying to optimize one or the other? Why does the energy dissipation of a 32bit integer adder depend on the input values? If I double the processor clock frequency and run the same program will it take less or more energy? (35) Study Guide (cont.) When the chip gets hotter, does it dissipate more or less energy? Why? How can you reduce dynamic energy of a combinational logic circuit? How can you reduce static energy of a combinational logic circuit? (36) 18
19 Glossary Dynamic Energy Dynamic Power oad capacitance Static Energy Static Power Time constant Threshold voltage Switching delay Switching energy (37) 19
PassTransistor Logic. Topics. NMOSOnly Logic. PassTransistor Logic. Resistance of Transmission Gate. PassTransistor Logic.
Topics Transmission Gate Passtransistor Logic 3 March 2009 1 3 March 2009 2 NMOSOnly Logic Example: AND Gate 3 March 2009 3 3 March 2009 4 Resistance of Transmission Gate XOR 3 March 2009 5 3 March 2009
More informationAnalysis (III) Low Power Design. Kai Huang
Analysis (III) Low Power Design Kai Huang Chinese new year: 1.3 billion urban exodus 1/28/2014 Kai.Huang@tum 2 The interactive map, which is updated hourly The thicker, brighter lines are the busiest routes.
More informationOutline. Power and Energy Dynamic Power Static Power. 4th Ed.
Lecture 7: Power Outline Power and Energy Dynamic Power Static Power 2 Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Energy: Average
More informationIndex i xi xv xxvi. Abstract List of Tables List of Figures Glossary. Page.No CHAPTER 1 INTRODUCTION
iv Abstract List of Tables List of Figures Glossary Index i xi xv xxvi CHAPTER 1 INTRODUCTION 1.1 Introduction 1.2 Formulation of the problem 1.3 Objectives 1.4 Methodology 1.5 Contribution of the Thesis
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
Introduction to TransistorLevel Logic Circuits Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed state
More informationChapter 10 Advanced CMOS Circuits
Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pullup inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in
More informationHere we introduced (1) basic circuit for logic and (2)recent nanodevices, and presented (3) some practical issues on nanodevices.
Outline Here we introduced () basic circuit for logic and (2)recent nanodevices, and presented (3) some practical issues on nanodevices. Circuit Logic Gate A logic gate is an elemantary building block
More informationLogic Design. Implementation Technology
Logic Design Implementation Technology Outline Implementation of logic gates using transistors Programmable logic devices Complex Programmable Logic Devices (CPLD) Field Programmable Gate Arrays (FPGA)
More informationNMOS Digital Circuits. Introduction Static NMOS circuits Dynamic NMOS circuits
NMOS Digital Circuits Introduction Static NMOS circuits Dynamic NMOS circuits Introduction PMOS and NMOS families are based on MOS transistors with induced channel of p, respectively n NMOS circuits mostly
More informationEE612: Lecture 25: CMOS Circuits: Part 2
EE612: Lecture 25: CMOS Circuits: Part 2 Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006 NCN www.nanohub.org Lundstrom EE612 F06 1 Outline 1) Review
More informationCMOS Power Consumption
CMOS Power Consumption Lecture 13 18322 Fall 2003 Textbook: [Sections 5.5 5.6 6.2 (p. 257263) 11.7.1 ] Overview Lowpower design Motivation Sources of power dissipation in CMOS Power modeling Optimization
More informationSemiconductor Memories
Chapter 8 Semiconductor Memories (based on Kang, Leblebici. CMOS Digital Integrated Circuits 8.1 General concepts Data storage capacity available on a single integrated circuit grows exponentially being
More informationBinary Adder. sum of 2 binary numbers can be larger than either number need a carryout to store the overflow
Binary Addition single bit addition Binary Adder sum of 2 binary numbers can be larger than either number need a carryout to store the overflow HalfAdder 2 inputs (x and y) and 2 outputs (sum and carry)
More informationEEC 118 Spring 2011 Midterm
EEC 118 Spring 2011 Midterm Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis May 2, 2011 This examination is closed book and closed notes. Some formulas
More informationEmbedded Systems. 9. Low Power Design
Embedded Systems 9. Low Power Design Lothar Thiele 91 Contents of Course 1. Embedded Systems Introduction 2. Software Introduction 7. System Components 10. Models 3. RealTime Models 4. Periodic/Aperiodic
More informationCHAPTER 14 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 4 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 4. Digital Logic Inverters 4. The CMOS Inverter 4.3 Dynamic Operation of the CMOS Inverter 4.4 CMOS LogicGate Circuits 4.5 Implications of Technology
More informationNEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.
CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floatingpoint unit and for address generation in case of cache
More informationDESIGN AND PERFORMANCE ANALYSIS OF CMOS FULL ADDER WITH 14 TRANSISTOR
DESIGN AND PERFORMANCE ANALYSIS OF CMOS FULL ADDER WITH 14 TRANSISTOR 1 Ruchika Sharma, 2 Rajesh Mehra 1 ME student, NITTTR, Chandigarh,India 2 Associate Professor, NITTTR, Chandigarh,India 1 just_ruchika016@yahoo.co.in
More informationClass 11: Transmission Gates, Latches
Topics: 1. Intro 2. Transmission Gate Logic Design 3. XGate 2to1 MUX 4. XGate XOR 5. XGate 8to1 MUX 6. XGate Logic Latch 7. Voltage Drop of nch XGates 8. nch Pass Transistors vs. CMOS XGates
More informationCombinational Logic Building Blocks and Bus Structure
Combinational Logic Building Blocks and Bus Structure ECE 5A Winter 0 Reading Assignment Brown and Vranesic Implementation Technology.8 Practical Aspects.8.7 Passing s and 0s Through Transistor Switches.8.8
More informationCapacitors and RC Circuits
Chapter 6 Capacitors and RC Circuits Up until now, we have analyzed circuits that do not change with time. In other words, these circuits have no dynamic elements. When the behavior of all elements is
More informationNovel Approaches to Low Leakage and Area Efficient VLSI Design. Professor Md. Shafiqul Islam, PhD
Novel Approaches to Low Leakage and Area Efficient VLSI Design A Thesis Submitted to the Department of Electrical and Electronic Engineering in Partial Fulfillment of the Requirements for the Degree of
More informationPrinciples of VLSI Review. CMOS Transistors (Ntype)
Principles of VSI Review Static CMOS ogic Design Delay Models Power Consumption CMOS Technology Scaling R 9/00 1 g s CMOS Transistors (Ntype) Ntype (NMOS) transistor  can think of it as a switch. g:
More informationSample Final Exam FinalDay, FinalMonth, FinalYear ELEC4708: Advanced Digital Electronics Department of Electronics, Carleton University
0 0 Sample Final Exam FinalDay, FinalMonth, FinalYear ELEC4708: Advanced Digital Electronics Department of Electronics, Carleton University Instructor: Maitham Shams Exam Duration: 3 hour Booklets: None
More informationPass Transistor Circuits
October 2007 Outline I 1 2 3 4 We can view the complementary CMOS gate as switching the output pin to one of power or ground. We can view the complementary CMOS gate as switching the output pin to one
More informationInternational Journal of Electronics and Computer Science Engineering 1482
International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN 22771956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant
More informationLecture 31. Inverters and Combinational Logic
Lecture 3 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas Email: k.masselos@imperial.ac.uk Lecture 31 Based on slides/material
More informationMcPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures
McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Sheng Li, Junh Ho Ahn, Richard Strong, Jay B. Brockman, Dean M Tullsen, Norman Jouppi MICRO 2009
More informationNMOS Inverter. MOSFET Digital Circuits. Chapter 16. NMOS Inverter. MOSFET Digital Circuits
Chapter 16 MOSFET Digital Circuits In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology of choice. Later the design flexibility and other advantages of the CMOS were
More informationBiCMOS Logic Gates. University of Connecticut 224
BiCMOS Logic Gates University of Connecticut 224 BiCMOS  Best of Both Worlds? CMOS circuitry exhibits very low power dissipation, but Bipolar logic achieves higher speed and current drive capability.
More informationChapter 2 Fundamentals of Adiabatic Logic
Chapter 2 Fundamentals of Adiabatic Logic 2.1 The Charging Process in Adiabatic Logic Compared to Static CMOS First the energy dissipation caused by switching of a simple CMOS inverter as shown in Fig.
More informationLecture 3: MOS Transistors Switch and Gate Logic
Lecture 3: MOS Transistors Switch and Gate Logic Mark Horowitz Modified by Azita Emami Computer Systems Laboratory Stanford University azita@stanford.edu MAH, AEN EE271 Lecture 3 1 Overview Reading W&E
More informationDesign of a Low Power FourBit Binary Counter Using Enhancement Type Mosfet
Design of a Low Power FourBit Binary Counter Using Enhancement Type Mosfet Praween Sinha Department of Electronics & Communication Engineering Maharaja Agrasen Institute Of Technology, Rohini sector 22,
More informationPass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches).
Pass Gate Logic n alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Switch Network Regeneration is performed via a buffer. We have already
More informationPERFORMANCE EVALUATION OF 4:1 MULTIPLEXER USING DIFFERENT DOMINO LOGIC STYLES
International Journal of Electronics and Communication Engineering and Technology (IJECET) Volume 7, Issue 4, JulyAugust 2016, pp. 20 31, Article ID: IJECET_07_04_003 Available online at http://www.iaeme.com/ijecet/issues.asp?jtype=ijecet&vtype=7&itype=4
More informationECE124 Digital Circuits and Systems Page 1
ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly
More informationMetal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs
The MOSFET Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Assets: High integration density and relatively simple manufacturing
More informationIntroduction to CMOS VLSI Design (E158) Lecture 3: Transistors and Gates
Harris Introduction to CMOS VLSI Design (E158) Lecture 3: Transistors and Gates David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH
More informationOutline. nmos Transistor. MOS Capacitor. Transistors and Scaling Introduction to Nanotechnology. Transistor theory Transistor reality Scaling
15398 ntroduction to Nanotechnology Transistors and Scaling Transistor theory Transistor reality Scaling Outline Seth Copen Goltein seth@cs.cmu.edu CMU Adapted from ntro to CMOS S Design, Harris lecture6
More informationThreePhase DualRail PreCharge Logic
Infineon Page 1 CHES 2006  Yokohama ThreePhase DualRail PreCharge Logic L. Giancane, R. Luzzi, A. Trifiletti {marco.bucci, raimondo.luzzi}@infineon.com {giancane, trifiletti}@die.mail.uniroma1.it Summary
More informationEfficient Interconnect Design with Novel Repeater Insertion for Low Power Applications
Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,
More informationCMOS Binary Full Adder
CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry   Table of Contents Key Terminology...  Introduction... 3  Design Architectures...
More informationCMOS Digital Integrated Circuits Analysis and Design
CMOS Digital Integrated Circuits nalysis and Design Chapter 7 Combinational MOS Logic Circuits 1 Introduction Combination logic circuit Performing Boolean operations between input and put Static and dynamic
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2016 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR Latch " DLatch! Timing Hazards! Dynamic
More informationExpanding the Synopsys PrimeTime Solution with Power Analysis
Expanding the Synopsys PrimeTime Solution with Analysis Gordon Yip, Product Marketing Manager, Synopsys, Inc. June 2006 Introduction Design closure in today s advanced designs requires a delicate balance
More informationField effect transistors
Field effect transistors Junction FETs MetalOxide Semiconductor FETs type N type P enhancement depletion type N type P type N type P Slide 1 Junction field effect transistor  JFET Construction and circuits
More informationLFSR BASED COUNTERS AVINASH AJANE, B.E. A technical report submitted to the Graduate School. in partial fulfillment of the requirements
LFSR BASED COUNTERS BY AVINASH AJANE, B.E A technical report submitted to the Graduate School in partial fulfillment of the requirements for the degree Master of Science in Electrical Engineering New Mexico
More information8 Bit DigitaltoAnalog Converter
8 Bit DigitaltoAnalog Converter Tim Adams ttexastim@hotmail.com Richard Wingfield wingfiel@cs.utah.edu 8 Bit DAC Project Description: For this project, an 8 bit digitaltoanalog converter was designed.
More informationInternational Conference on Science, Technology, Engineering & Management [ICONSTEM 15]
An Enhanced Technique for Leakage Reduction in 8:1 Domino Multiplexer S. Lakshmi Narayanan*, R. Jaya Nandhini, Dr. ReebaKorah Department of ECE, Anna University, Chennai,Tamil Nadu, India. *Corresponding
More informationl What have discussed up until now & why: l C Programming language l More lowlevel then Java. l Better idea about what s really going on.
CS211 Computer Architecture l Topics Digital Logic l Transistors (Design & Types) l Logic Gates l Combinational Circuits l KMaps Class Checkpoint l What have discussed up until now & why: l C Programming
More informationSequential 4bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More information1 An introduction to domino logic
1 n introduction to domino logic 1.1 CMOS and NMOS y the late 1970s complementary metal oxide semiconductor (CMOS) started to become the process of choice for digital semiconductor designs. CMOS had originally
More informationGates, Circuits, and Boolean Algebra
Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks
More informationExperiment 5. Arithmetic Logic Unit (ALU)
Experiment 5 Arithmetic Logic Unit (ALU) Objectives: To implement and test the circuits which constitute the arithmetic logic circuit (ALU). Background Information: The basic blocks of a computer are central
More informationCMOS Digital Circuits
CMOS Digital Circuits Types of Digital Circuits Combinational The value of the outputs at any time t depends only on the combination of the values applied at the inputs at time t (the system has no memory)
More informationComparators. Chapter 10
Comparators Chapter 10 Introduction The second most widely used circuit block are comparators after OpAmps. They are used extensively in A/D converters and other signal processing applications. 10.1.1
More informationEEC 116 Lecture #6: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #6: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 extended, same due date as Lab 4 HW4 issued today Amirtharajah/Parkhurst,
More informationKeywords: SAEN (sense enable signal), BB (bit bar), BL (bit line), SOC (system on chip)
Volume 4, Issue 5, May 2014 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Analytical Study
More informationGates and Logic: From switches to Transistors, Logic Gates and Logic Circuits
Gates and Logic: From switches to Transistors, Logic Gates and Logic Circuits Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University See: P&H ppendix C.2 and C.3 (lso, see C.0 and
More informationHow many laws are named after Kirchhoff?
Chapter 32. Fundamentals of Circuits Surprising as it may seem, the power of a computer is achieved simply by the controlled flow of charges through tiny wires and circuit elements. Chapter Goal: To understand
More informationCMOS Inverter. MetalOxide Semiconductor Field Effect Transistor. NChannel MOS (NMOS) Transistor. PChannel MOS (PMOS) Transistor
MetalOxide Semiconductor Field Effect Transistor NChannel MOS (NMOS) Transistor PChannel MOS (PMOS) Transistor Complementary MetalOxide Semiconductor CMOS Inverter 1 CMOS Inverter : Low Input ON OFF
More informationIntroduction to CMOS VLSI Design. Lecture 6: Wires. David Harris
Introduction to CMOS VLSI Design Lecture 6: Wires David Harris Harvey Mudd College Spring 2004 Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors
More informationAdvanced VLSI Design Combinational Logic Design
Combinational Logic: Static versus Dynamic Static: t every point in time (except during the switching transient), each gate output is connected to either V DD or V SS via a lowresistance path. Slower
More informationDesign of carry save adder using transmission gate logic
ABSTRACT NOVATEUR PUBLICATIONS Design of carry save adder using transmission gate logic J.Princy Joice Dept of ECE/Sathyabama University, Chennai/Tamilnadu/India M.Anitha Dept of ECE/Sathyabama University,
More information1.5MHz, 900mA Synchronous StepDown Converter
1.5MHz, 900mA Synchronous StepDown Converter FEATURES High Efficiency  Up to 95% Guaranteed 900mA Output Current 2.5V to 5.5V Input Voltage Range 1.5MHz Constant Frequency Operation No external Schottky
More informationUnit 2. Electronic circuits and logic families
Unit 2. Electronic circuits and logic families Digital Electronic Circuits (Circuitos Electrónicos Digitales) E.T.S.. nformática Universidad de Sevilla Sept. 23 Jorge Juan 223 You are
More informationLow Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 14 Pass Transistor Logic Circuits  I Hello
More informationAn Efficient Implementation of Multiplexer Based FlipFlop in Subthreshold Region
An Efficient Implementation of Multiplexer Based FlipFlop in Subthreshold Region Bhanu Prasad Nimmagadda 1, M. Murali Krishna 2, Ch. Sumanth Kumar 3 and G.V.K.Sharma 4 1 Department of ECE, GITAM Institute
More informationLowVoltage SwitchedOpAmp Circuits. Term Paper
University of Toronto Department of Electrical and Computer Engineering LowVoltage SwitchedOpAmp Circuits Analog Circuit Design I ECE1352F Term Paper University of Toronto Electronics Group Toronto,
More informationA NEW LOW POWER HIGH PERFORMANCE FLIPFLOP
A NEW LOW POWER HIGH PERFORMANCE FLIPFLOP Ahmed Sayed and Hussain AlAsaad epartment of Electrical and Computer Engineering University of California avis, CA, U.S.A. ABSRAC Low power flipflops are crucial
More informationEnhancement Mode MOSFET Circuits
Engineering Sciences 154 Laboratory Assignment 4 Enhancement Mode MOSFET Circuits Note: This is quite a long, but very important laboratory assignment. Take enough time  at least two laboratory sessions
More informationDigital Circuits. Frequently Asked Questions
Digital Circuits Frequently Asked Questions Module 1: Digital & Analog Signals 1. What is a signal? Signals carry information and are defined as any physical quantity that varies with time, space, or any
More informationLogic Gates & Operational Characteristics
Logic Gates & Operational Characteristics NOR Gate as a Universal Gate The NOR gate is also used as a Universal Gate as the NOR Gate can be used in a combination to perform the function of a AND, OR and
More informationNotes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits
Notes about Small Signal Model for EE 40 Intro to Microelectronic Circuits 1. Model the MOSFET Transistor For a MOSFET transistor, there are NMOS and PMOS. The examples shown here would be for NMOS. Figure
More informationLow Power AMD Athlon 64 and AMD Opteron Processors
Low Power AMD Athlon 64 and AMD Opteron Processors Hot Chips 2004 Presenter: Marius Evers Block Diagram of AMD Athlon 64 and AMD Opteron Based on AMD s 8 th generation architecture AMD Athlon 64 and AMD
More informationDynamic Combinational Circuits
Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic npcmos (zipper CMOS) James Morizio 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:
More informationSwitchedCapacitor Circuits. Basic Building Blocks
SwitchedCapacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationSystem on Chip Design. Michael Nydegger
Short Questions, 26. February 2015 What is meant by the term nwell process? What does this mean for the ntype MOSFETs in your design? What is the meaning of the threshold voltage (practically)? What
More informationPrinciples of VLSI Design Introduction
Principles of VLSI Design Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text CMOS VLSI Design: A Circuits and Systems Perspective, Third Edition. by Neil H.E. Weste and David Harris.
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles or any text in boolean algebra Introduction We could design at the level of irsim
More informationModule 4 : Propagation Delays in MOS Lecture 16 : Propagation Delay Calculation of CMOS Inverter
Module 4 : Propagation Delays in MOS Lecture 16 : Propagation Delay Calculation of CMOS Inverter Objectives In this lecture you will learn the following Few Definitions Quick Estimates Rise and Fall times
More informationChapter 02 Logic Design with MOSFETs
Introduction to VLSI Circuits and Systems 路 論 Chapter 02 Logic Design with MOSFETs Dept. of Electronic Engineering National ChinYi University of Technology Fall 2007 Outline The Fundamental MOSFETs Ideal
More informationSELFOSCILLATING HALFBRIDGE DRIVER
Features n Floating channel designed for bootstrap operation Fully operational to +600V Tolerant to negative transient voltage dv/dt immune n Undervoltage lockout n Programmable oscillator frequency 1
More informationSupertex inc. MD1820. High Speed, Four Channel MOSFET Driver with NonInverting Outputs. Features
inc. High Speed, Four Channel MOSFET Driver with NonInverting Outputs Features Noninverting, four channel MOSFET driver.0ns rise and fall time 2.0A peak output source/sink current 1. to 5.0V input CMOS
More information4. CMOS Transistor Theory
4. CMOS Transistor Theory 1 4. CMOS Transistor Theory Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016 September 7, 2016 ECE Department,
More informationLM555 Timer MOS Inverter MOSFET Analog Switch SampleandHold Amplifier 2:1 Analog Multiplexer
LM555 Timer MOS Inverter MOSFET Analog Switch SampleandHold Amplifier :1 Analog Multiplexer ECE 04 Lab 4 Objective The purpose of this lab is to gain familiarity with circuits that are useful in "mixedsignal"
More informationStepper Motor Drive Circuit
Stepper Motor Drive Circuit FEATURES Halfstep and Fullstep Capability Bipolar Constant Current Motor Drive Builtin Fast Recovery Schottky Commutating Diodes Wide Range of Current Control 51000mA Wide
More information1. Memory technology & Hierarchy
1. Memory technology & Hierarchy RAM types Advances in Computer Architecture Andy D. Pimentel Memory wall Memory wall = divergence between CPU and RAM speed We can increase bandwidth by introducing concurrency
More informationDESIGN OF LOW POWER SRAM USING NEGATIVE BIAS TEMPERATURE INSTABILITY TECHNIQUE
DESIGN OF LOW POWER SRAM USING NEGATIVE BIAS TEMPERATURE INSTABILITY TECHNIQUE 1 SWATHI TANGELLA, 2 PREMA KUMAR MEDAPATI 1 M.Tech Student, Department of ECE, Shri Vishnu Engineering College for Women 2
More informationAdiabatic Logic. Yasmine Badr NanoCAD Lab. A major part of the contents is from Reference 1
Adiabatic Logic Yasmine Badr NanoCAD Lab A major part of the contents is from Reference 1 1 Terminology Reversible logic: circuits that have onetoone mapping between vectors of inputs and outputs Adiabatic
More informationRipple Carry and Carry Lookahead Adders
Ripple Carry and Carry Lookahead Adders 1 Objectives Design ripple carry and carry lookahead (CLA) adders. Use VHDL CAD tools. Use hierarchical design techniques. Model and simulate combinational logic
More informationIPS511/IPS511S FULLY PROTECTED HIGH SIDE POWER MOSFET SWITCH. Load
Data Sheet No.PD 6155 IPS511/IPS511S FUY PROTECTED IG SIDE POWER MOSFET SWITC Features Over temperature protection (with autorestart) Shortcircuit protection (current limit ) Active clamp E.S.D protection
More informationComparison of power consumption of 4bit binary counters with various state encodings including gray and onehot codes
1 Comparison of power consumption of 4bit binary counters with various state encodings including gray and onehot codes Varun Akula, Graduate Student, Auburn University, Dr. Vishwani D. Agrawal, James
More informationOutline. Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. 4th Ed.
Lecture 14: Wires Outline Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters 2 Introduction Chips are mostly made of wires called interconnect
More information1.1 Silicon on Insulator a brief Introduction
Table of Contents Preface Acknowledgements Chapter 1: Overview 1.1 Silicon on Insulator a brief Introduction 1.2 Circuits and SOI 1.3 Technology and SOI Chapter 2: SOI Materials 2.1 Silicon on Heteroepitaxial
More informationGuide to Power Measurement A Cadence EDA Tools Help Document
Document Contents Introduction General Steps Static Power Dynamic and Average Power Peak Power Energy Measuring Power using Voltage and Current Guide to Power Measurement A Cadence EDA Tools Help Document
More informationDigital VLSI design. Lecture 2: Complementary Metal Oxide Semiconductor (CMOS) Chips
Digital VLSI design Lecture 2: Complementary Metal Oxide Semiconductor (CMOS) Chips What will we learn? How integrated circuits work How to design chips with millions of transistors Ways of managing the
More informationPhysics 219 Fall, 2005 LabNotes 11 Combinational Logic. Table of Contents
Physics 219 Fall, 2005 LabNotes 11 Combinational Logic Table of Contents Friday, December 2... 2 Digital uilding locks... 2 Combinational Logic... 3 n example of combinational logic: car s warning buzzer...
More information9. Memory Elements and Dynamic Logic
9. Memory Elements and RS Flipflop The RSflipflop is a bistable element with two inputs: Reset (R), resets the output Q to 0 Set (S), sets the output Q to 1 2 RSFlipflops There are two ways to implement
More informationDESIGN CHALLENGES OF TECHNOLOGY SCALING
DESIGN CHALLENGES OF TECHNOLOGY SCALING IS PROCESS TECHNOLOGY MEETING THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SUCCESSIVE
More information