Programmable Logic Devices Verilog Design Examples CMPE 415

Transcription

1 Buildig Blocks Digital systems cosist of 2 mai parts: the datapath ad cotrol circuits. Datapath: stores ad maipulates data ad icludes compoets such as registers, shift registers, couters, multiplexers, decoders, adders, etc. Cotrol: a FSM that cotrols the datapath elemets. We ve talked about may datapath buildig blocks -- we start here by discussig a few more that are useful i digital system desig. i Clk eable D Q out module rege(i, Clk, reset, eable, Q); parameter = 8; iput [-:] i; iput Clk, reset, eable; output reg [-] Q; Clk or egedge Reset) if (reset == ) Q <= ; else if (eable) Q <= i; module The code describes D FFs with a asychroous reset ad a eable iputs. The eable iput allows selective loadig of the FFs. (/6/7)

2 Buildig Blocks Left shift register with parallel load ad eable iputs. par_load eable i i w D Q D Q Clk Clk out out module shiftle(i, par_load, eable, w, Clk, Q); parameter = 4; iput [-:] i; iput par_load, eable, w, Clk; output reg [-] Q; iteger k; 2 (/6/7)

3 Buildig Blocks Clk) begi if (par_load) Q <= i; else if (eable) begi Q[] <= w; // o-blockig -- all RHS sampled FIRST. for (k = ; k < ; k = k+) Q[k] <= Q[k-]; module SRAM: select data data 3 (/6/7)

4 Bit Coutig Cout the umber of bits i a register that have the value. reset B = ; while A /= do S if a = the B <- B = B + ; Load A if Right-shift A; s while; S2 shift right A s S3 doe B <- B + Whe S2 is etered, A is NOT shifted util the followig clock cycle -- we will set a eable sigal to allow this. A == a While s ==, exteral operatios are loadig register A 4 (/6/7)

5 Bit Coutig module bitcout (Clk, reset, load_a, A_ready, data, ct, doe); iput Clk, reset, load_a, A_ready; iput [7:] data; output reg [3:] B; output reg doe; wire [7:] A; wire A_zero; reg [:] cur_state, ext_state; reg e_shift, ic_b, iit_b; parameter S = 2 b, S2 = 2 b, S3 = 2 b; cur_state, A_zero) begi: State_table case (cur_state) S: if (!A_ready) ext_state = S; else ext_state = S2; S2: if (A_zero == ) ext_state = S2; else ext_state = S3; S3: if (A_ready) ext_state = S3; else ext_state = S; case default: ext_state = 2 bxx; // Next state logic 5 (/6/7)

6 Bit Coutig Clk or egedge reset) begi: State_flipflops if (reset == ) cur_state <= S; else cur_state <= ext_state; or A[]) begi: FSM_outputs e_shift = ; ic_b = ; iit_b = ; doe = ; case (y) S: iit_b = ; S2: begi e_shift = ; if (A[]) ic_b = ; else ic_b = ; S3: doe = ; case // Sequetial logic // Combo logic for output sigals // Eablig the shift cotrol sigal // is asserted o eterig state S2 -- // so it s ot available util ext Clk Same is true for ic_b sigal -- they are ot set/uset util state S2 is active so actios take by assertig sigals i this state do t take place util ext Clk. 6 (/6/7)

7 Bit Coutig Clk or egedge reset) if (reset) B <= ; else if (iit_b) B <= ; else if (ic_b) B <= B + ; // Seq. logic for cter B shiftre shift_a(data, load_a, e_shift, b, Clk, A) assig A_zero = ~ A; module // RIGHT shifter Note that reset is NOT used to iitialize B after the iitial reset of the machie durig power up. A separate sigal iit_b is used to do this whe the FSM trasitios from state S3 to S. 7 (/6/7)

8 The example illustrates divisio usig a the traditioal log-had approach B Q A R 2-bit shift register with R cocat with A R = ; for i = to - do left-shift R A; if R >= B the q i = ; R = R - B; else q i = ; if; for; Pseudo-code illustrates operatio where A is left shifted, oe bit at a time, ito R ad the R (ot R A) is compared with B. Q is computed by left shiftig a or ito the least sigificat digit based o the compariso of R with B, i.e., if R >= B, shift a, else a. The remaider, R, is what remais after clks. 8 (/6/7)

9 We use a left-shift register with parallel load for R to hadle two cases. If R becomes greater tha B (remember, A is shifted ito R oe bit at a time), the the ew value of R is R - B. If R is less tha B, tha we shift the MSB bit of A ito R. I either case, the R iputs to the subtractor must be drive with the low order - bits of the register R cocateated with the MSB of A. R iputs of adder = R[-2:] MSB(A) However, R itself is R[-:] whe the divisio is completed. To accomplish this, we keep the MSB(A) i a separate -bit register: - R MSB(A) c out + c i 9 (/6/7)

10 Register A is used to store the quotiet by left shiftig as A is shifted out: Clk cycle R rr A/Q Load A, B Shift left Shift left, Q <- 2 Shift left, Q <- 3 Shift left, Q <- 4 Shift left, Q <- 5 Subtract, Q <- 6 Subtract, Q <- 7 Subtract, Q <- 8 Subtract, Q <- At clk cycle, A s MSB is left shifted ito rr, yieldig R rr =, which is smaller tha B (). At clk cycle, rr is left shifted ito R while A s MSB moves ito rr. Also, a is shifted ito the LSB of A to idicate a i the quotiet. At clk cycle 4, R rr =, which is > B, so i clk cycle 5, the result of subtractio _ - = _ is loaded ito R. (/6/7)

11 s S3 doe load_r Also load A&B reset S Rmux = load_ct e_shift_r s e_shift_a, rr mux S2 e_shift_r, rr mux e_shift_a, Rmux c out load_r e_ct ct ==? (/6/7)

12 Hardware requiremets: Register for B. Two shift registers for A ad R. A subtractor for R-B (implemeted as a adder with carry = ad B complemeted). The c out of this module is if R >= B. c out coected to the serial iput of the shift reg that stores Q. A multiplexer feedig the iput to R because it is loaded with i state S ad from the output of the adder i S3. A dow couter to implemet ct. A NOR gate to determie whe C ==. 2 (/6/7)

13 load_a DataA load_b DataB e_shift_a Clk L E Left-shift reg w Clk E reg if c out == load_r = - load_r e_shift_r Clk c out + Rmux r r L E c i Left-shift reg R w missig: cter, NOR gate Clk rr Q D rr mux q - Q 3 (/6/7)

14 module divider (Clk, reset, s, load_a, load_b, DataA, DataB, R, Q, doe); parameter = 8, log = 3; iput Clk, reset, s, load_a, load_b; iput [-:] DataA, DataB; output [-:] R, Q; output reg doe; wire Cout, ct_zero, rr; wire [-:] DataR; wire [:] Sum; reg [:] cur_state, ext_state; wire [-:] A, B; wire [log-:] ct; reg e_shift_a, Rmux, load_r, e_shift_r, rrmux, load_ct, e_ct; parameter S = 2 b, S2 = 2 b, S3 = 2 b; 4 (/6/7)

15 cur_state, ct_zero) begi: State_table case (cur_state) S: if (s == ) ext_state = S; else ext_state = S2; S2: if (ct_zero == ) ext_state = S2; else ext_state = S3; S3: if (s == ) ext_state = S3; else ext_state = S; case default: ext_state = 2 bxx; Clk or egedge reset) begi: State_flipflops if (reset == ) cur_state <= S; else cur_state <= ext_state; // Next state logic // Sequetial logic 5 (/6/7)

16 or s or Cout or ct_zero) // Combo logic for begi: FSM_outputs // output sigals load_r = ; e_shift_r = ; rrmux = ; load_ct = ; e_ct = ; e_shift_a = ; case (y) S: begi load_ct = ; e_shift_r = ; if (s == ) begi load_r = ; rrmux = ; else begi load_r = ; e_shift_a =, rrmux = ; S2: begi Rmux = ; e_shift_r = ; rrmux = ; e_shift_a = ; if (Cout) load_r = ; else load_r = ; if (ct_zero == ) e_ct = ; S3: doe = ; case else e_ct = ; 6 (/6/7)

17 // Datapath rege RegB(DataB, Clk, reset, e_shift_b, B); defparam RegB. = ; shiftle ShiftR(DataR, load_r, e_shift_r, rr, Clk, R); defparam ShiftR. = ; muxdff FF_rr( b, A[-], rrmux, Clk, rr); shiftle ShiftA(DataA, load_a, e_shift_a, Cout, Clk, A); defparam ShiftA. = ; // Shift reg R // Sigle bit // Shift reg A assig Q = A; dowcout Cter(Clk, e_ct, load_ct, Cout); defparam Cter. = log; assig ct_zero = (Cout == ); assig Sum = { b, R[-2:], rr} + { b, ~B} + ; assig Cout = Sum[]; assig DataR = Rmux? Sum : ; module // Output of A is Q oce calc performed // Couter // Adder is + // bits to save // Cout // 2-to- MUXs 7 (/6/7)