ICL232. Features. +5V Powered, Dual RS-232 Transmitter/Receiver. Ordering Information. Applications. Pinout

Transcription

1 ICL Datasheet July, 00 FN00. V Powered, Dual RS Transmitter/Receiver The ICL is a dual RS transmitter/receiver interface circuit that meets all ElA RSC and V. specifications. It requires a single V power supply, and features two onboard charge pump voltage converters which generate V and V supplies from the V supply. The drivers feature true input compatibility, slewratelimited output, and 00Ω poweroff source impedance. The receivers can handle up to 0V, and have a kω to kω input impedance. The receivers also have hysteresis to improve noise rejection. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. DWG. # ICLCPE 0 to 0 Ld PDIP E. ICLCBE 0 to 0 Ld SOIC M. ICLCBET Ld SOIC Tape and Reel M. ICLCBEZ (See Note) ICLCBEZT (See Note) 0 to 0 Ld SOIC (Pbfree) Ld SOIC Tape and Reel (Pbfree) M. M. ICLlPE 0 to Ld PDIP E. ICLlBE 0 to Ld SOIC M. ICLlBET Ld SOIC Tape and Reel M. ICLMJE to Ld CERDIP F. NOTE: Intersil Pbfree plus anneal products employ special Pbfree material sets; molding compounds/die attach materials and 0% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD00. Features Meets All RSC and V. Specifications Requires Only Single V Power Supply Onboard Voltage Doubler/Inverter Low Power Consumption Drivers ±V Output Swing for V lnput 00Ω Poweroff Source Impedance Output Current Limiting Compatible 0V/µs Maximum Slew Rate Receivers ±0V Input Voltage Range kω to kω Input Impedance 0.V Hysteresis to Improve Noise Rejection All Critical Parameters are Guaranteed Over the Entire Commercial, Industrial and Military Temperature Ranges PbFree Plus Anneal Available (RoHS Compliant) Applications Any System Requiring RS Communications Port Computer Portable and Mainframe Peripheral Printers and Terminals Portable Instrumentation Modems Dataloggers Pinout ICL (PDIP, CERDIP, SOIC) TOP VIEW C V C T OUT C R IN C R OUT V T IN T OUT T IN R IN R OUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 00, 00. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 ICL Functional Diagram V.0µF µf µf T IN T IN R OUT C V TO V VOLTAGE INVERTER V C C V TO V VOLTAGE INVERTER V C V 00kΩ V 00kΩ T T R kω µf µf T OUT T OUT R IN R OUT R kω R IN FN00. July, 00

3 ICL Absolute Maximum Ratings to Ground ( 0.V) < < V V to Ground ( 0.V) < V < V V to Ground V < V < ( 0.V) Input Voltages T IN, T IN (V 0.V) < V IN < (V 0.V) R IN, R IN ±0V Output Voltages T OUT, T OUT (V 0.V) < V TXOUT < (V 0.V) R OUT, R OUT ( 0.V) < V RXOUT < ( 0.V) Short Circuit Duration T OUT, T OUT Continuous R OUT, R OUT Continuous Operating Conditions Temperature Ranges ICLC o C to 0 o C ICLI o C to o C ICLM o C to o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) CERDIP Package PDIP Package N/A SOIC Package N/A Maximum Junction Temperature Plastic Packages o C Ceramic Package o C Maximum Storage Temperature Range o C to 0 o C Maximum Lead Temperature (Soldering s) o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Test Conditions: = V ±%, T A = Operating Temperature Range. Test Circuit as in Figure Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Transmitter Output Voltage Swing, T OUT T OUT and T OUT Loaded with kω to Ground ± ± ± V Power Supply Current, I CC Outputs Unloaded, T A = o C ma T IN, Input Logic Low, V ll 0. V T IN, Input Logic High, V lh.0 V Logic Pullup Current, I P T IN, T IN = 0V 00 µa RS Input Voltage Range, V IN 0 0 V Receiver Input Impedance, R IN V IN = ±V kω Receiver Input Low Threshold, V ln (HL) = V, T A = o C 0.. V Receiver Input High Threshold, V IN (LH) = V, T A = o C.. V Receiver Input Hysteresis, V HYST V Receiver Output Voltage Low, V OL I OUT =.ma V Receiver Output Voltage High, V OH I OUT =.0mA.. V Propagation Delay, t PD RS to TTL 0. µs Instantaneous Slew Rate, SR Transition Region Slew Rate, SR T C L = pf, R L = kω, T A = o C (Notes, ) R L = kω, C L = 00pF Measured from V to V or V to V 0 V/µs V/µs Output Resistance, R OUT = V = V = 0V, V OUT = ±V 00 Ω RS Output Short Circuit Current, I SC T OUT or T OUT Shorted to ± ma NOTES:. Guaranteed by design.. See Figure for definition. FN00. July, 00

4 ICL Test Circuits kω µf C µf C µf C µf C T OUTPUT RS ±0V INPUT T OUT R IN R OUT T IN T IN R OUT.V TO.V INPUT kω T OUTPUT RS ±0V INPUT OUTPUT INPUT INPUT OUTPUT C V C C C V T OUT R IN C V C C C V T OUT R IN T OUT R IN R OUT T IN T IN R OUT R OUT = V IN /I T OUT V IN = ±V A T OUT FIGURE. GENERAL TEST CIRCUIT FIGURE. POWEROFF SOURCE RESISTANCE CONFIGURATION Typical Performance Curves 0 V, V SUPPLY IMPEDANCES (Ω) 00 0 T A = o C EXTERNAL SUPPLY LOAD 00 kω BETWEEN V OR V 0 TRANSMITTER OUTPUT OPEN CIRCUIT V SUPPLY V SUPPLY GUARANTEED OPERATING RANGE 0 INPUT SUPPLY VOLTAGE (V) OUTPUT VOLTAGE ( V ) V ( =.V) V ( =.V) T A = o C TRANSMITTER OPEN CIRCUIT 0 I LOAD (ma) V ( = V) V ( = V) FIGURE. V, V OUTPUT IMPEDANCES vs FIGURE. V, V OUTPUT VOLTAGES vs LOAD CURRENT Pin Descriptions PDIP, CERDIP SOIC PIN NAME DESCRIPTION C External capacitor for internal voltage doubler. V Internally generated V (typical) supply. C External capacitor for internal voltage doubler. C External capacitor internal voltage inverter. C External capacitor internal voltage inverter. V Internally generated V (typical) supply. T OUT RS Transmitter output ±V (typical). R IN RS Receiver input, with internal K pulldown resistor to. FN00. July, 00

5 ICL Pin Descriptions (Continued) PDIP, CERDIP SOIC PIN NAME DESCRIPTION Rout Receiver output. T IN Transmitter input, with internal 00K pullup resistor to. T IN Transmitter input, with internal 00K pullup resistor to. R OUT Receiver output. R IN RS Receiver input, with internal K pulldown resistor to. T OUT RS Transmitter output ±V (typical). Supply Ground. Positive Power Supply V ±% RC OSCILLATOR VOLTAGE DOUBLER VOLTAGE INVERTER S C S V = S C S C C C C S C S S C S FIGURE. DUAL CHARGE PUMP V = (V) Detailed Description The ICL is a dual RS transmitter/receiver powered by a single V power supply which meets all ElA RSC specifications and features low power consumption. The functional diagram illustrates the major elements of the ICL. The circuit is divided into three sections: a voltage doubler/inverter, dual transmitters, and dual receivers Voltage Converter. An equivalent circuit of the dual charge pump is illustrated in Figure. The voltage quadrupler contains two charge pumps which use two phases of an internally generated clock to generate V and V. The nominal clock frequency is khz. During phase one of the clock, capacitor C is charged to. During phase two, the voltage on C is added to, producing a signal across C equal to twice. At the same time, C is also charged to, and then during phase one, it is inverted with respect to ground to produce a signal across C equal to. The voltage converter accepts input voltages up to.v. The output impedance of the doubler (V) is approximately 00Ω, and the output impedance of the inverter (V) is approximately 0Ω. Typical graphs are presented which show the voltage converters output vs input voltage and output voltages vs load characteristics. The test circuit (Figure ) uses µf capacitors for CC, however, the value is not critical. Increasing the values of C and C will lower the output impedance of the voltage doubler and inverter, and increasing the values of the reservoir capacitors, C and C, lowers the ripple on the V and V supplies. T IN, T IN T OUT, T OUT t f 0% % Instantaneous Slew Rate (SR) = (0.) (V OH V OL ) or (0.) (V OL V OH ) t r t f FIGURE. SLEW RATE DEFINITION V OH V OL Transmitters The transmitters are compatible inverters which translate the inputs to RS outputs. The input logic threshold is about % of, or.v for = V. A logic at the input results in a voltage of between V and V at the output, and a logic 0 results in a voltage between V and (V 0.V). Each transmitter input has an internal 00kΩ pullup resistor so any unused input can be left unconnected and its output remains in its low state. The output voltage swing meets the RSC specification of ±V minimum with the worst case conditions of: both transmitters driving kω minimum load impedance, =.V, and maximum allowable operating temperature. The transmitters have an internally limited output slew rate which is less than 0V/µs. The outputs are short circuit protected and can be shorted to ground indefinitely. The powered down output impedance is a t r FN00. July, 00

6 ICL minimum of 00Ω with ±V applied to the outputs and = 0V. V 00kΩ 00Ω T XIN T OUT < T XIN < V < V TOUT < V V FIGURE. TRANSMITTER Receivers The receiver inputs accept up to ±0V while presenting the required kω to kω input impedance even it the power is off ( = 0V). The receivers have a typical input threshold of.v which is within the ±V limits, known as the transition region, of the RS specification. The receiver output is 0V to. The output will be low whenever the input is greater than.v and high whenever the input is floating or driven between 0.V and 0V. The receivers feature 0.V hysteresis to improve noise rejection. R XIN 0V < R XIN < 0V kω FIGURE. RECEIVER R OUT < V ROUT < is generated by driving them through a kω resistor connected to V. INPUTS V C µf C µf TD RTS RD CTS R ICL T R T CTR (0) DATA TERMINAL READY DSRS () DATA SIGNALING RATE SELECT RS INPUTS AND TD () TRANSMIT DATA RTS () REQUEST TO SEND RD () RECEIVE DATA CTS () CLEAR TO SEND SIGNAL GROUND () In applications requiring four RS inputs and outputs (Figure ), note that each circuit requires two charge pump capacitors (C and C) but can share common reservoir capacitors (C and C). The benefit of sharing common reservoir capacitors is the elimination of two capacitors and the reduction of the charge pump source impedance which effectively increases the output swing of the transmitters. C µf kω kω C µf FIGURE. SIMPLE DUPLEX RS PORT WITH CTS/RTS HANDSHAKING T IN, T IN OR R IN, R IN T OUT, T OUT OR R OUT, R OUT t PHL t PLH V OH V OL Average Propagation Delay = t PHL t PLH FIGURE. PROPAGATION DELAY DEFINITION Applications The ICL may be used for all RS data terminal and communication links. It is particularly useful in applications where ±V power supplies are not available for conventional RS interface circuits. The applications presented represent typical interface configurations. A simple duplex RS port with CTS/RTS handshaking is illustrated in Figure. Fixed output signals such as DTR (data terminal ready) and DSRS (data signaling rate select) FN00. July, 00

7 ICL INPUTS C µf TD RTS RD CTS ICL T T R R C µf TD () TRANSMIT DATA RTS () REQUEST TO SEND RD () RECEIVE DATA CTS () CLEAR TO SEND C µf V V C µf V RS INPUTS AND INPUTS C µf DTR DSRS DCD R ICL T T R R C µf DTR (0) DATA TERMINAL READY DSRS () DATA SIGNALING RATE SELECT DCD () DATA CARRIER DETECT R () RING INDICATOR SIGNAL GROUND () FIGURE. COMBINING TWO ICLs FOR PAIRS OF RS INPUTS AND All Intersil U.S. products are manufactured, assembled and tested utilizing ISO000 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN00. July, 00