INTEGRATED CIRCUITS DATA SHEET. 74HC4066; 74HCT4066 Quad bilateral switches. Product specification Supersedes data of 2003 Jun 17.

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1 INTEGRTED CIRCUITS DT SHEET Supersedes data of 2003 Jun Nov 11

2 FETURES Very low ON-resistance: 50 Ω (typical) at = 4.5 V 45 Ω (typical) at = 6.0 V 35 Ω (typical) at = 9.0 V. Complies with JEDEC standard no. 7 ESD protection: HBM EI/JESD B exceeds 2000 V MM EI/JESD exceeds 200 V. Specified from 40 C to +85 C and 40 C to +125 C. GENERL DESCRIPTION The 74HC4066 and 74HCT4066 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4066B. They are specified in compliance with JEDEC standard no. 7. The 74HC4066 and 74HCT4066 have four independent analog switches. Each switch has two input/output pins (pins ny or nz) and an active HIGH enable input pin (pin ne). When pin ne = LOW the belonging analog switch is turned off. The 74HC4066 and 74HCT4066 are pin compatible with the 74HC4016 and 74HCT4016 but exhibit a much lower on-resistance. In addition, the on-resistance is relatively constant over the full input signal range. QUICK REFERENCE DT = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICL SYMBOL PRMETER CONDITIONS 74HC HCT4066 UNIT t PZH /t PZL turn-on time ne to V os C L = 15 pf; R L =1kΩ; = 5 V ns t PHZ /t PLZ turn-off time ne to V os C L = 15 pf; R L =1kΩ; = 5 V ns C I input capacitance pf C PD power dissipation notes 1 and pf capacitance per switch C S maximum switch capacitance 8 8 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+Σ[(C L +C S ) V 2 CC f o ] where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; C S = maximum switch capacitance in pf; = supply voltage in V; N = number of inputs switching; Σ[(C L +C S ) V 2 CC f o ] = sum of the outputs. 2. For 74HC4066 the condition is V I = to. For 74HCT4066 the condition is V I = to 1.5 V Nov 11 2

3 FUNCTION TBLE See note 1. INPUT ne L H SWITCH off on Note 1. H = HIGH voltage level. L = LOW voltage level. ORDERING INFORMTION PCKGE TYPE NUMBER TEMPERTURE RNGE PINS PCKGE MTERIL CODE 74HC4066N 40 C to 125 C 14 DIP14 plastic SOT HCT4066N 40 C to 125 C 14 DIP14 plastic SOT HC4066D 40 C to 125 C 14 SO14 plastic SOT HCT4066D 40 C to 125 C 14 SO14 plastic SOT HC4066DB 40 C to 125 C 14 SSOP14 plastic SOT HCT4066DB 40 C to 125 C 14 SSOP14 plastic SOT HC4066PW 40 C to 125 C 14 TSSOP14 plastic SOT HCT4066PW 40 C to 125 C 14 TSSOP14 plastic SOT HC4066BQ 40 C to 125 C 14 DHVQFN14 plastic SOT HCT4066BQ 40 C to 125 C 14 DHVQFN14 plastic SOT762-1 PINNING PIN SYMBOL DESCRIPTION 1 1Y independent input/output 2 1Z independent input/output 3 2Z independent input/output 4 2Y independent input/output 5 2E enable input (active HIGH) 6 3E enable input (active HIGH) 7 ground (0 V) 8 3Y independent input/output 9 3Z independent input/output 10 4Z independent input/output 11 4Y independent input/output 12 4E enable input (active HIGH) 13 1E enable input (active HIGH) 14 supply voltage handbook, halfpage Fig.1 1Y 1Z 2Z 2Y 2E 3E MGR E 4E 4Y 4Z 3Z 3Y Pin configuration DIP14, SO14 and (T)SSOP Nov 11 3

4 terminal 1 index area 1Z 2Z 2Y 2E 3E 1Y VCC V (1) CC E 4E 4Y 4Z 3Z handbook, halfpage 13 1E 5 2E 6 3E 1Y 1Z 2Y 2Z 3Y 3Z Y Transparent top view 001aac E 4Y 4Z MGR254 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.2 Pin configuration DHVQFN14. Fig.3 Logic symbol. handbook, halfpage # handbook, halfpage 1 13 # 1 1 X # # X # # X1 12 # MGR # X1 MGR256 Fig.4 IEEEC logic symbol Nov 11 4

5 handbook, halfpage ny handbook, halfpage E 1Y 2E 2Y 3E 3Y 4E 4Y ne 1Z 2Z 3Z 4Z MGR257 nz MGR258 Fig.5 Functional diagram. Fig.6 Schematic diagram (one switch) Nov 11 5

6 RECOMMENDED OPERTING CONDITIONS SYMBOL PRMETER CONDITIONS 74HC HCT4066 MIN. TYP. MX. MIN. TYP. MX. UNIT supply voltage V V I input voltage V V S switch voltage V T amb ambient temperature see DC and C C characteristics per device C t r,t f input rise and fall times = 2.0 V ns = 4.5 V 500 ns = 6.0 V 400 ns = 10.0 V 250 ns LIMITING VLUES In accordance with the bsolute Maximum Rating System (IEC 60134); voltages are referenced to (ground = 0 V). SYMBOL PRMETER CONDITIONS MIN. MX. UNIT supply voltage V I IK input diode current V I < 0.5 V or V I > V ±20 m I SK switch diode current V S < 0.5 V or V S > V ±20 m I S switch current 0.5V<V O < V; note 1 ±25 m I CC, I or current ±50 m T stg storage temperature C P tot power dissipation T amb = 40 C to +125 C; note mw P S power dissipation per switch 100 mw Notes 1. To avoid drawing current out of pin nz, when switch current flows in pin ny, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into pin nz, no current will flow out of pin ny. In this case there is no limit for the voltage drop across the switch, but the voltages at pins ny and nz may not exceed or. 2. For DIP14 packages: above 70 C derate linearly with 12 mw/k. For SO14 packages: above 70 C derate linearly with 8 mw/k. For SSOP14 and TSSOP16 packages: above 60 C derate linearly with 5.5 mw/k. For DHVQFN14 packages: above 60 C derate linearly with 4.5 mw/k Nov 11 6

7 DC CHRCTERISTICS Family 74HC4066 Voltages are referenced to (ground = 0 V); V is is the input voltage at pins ny or nz, whichever is assigned as an input; V os is the output voltage at pins ny or nz, whichever is assigned as an output. SYMBOL PRMETER TEST CONDITIONS OTHER (V) MIN. TYP. MX. UNIT T amb = 40 C to +85 C; note 1 V IH HIGH-level input V voltage V V V V IL LOW-level input voltage V V V V I LI input leakage current V I = or 6.0 ±1.0 µ 10.0 ±2.0 µ I S(OFF) I S(ON) I CC analog switch current OFF-state analog switch current ON-state quiescent supply current per channel; V I =V IH or V IL ; V S = ; see Fig.7 V I =V IH or V IL ; V S = ; see Fig.8 V I = or ; V is = or ; V os = or 10.0 ±1.0 µ 10.0 ±1.0 µ µ µ 2004 Nov 11 7

8 SYMBOL T amb = 40 C to +125 C V IH HIGH-level input V voltage V V V V IL LOW-level input voltage V V V V I LI input leakage current V I = or 6.0 ±1.0 µ 10.0 ±2.0 µ I S(OFF) I S(ON) I CC PRMETER analog switch current OFF-state analog switch current ON-state quiescent supply current Note 1. ll typical values are measured at T amb =25 C. TEST CONDITIONS OTHER per channel; V I =V IH or V IL ; V S = ; see Fig.7 V I =V IH or V IL ; V S = ; see Fig.8 V I = or ; V is = or ; V os = or (V) MIN. TYP. MX. UNIT 10.0 ±1.0 µ 10.0 ±1.0 µ µ µ 2004 Nov 11 8

9 Family 74HCT4066 Voltages are referenced to (ground = 0 V); V is is the input voltage at pins ny or nz, whichever is assigned as an input; V os is the output voltage at pins ny or nz, whichever is assigned as an output. SYMBOL PRMETER Note 1. ll typical values are measured at T amb =25 C. TEST CONDITIONS OTHER (V) MIN. TYP. MX. UNIT T amb = 40 C to +85 C; note 1 V IH HIGH-level input 4.5 to V voltage V IL LOW-level input voltage 4.5 to V I LI input leakage current V I = or 5.5 ±1.0 µ I S(OFF) I S(ON) I CC analog switch current OFF-state analog switch current ON-state quiescent supply current I CC additional quiescent supply current per input T amb = 40 C to +125 C V IH HIGH-level input voltage per channel; V I =V IH or V IL ; V S = ; see Fig.7 V I =V IH or V IL ; V S = ; see Fig.8 V I = or ; V is = or ; V os = or V I = 2.1 V; other inputs at or 5.5 ±1.0 µ 5.5 ±1.0 µ 4.5 to µ 4.5 to µ 4.5 to V V IL LOW-level input voltage 4.5 to V I LI input leakage current V I = or 5.5 ±1.0 µ I S(OFF) I S(ON) I CC I CC analog switch current OFF-state analog switch current ON-state quiescent supply current additional quiescent supply current per input per channel; V I =V IH or V IL ; V S = ; see Fig.7 V I =V IH or V IL ; V S = ; see Fig.8 V I = or ; V is = or ; V os = or V I = 2.1 V; other inputs at or 10.0 ±1.0 µ 10.0 ±1.0 µ 4.5 to µ 4.5 to µ 2004 Nov 11 9

10 LOW (from enable inputs) V I = or ny nz V O = or MGR260 Fig.7 Test circuit for measuring OFF-state current. HIGH (from enable inputs) V I = or ny nz V O (open circuit) MGR261 Fig.8 Test circuit for measuring ON-state current Nov 11 10

11 Resistance R ON for 74HC4066 and 74HCT4066 For 74HC4066: = 2.0, 4.5, 6.0 and 9.0 V; for 74HCT4066: = 4.5 V; note 1; V is is the input voltage at pins ny or nz, whichever is assigned as an input; see Fig.9. SYMBOL PRMETER TEST CONDITIONS OTHER I S (µ) (V) MIN. TYP. MX. UNIT T amb = 40 C to +85 C; note 2 R ON(peak) R ON(rail) ON-resistance (peak) ON-resistance (rail) R ON maximum variation of ON-resistance between any two channels T amb = 40 C to +125 C V I =V IH or V IL ; V is = to Ω Ω Ω Ω V I =V IH or V IL ; V is = Ω Ω Ω Ω V I =V IH or V IL ; V is = Ω Ω Ω Ω V I =V IH or V IL ; V is = to 2.0 Ω Ω Ω Ω R ON(peak) R ON(rail) ON-resistance (peak) ON-resistance (rail) V I =V IH or V IL ; V is = to Ω Ω Ω Ω V I =V IH or V IL ; V is = Ω Ω Ω Ω V I =V IH or V IL ; V is = Ω Ω Ω Ω Notes 1. t supply voltages approaching 2 V, the analog ON-resistance switch becomes extremely non-linear. Therefore, it is recommended that these devices are being used to transmit digital signals only, when using these supply voltages. 2. ll typical values are measured at T amb =25 C Nov 11 11

12 HIGH (from enable inputs) V ny nz V is = 0 to I s MGR259 Fig.9 Test circuit for measuring ON-resistance (R ON ). 60 handbook, halfpage R ON (Ω) 50 = 4.5 V MGR V 9 V V is (V) V is =0Vto. Fig.10 Typical ON-resistance (R ON ) as a function of input voltage (V is ) Nov 11 12

13 C CHRCTERISTICS Type 74HC4066 = 0 V; t r =t f = 6 ns; C L = 50 pf; V is is the input voltage at pins ny or nz, whichever is assigned as an input; V os is the output voltage at pins ny or nz, whichever is assigned as an output. SYMBOL PRMETER Note 1. ll typical values are measured at T amb =25 C. TEST CONDITIONS OTHER (V) MIN. TYP. MX. UNIT R L = ; see Fig ns R L = ; see Fig ns T amb = 40 C to +85 C; note 1 t PHL /t PLH propagation delay V is to V os ns ns ns t PZH /t PZL turn-on time ne to V os R L =1kΩ; see Figs 20 and ns ns ns ns t PHZ /t PLZ turn-off time ne to V os R L =1kΩ; see Figs 20 and ns ns ns ns T amb = 40 C to +125 C t PHL /t PLH propagation delay V is to V os ns ns ns t PZH /t PZL turn-on time ne to V os R L =1kΩ; see Figs 20 and ns ns ns ns t PHZ /t PLZ turn-off time ne to V os R L =1kΩ; see Figs 20 and ns ns ns ns 2004 Nov 11 13

14 Type 74HCT4066 = 0 V; t r =t f = 6 ns; C L = 50 pf; V is is the input voltage at pins ny or nz, whichever is assigned as an input; V os is the output voltage at pins ny or nz, whichever is assigned as an output. SYMBOL PRMETER Note 1. ll typical values are measured at T amb =25 C. 74HC4066 and 74HCT4066 t recommended conditions and typical values; = 0 V; t r =t f = 6 ns; V is is the input voltage at pins ny or nz, whichever is assigned as an input; V os is the output voltage at pins ny or nz, whichever is assigned as an output. Notes 1. djust input voltage V is is 0 dbm level (0 dbm = 1 mw into 600 Ω). 2. djust input voltage V is is 0 dbm level at V os for 1 MHz (0 dbm = 1 mw into 50 Ω) Nov TEST CONDITIONS OTHER (V) MIN. TYP. MX. UNIT R L = ; see Fig ns R L = ; see Fig ns T amb = 40 C to +85 C; note 1 t PHL /t PLH propagation delay V is to V os t PZH /t PZL turn-on time ne to V os R L =1kΩ; see Figs 20 and ns t PHZ /t PLZ turn-off time ne to V os R L =1kΩ; see Figs 20 and ns T amb = 40 C to +125 C t PHL /t PLH propagation delay V is to V os t PZH /t PZL turn-on time ne to V os R L =1kΩ; see Figs 20 and ns t PHZ /t PLZ turn-off time ne to V os R L =1kΩ; see Figs 20 and ns CONDITIONS SYMBOL PRMETER OTHER V is(p-p) (V) (V) TYP. UNIT d sin sine wave distortion f = 1 khz; R L =10kΩ; C L =50pF; % see Fig % f = 10 khz; R L =10kΩ;C L =50pF; % see Fig % α OFF(feedthr) α ct(s) V ct(p-p) f max C S switch OFF signal feed-through crosstalk between any two switches crosstalk voltage between any input to any switch (peak-to-peak value) minimum frequency response ( 3 db) maximum switch capacitance R L = 600 Ω; C L = 50 pf; f = 1 MHz; see Figs 11 and 18 R L = 600 Ω; C L = 50 pf; f = 1 MHz; see Fig.13 R L = 600 Ω; C L = 50 pf; f = 1 MHz; see Fig.15 (ne, square wave between and, t r =t f = 6 ns) R L =50Ω; C L = 10 pf; see Figs 12 and 16 note db db note db db mv mv note MHz MHz 8 pf

15 0 MGR263 (db) f (khz) 10 6 Test conditions: = 4.5 V; = 0 V; R L =50Ω; R source =1kΩ. Fig.11 Typical switch OFF signal feed-through as a function of frequency. 5 MGR264 (db) f (khz) 10 6 Test conditions: = 4.5 V; = 0 V; R L =50Ω; R source =1kΩ. Fig.12 Typical frequency response Nov 11 15

16 V I 0.1 µf R L ny/nz nz/ny C L channel ON MGR265 Fig.13 Test circuit for measuring crosstalk between any two switches; channels ON condition. ny/nz nz/ny V os channel OFF C L db MGR266 Fig.14 Test circuit for measuring crosstalk between any two switches; channels OFF condition Nov 11 16

17 page The crosstalk is defined as follows (oscilloscope output). V ct(p-p) ny/nz ne D.U.T. VCC nz/ny V os MGR267 C L oscilloscope MGR268 Fig.15 Test circuit for measuring crosstalk between control and any switch. sine-wave 0.1 µf ny/nz V is nz/ny V os C L db channel ON MGR269 djust input voltage to obtain 0 db at V os when f i = 1 MHz. fter set-up, the frequency of f i is increased to obtain a reading of -3 db at V os. Fig.16 Test circuit for measuring minimum frequency response Nov 11 17

18 f i = 1 khz sine-wave V is 10 µf ny/nz channel ON C L DISTORTION METER nz/ny V os MGR270 Fig.17 Test circuit for measuring sine wave distortion. 0.1 µf ny/nz V is nz/ny V os C L db channel OFF MGR271 Fig.18 Test circuit for measuring switch OFF signal feed-through Nov 11 18

19 C WVEFORMS t r t f 90% V is 10% 50% V os 50% t PLH t PHL MGR272 Fig.19 Waveforms showing the input (V is ) to output (V os ) propagation delays. t f t r 90 % ne input V M 10 % t PLZ t PZL output LOW - to - OFF OFF - to - LOW 10 % 50 % t PHZ t PZH output HIGH - to - OFF OFF - to - HIGH 90 % 50 % MG846 outputs enabled outputs disabled outputs enabled 74HC4066: V M = 50 %; V I = to. 74HCT4066: V M = 1.3 V; V I = to 3 V. Fig.20 Waveforms showing the turn-on and turn-off times Nov 11 19

20 TEST CIRCUIT ND WVEFORMS V is PULSE GENERTOR V I D.U.T. V O R L switch open RT C L MGR273 TEST SWITCH V is t PZH t PZL t PHZ t PLZ other open pulse Definitions for test circuit: R L = Load resistance. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Z O of the pulse generator. t f = 6 ns; when measuring f max, there is no constraint to t r and t f with 50 % duty factor. Fig.21 Test circuit for measuring C performance. t W negative input pulse 90% amplitude V M 10% 0 V t THL (t f ) t TLH (t r ) t TLH (t r ) t THL (t f ) positive input pulse 10% 90% V M amplitude 0 V t W MGR274 FMILY MPLITUDE V M f max ; PULSE t r and t f WIDTH OTHER 74HC % <2 ns 6ns 74HCT V 1.3 V <2 ns 6ns Fig.22 Input pulse definitions Nov 11 20

21 PCKGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D M E seating plane 2 L 1 Z 14 e b b 1 8 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT G04 MO-001 SC Nov 11 21

22 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E X c y H E v M Z 14 8 Q pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E06 MS Nov 11 22

23 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E X c y H E v M Z 14 8 Q 2 1 ( ) 3 pin 1 index 1 7 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p Q v w y Z(1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337-1 MO Nov 11 23

24 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E X c y H E v M Z 14 8 pin 1 index 2 1 Q ( ) 3 θ 1 7 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402-1 MO-153 EUROPEN PROJECTION ISSUE DTE Nov 11 24

25 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 6 v M w M C C B y 1 C C y L 1 7 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) E h e e 1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Nov 11 25

26 DT SHEET STTUS LEVEL DT SHEET STTUS (1) PRODUCT STTUS (2)(3) DEFINITION I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified Nov 11 26

27 a worldwide company Contact information For additional information please visit Fax: For sales offices addresses send to: Koninklijke Philips Electronics N.V SC76 ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R44/05/pp27 Date of release: 2004 Nov 11 Document order number: