Hardware Functional Specification
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1 Hardware Functional Specification SEIKO EPSON CORPORATION Rev. 1.6
2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. SEIKO EPSON CORPORATION , All rights reserved.
3 Table of Contents Chapter 1 Introduction Scope Operational Overview Chapter 2 Features Display Resolution CPU Interface Input Data Format Display Interface Display Features Miscellaneous Chapter 3 Typical System Implementation Chapter 4 Pins Pinout Diagram Pin Description Host Interface Panel Interface Clock Input Miscellaneous Power And Ground Summary of Configuration Options Host Interface Pin Mapping Panel Interface Pin Mapping Chapter 5 Logic Diagram Chapter 6 Embedded Memory Memory Map Sample Maximum Resolution Chapter 7 Clocks Clock Tree PLL Setting Clock Setting Minimum Requirement Chapter 8 D.C. Characteristics Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Chapter 9 A.C. Characteristics Clock Timing S1D13781 Series Hardware Functional Specification EPSON 3
4 9.1.1 Input Clocks PLL Clock RESET# Timing Power Supply Sequence Power-On Sequence Power-Off Sequence Host Interface Timing Direct 16-bit Mode 1 Timing Direct 16-bit Mode 2 Timing Indirect 16-bit Mode 1 Timing Indirect 16-bit Mode 2 Timing Direct 8-bit Timing Indirect 8-bit Timing SPI Timing Panel Interface Timing General STN Panel Timing Single Color 8-Bit Panel Format 2 Timing Single Color 16-Bit Panel Timing Single Monochrome 4-Bit Panel Timing Single Monochrome 8-Bit Panel Timing General TFT Panel Timing TFT 16/18/24-Bit Panel Timing Chapter 10 Registers General Configuration Registers Clock Configuration Registers Panel Configuration Registers Layer Configuration Registers D BitBLT Engine Setting Registers GPIO Setting Registers Look-Up Table Registers Chapter 11 Indirect and Serial Host Interface Accessing Sequence Indirect Interface Write Procedure Read Procedure SPI Write Procedure Read Procedure Chapter 12 Image Data Formats EPSON S1D13781 Series Hardware Functional Specification
5 12.1 Image Data Formats for Host Interface RGB 8:8:8 Data Format RGB 5:6:5 Data Format bpp for Monochrome bpp + LUT Data Format bpp + LUT Data Format bpp + LUT Data Format Data Expansion Monochrome Mode Color Depth Chapter 13 Look-Up Table Architecture bpp LUT bpp LUT bpp LUT in Color Mode bpp LUT in Monochrome Mode Chapter 14 2D BitBLT Engine Overview Move BitBLT Move with Color Expansion BitBLT Solid Fill BitBLT Linear / Rectangular Calculation for Move Performance Considerations Chapter 15 Display Features PIP (Picture-in-Picture) Layer Transparency Alpha Blending PIP Effects Blinking and Fading Effects Blink/Fade Period Fade Steps PIP Effect State Transitions Rotation Location Address Start Address Operating Modes Chapter 16 Mechanical Data Chapter 17 Change Record S1D13781 Series Hardware Functional Specification EPSON 5
6 6 EPSON S1D13781 Series Hardware Functional Specification
7 Chapter 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13781 Series Simple LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development. The latest revision can be downloaded at We appreciate your comments on our documentation. Please contact us via at documentation@erd.epson.com. 1.2 Operational Overview The S1D13781 is a simple LCD controller with an embedded 384K byte display buffer. The S1D13781 supports both 8/16-bit direct/indirect CPU interfaces and a SPI CPU interface. Resolutions supported are up to 480x272 at 24 bpp or 800x480 at 8 bpp for single layer display, or 400x240 at 24 bpp (Main Layer) and 400x240 at 8 bpp (PIP Layer) for two layer display. Passive Single Color and Monochrome, as well as TFT panels are supported. The S1D13781 provides hardware rotation of the display memory transparent to the software application. The S1D13781 supports both Alpha Blending and Transparency, and with PIP Layer Flashing both preset Blinking and Fade In/Out is achieved with simple register settings. With PIP Layer Flashing the displayed image looks rich, even when used with a low performance CPU. S1D13781 Series Hardware Functional Specification EPSON 7
8 Chapter 2 Features 2.1 Display Resolution 384K bytes of embedded VRAM for storing the image data Display Resolutions for one layer display (Main Layer Only): Up to 480x272 at 24 bpp Up to 800x480 at 8 bpp Display Resolutions for two layer display (Main and PIP Layer): Up to 400x240 at 24 bpp (Main Layer) and 400x240 at 8 bpp (PIP Layer) 2.2 CPU Interface 8/16-bit Direct interface 8/16-bit Indirect interface SPI (Mode 0, Mode 3) 2.3 Input Data Format RGB 8:8:8, RGB 5:6:5, 8 bpp grayscale, or 8/16/24 bpp with Look-Up Table (LUT) 2.4 Display Interface Single panel, single drive passive displays 8/16-bit color 4/8-bit monochrome Active Matrix TFT panels 16/18/24-bit 8 EPSON S1D13781 Series Hardware Functional Specification
9 2.5 Display Features Up to two display layers: Main Layer 8/16/24 bpp color depths with optional Look-up Table (LUT) Independent rotation (0, 90, 180, 270 counter-clockwise) PIP Layer 8/16/24 bpp color depths with optional Look-up Table (LUT) Independent rotation (0, 90, 180, 270 counter-clockwise) Configurable PIP Effects allow automatic blink and fade in/out effects Alpha Blending Transparency Look-up Tables for Main and PIP Layers (256 address x 24 bpp) 2D BitBLT Engine 2.6 Miscellaneous Single Clock Input: CLKI Embedded PLL Software initiated Power Save Modes General Purpose IO Pins are available Operating Temperature: S1D13781F00A*** -40 to 85 C S1D13781F01A*** -40 to 105 C Package: QFP pin (14mm x 14mm x 1.7mm) S1D13781 Series Hardware Functional Specification EPSON 9
10 Chapter 3 Typical System Implementation Direct 16-bit Mode 1 S1D13781 Monochrome Passive 4-bit Panel CS# WR# RD# UB# LB# CS# WR# RD# UB# LB# VS HS DE (MOD) PCLK FRM LOAD CP AB[18:1] AB0 INT AB[18:1] TE (AB0) D[3:0] (PDT[7:4] PT[11:8], PDT[3:0] GPIO[15:4] (PDT[23:12]) D[3:0] DB[15:0] DB[15:0] GPIO DISP RESET# RESET# Oscillator CLKI Figure 3-1: Typical System Diagram (Direct 16-bit Mode 1, Monochrome Passive 4-bit Panel) Direct 16-bit Mode 2 S1D13781 Monochrome Passive 8-bit Panel CS# WRU# WRL# RDU# RDL# CS# WRU# (UB#) WRL# (LB#) RDU# (WR#) RDL# (RD#) VS HS DE (MOD) PCLK FRM LOAD WF CP AB[18:1] AB0 INT DB[15:0] AB[18:1] TE (AB0) DB[15:0] D[7:0] (PDT[7:0]) PDT[11:8] GPIO[15:4] (PDT[23:12]) GPIO D[7:0] DISP RESET# RESET# Oscillator CLKI Figure 3-2: Typical System Diagram (Direct 16-bit Mode 2, Monochrome Passive 8-bit Panel) 10 EPSON S1D13781 Series Hardware Functional Specification
11 Indirect 16 bit Mode 1 S1D13781 Color Passive 8-bit Format 2 Panel CS# WR# RD# UB# LB# P/C# INT CS# WR# RD# UB# LB# P/C# (AB1) TE (AB0) AB[18:2] VS HS DE(MOD) PCLK D[7:0] (PDT[7:0]) PDT[11:8] GPIO[15:4] (PDT[23:12]) FRM LOAD CP D[7:0] DB[15:0] DB[15:0] GPIO DISP RESET# RESET# Oscillator CLKI Figure 3-3: Typical System Diagram (Indirect 16-bit Mode 1, Color Passive 8-bit Format 2 Panel) Indirect 16-bit Mode 2 S1D13781 Color Passive 16-bit Panel CS# WRU# WRL# RDU# RDL# CS# WRU# (UB#) WRL# (LB#) RDU# (WR#) RDL# (RD#) VS HS DE (MOD) PCLK FRM LOAD WF CP P/C# INT P/C# (AB1) TE (AB0) D[15:0] (PDT[15:0]) GPIO[15:8] (PDT[23:16]) D[15:0] AB[18:2] GPIO DISP DB[15:0] DB[15:0] RESET# RESET# Oscillator CLKI Figure 3-4: Typical System Diagram (Indirect 16-bit Mode 2, Color Passive 16-bit Panel) S1D13781 Series Hardware Functional Specification EPSON 11
12 Direct 8-bit S1D13781 Generic TFT 16-bit CS# WR# RD# AB[18:0] INT IOVDD CS# WR# RD# UB# LB# AB[18:0] TE (DB8) VS HS DE PCLK B[4:0] (PDT[4:0]) G[5:0] (PDT[10:5]) R[4:0] (PDT[15:11]) GPIO[15:8] (PDT[23:16]) VSYNC HSYNC DE DCK Blue[4:0] Green[5:0] Red[4:0] DB[7:0] DB[7:0] DB[15:9] RESET# RESET# Oscillator CLKI Figure 3-5: Typical System Diagram (Direct 8-bit, Generic TFT 16-bit) Indirect 8-bit S1D13781 Generic TFT 18-bit CS# WR# RD# P/C# INT DB[7:0] IOVDD CS# WR# RD# UB# LB# P/C# (AB1) AB[18:2] TE (AB0) DB[7:0] DB[15:8] VS HS DE PCLK B[5:0] (PDT[5:0]) G[5:0] (PDT[11:6]) R[5:0] (PDT[17:12]) GPIO[15:10] (PDT[23:18]) VSYNC HSYNC DE DCK Blue[5:0] Green[5:0] Red[5:0] RESET# RESET# Oscillator CLKI Figure 3-6: Typical System Diagram (Indirect 8-bit, Generic TFT 18-bit) 12 EPSON S1D13781 Series Hardware Functional Specification
13 SPI S1D13781 Generic TFT 24-bit CS# CLK# INT IOVDD SCS# (CS#) SCK (WR#) RD# UB# LB# TE (AB0) AB[18:1] VS HS DE PCLK B[7:0] (PDT[7:0]) G[7:0] (PDT[15:8]) R[7:0] (PDT[23:16]) VSYNC HSYNC DE DCK Blue[7:0] Green[7:0] Red[7:0] SO SI SI (DB0) SO (DB1) DB[15:2] RESET# RESET# Oscillator CLKI Figure 3-7: Typical System Diagram (SPI, Generic TFT 24-bit) S1D13781 Series Hardware Functional Specification EPSON 13
14 Chapter 4 Pins 4.1 Pinout Diagram PDT13 77 PDT14 78 PDT12 PDT11 PDT15 79 COREVDD 80 GND 81 PDT16 82 PDT17 83 PDT18 84 PDT19 85 PDT20 86 PDT21 87 PDT22 88 PDT23 89 IOVDD 90 GND 91 GPIO0 92 GPIO1 93 GPIO2 94 GPIO3 95 CNF0 96 CNF1 97 CNF2 98 TESTEN 99 SCANEN 100 RESET# IOVDD PDT10 PDT9 IOVDD AB0 AB1 AB2 AB3 AB4 PDT8 PDT7 S1D13781 Index AB5 PDT6 GND PDT5 PDT4 PDT3 PDT2 AB6 AB7 AB8 AB9 GND PDT1 PDT0 COREVDD AB10 AB11 IOVDD PCLK COREVDD GND DE HS VS PLLVDD AB14 AB15 AB16 AB17 AB18 GND LB# UB# AB12 AB13 VCP PLLGND 50 IOVDD 49 CLKI GND DB15 DB14 46 DB13 45 DB12 44 DB11 43 DB10 42 DB9 41 DB COREVDD 38 GND 37 DB7 36 DB6 35 DB5 34 DB4 33 DB3 32 DB2 31 DB1 30 IOVDD 29 DB0 28 CS# 27 WR# 26 RD# Figure 4-1 S1D13781 Pinout Diagram (QFP15-100pin) - Top View 14 EPSON S1D13781 Series Hardware Functional Specification
15 4.2 Pin Description Key: Pin Types I = Input O = Output IO = Bi-Directional (Input/Output) P = Power pin AP = Analog Power pin G = Ground AG = Analog Ground RESET# / Power Save State H = High level output L = Low level output Hi-Z = High Impedance Q = Output Pin, retains output state QB = IO Pin, if configured as output retains state Table 4-1: Cell Description HIS HISD HISU HID HO HB HBD LIDS LITR Item Description H System LVCMOS Schmitt Input Buffer with Fail Safe H System LVCMOS Schmitt Input Buffer with pull-down resistor and Fail Safe H System LVCMOS Schmitt Input Buffer with pull-up resistor and Fail Safe H System LVCMOS Input Buffer with pull-down resistor and Fail Safe H System LVCOMOS Output buffer with Fail Safe H System LVCMOS Bidirectional Buffer with Fail Safe H System LVCMOS Bidirectional Buffer with pull-down resistor and Fail Safe L System 2 LVCMOS Schmitt Input Buffer with pull-down resistor L System Transparent Input Buffer 1 H System is IOVDD (see Chapter 8, D.C. Characteristics on page 27). 2 L System is COREVDD (see Chapter 8, D.C. Characteristics on page 27). 3 LVCMOS is Low Voltage CMOS (see Chapter 8, D.C. Characteristics on page 27). S1D13781 Series Hardware Functional Specification EPSON 15
16 4.2.1 Host Interface Pin Name Type Pin# Cell Power Table 4-2: Host Interface Pin Descriptions Power Save State RESET# State Description CS# I 28 HIS IOVDD This input pin is the Chip Select signal. WR# I 27 HIS IOVDD This input pin has multiple functions, WR#, RDU# and SCK. See Section 4.4, Host Interface Pin Mapping on page 20 for details. RD# I 26 HISU IOVDD This input pin has multiple functions, RD# and RDL#. See Section 4.4, Host Interface Pin Mapping on page 20 for details. UB# I 25 HISU IOVDD This input pin has multiple functions, UB# and WRU#. See Section 4.4, Host Interface Pin Mapping on page 20 for details. LB# I 24 HISU IOVDD This input pin has multiple functions, LB# and WRL#. See Section 4.4, Host Interface Pin Mapping on page 20 for details. AB0 IO 2 HB IOVDD QB This bidirectional pin has multiple functions, AB0 and TE. See Section 4.4, Host Interface Pin Mapping on page 20 for details. AB1 I 3 HID IOVDD This input pin has multiple functions, AB1 and P/C#. See Section 4.4, Host Interface Pin Mapping on page 20 for details. AB[18:2] I 22~14, 11~4 HID IOVDD DB0 IO 29 HB IOVDD DB1 IO 31 HB IOVDD DB[7:2] IO 37~32 HB IOVDD DB8 IO 40 HB IOVDD DB[15:9] IO 47~41 HB IOVDD RESET# I 100 HIS IOVDD These input pins are the host address bus AB[18:2]. See Section 4.4, Host Interface Pin Mapping on page 20 for details. This bidirectional pin has multiple functions, host data bus DB0 and SI. See Section 4.4, Host Interface Pin Mapping on page 20 for details. This bidirectional pin has multiple functions, host data bus DB1 and SO. See Section 4.4, Host Interface Pin Mapping on page 20 for details. These bidirectional pins are the host data bus DB[7:2]. See Section 4.4, Host Interface Pin Mapping on page 20 for details. This bidirectional pin has multiple functions, host data bus DB8 and TE. See Section 4.4, Host Interface Pin Mapping on page 20 for details. These bidirectional pins are the host data bus DB[15:9]. See Section 4.4, Host Interface Pin Mapping on page 20 for details. Active low input to set all internal registers to the default state and to force all signals to their inactive states. 16 EPSON S1D13781 Series Hardware Functional Specification
17 4.2.2 Panel Interface Pin Name Type Pin# Cell Power PDT[11:0] O PDT[23:12] IO 74, 72~68, 66~61 88~81, 78~75 Table 4-3: Panel Interface Pin Descriptions Power Save State RESET# State HO IOVDD Q L HBD IOVDD QB L VS O 54 HO IOVDD Q L HS O 55 HO IOVDD Q L DE O 56 HO IOVDD Q L PDCLK O 59 HO IOVDD Q L Description These output pins are the panel data bus PDT[11:0]. See Section 4.5, Panel Interface Pin Mapping on page 21 for details. These bidirectional pins have multiple functions, panel data bus PDT[23:12] and GPIO. See Section 4.5, Panel Interface Pin Mapping on page 21 for details. This output pin is VS, the panel vertical sync signal. See Section 4.5, Panel Interface Pin Mapping on page 21 for details. This output pin is HS, the panel horizontal sync signal. See Section 4.5, Panel Interface Pin Mapping on page 21 for details. This output pin has multiple functions, panel data bus enable DE and MOD. See Section 4.5, Panel Interface Pin Mapping on page 21 for details. This output pin is PDCLK, pixel clock for panels. See Section 4.5, Panel Interface Pin Mapping on page 21 for details Clock Input Pin Name Type Pin# Cell Power Table 4-4: Clock Input Pin Descriptions Power Save State RESET# State Description CLKI I 49 HIS IOVDD Input clock source for PLL or MCLK. S1D13781 Series Hardware Functional Specification EPSON 17
18 4.2.4 Miscellaneous Pin Name Type Pin# Cell Power Table 4-5: Miscellaneous Pin Descriptions Power Save State RESET# State TESTEN I 98 LIDS COREVDD SCANEN I 99 HISD IOVDD VCP O 52 LITR PLLVDD CNF[2:0] I 97~95 HIS IOVDD GPIO[3:0] IO 94~91 HBD IOVDD QB Description Test Enable input used for production test only. This pin must be connected directly to GND for normal operation. Scan Enable input used for production test only. This pin must be connected directly to GND for normal operation. This pin is for production test only and should be left unconnected for normal operation. These inputs are used for power-on configuration. For details, see Table 4-7: Summary of Power- On/Reset Options (Host Interface Selection), on page 19. Note: These pins must be connected directly to IOVDD or GND. These pins are a general purpose input/output. Default is input. See Section 10.7, GPIO Setting Registers on page 96 for details Power And Ground Pin Name Type Pin# Cell Power Table 4-6: Power And Ground Pin Descriptions Power Save State RESET# State IOVDD P 1, 30, 50 60, 73, 89 P IO power supply COREVDD P 13, 39, 58, 79 P Core power supply GND G 12, 23, 38, 48, 57, 67, 80, 90 P GND for digital PLLVDD AP 53 P PLL Power Supply PLLGND AG 51 P GND for PLL Description 18 EPSON S1D13781 Series Hardware Functional Specification
19 4.3 Summary of Configuration Options The CNF[2:0] pins are used for Host Interface selection and must be connected directly to IOVDD or GND. Table 4-7: Summary of Power-On/Reset Options (Host Interface Selection) Configuration Input CNF[2:0] Power-On/Reset State 1 (connected to IOVDD) 0 (connected to GND) 000: Direct 16-bit mode 1 001: Direct 16-bit mode 2 010: Indirect 16-bit mode 1 011: Indirect 16-bit mode 2 100: Direct 8-bit 101: Indirect 8-bit 110: Reserved 111: SPI S1D13781 Series Hardware Functional Specification EPSON 19
20 4.4 Host Interface Pin Mapping The S1D13781 Host interface is selected by setting of the CNF[2:0] pins. For a summary of the Host interface options, see Section 4.3, Summary of Configuration Options on page 19. S1D13781 Pin Name Direct 16-bit Mode 1 Direct 16-bit Mode 2 Where: H = Connect directly to IOVDD. L = Connect directly to GND. Low = Internal pull-down for address bus is active. TE is defined by REG[22h] bits 6-5. Table 4-8: Host Interface Pin Mapping Indirect 16-bit Mode 1 Indirect 16-bit Mode 2 Direct 8-bit Indirect 8-bit SPI CS# CS# CS# CS# CS# CS# CS# SCS# WR# WR# RDU# WR# RDU# WR# WR# SCK RD# RD# RDL# RD# RDL# RD# RD# H UB# UB# WRU# UB# WRU# H H H LB# LB# WRL# LB# WRL# H H H AB0 TE TE TE TE AB0 TE TE AB1 AB1 AB1 P/C# P/C# AB1 P/C# Low AB[18:2] AB[18:2] AB[18:2] Low Low AB[18:2] Low Low DB0 DB0 DB0 DB0 DB0 DB0 DB0 SI DB1 DB1 DB1 DB1 DB1 DB1 DB1 SO DB[7:2] DB[7:2] DB[7:2] DB[7:2] DB[7:2] DB[7:2] DB[7:2] L DB8 DB8 DB8 DB8 DB8 TE L L DB[15:9] DB[15:9] DB[15:9] DB[15:9] DB[15:9] L L L 20 EPSON S1D13781 Series Hardware Functional Specification
21 4.5 Panel Interface Pin Mapping Panel interface mode selection is specified by REG[20h] bits 3-0. S1D13781 Pin Monochrome Passive Panel 4-bit Table 4-9: Panel Interface Pin Mapping 8-bit Color Passive Panel 8-bit Format 2 Note 1. L = output is fixed Low. 2. H = output is fixed High 3. When PDT[12:23] is assigned as panel data bus, the internal pull down is inactive. When PDT[12:23] is assigned as GPIO, the internal pull down is controlled by REG[D4h]. Generic TFT 16-bit 16-bit 18-bit 24-bit VS VS VS VS VS VS VS VS HS HS HS HS HS HS HS HS DE MOD MOD MOD MOD DE DE DE PDCLK CK CK CK CK PCLK PCLK PCLK PDT0 L D0 (px8) D0 (G3) D0 (R6) B0 B0 B0 PDT1 L D1 (px7) D1 (R3) D1 (G5) B1 B1 B1 PDT2 L D2 (px6) D2 (B2) D2 (B4) B2 B2 B2 PDT3 L D3 (px5) D3 (G2) D3 (R4) B3 B3 B3 PDT4 D0 (px4) D4 (px4) D4 (R2) D8 (B5) B4 B4 B4 PDT5 D1 (px3) D5 (px3) D5 (B1) D9 (R5) G0 B5 B5 PDT6 D2 (px2) D6 (px2) D6 (G1) D10 (G4) G1 G0 B6 PDT7 D3 (px1) D7 (px1) D7 (R1) D11 (B3) G2 G1 B7 PDT8 L L L D4 (G3) G3 G2 G0 PDT9 L L L D5 (B2) G4 G3 G1 PDT10 L L L D6 (R2) G5 G4 G2 PDT11 L L L D7 (G1) R0 G5 G3 PDT12 GPIO4 GPIO4 GPIO4 D12 (R3) R1 R0 G4 PDT13 GPIO5 GPIO5 GPIO5 D13 (G2) R2 R1 G5 PDT14 GPIO6 GPIO6 GPIO6 D14 (B1) R3 R2 G6 PDT15 GPIO7 GPIO7 GPIO7 D15 (R1) R4 R3 G7 PDT16 GPIO8 GPIO8 GPIO8 GPIO8 GPIO8 R4 R0 PDT17 GPIO9 GPIO9 GPIO9 GPIO9 GPIO9 R5 R1 PDT18 GPIO10 GPIO10 GPIO10 GPIO10 GPIO10 GPIO10 R2 PDT19 GPIO11 GPIO11 GPIO11 GPIO11 GPIO11 GPIO11 R3 PDT20 GPIO12 GPIO12 GPIO12 GPIO12 GPIO12 GPIO12 R4 PDT21 GPIO13 GPIO13 GPIO13 GPIO13 GPIO13 GPIO13 R5 PDT22 GPIO14 GPIO14 GPIO14 GPIO14 GPIO14 GPIO14 R6 PDT23 GPIO15 GPIO15 GPIO15 GPIO15 GPIO15 GPIO15 R7 S1D13781 Series Hardware Functional Specification EPSON 21
22 Chapter 5 Logic Diagram LUT1 Host Interface Main Layer Pipe Direct/ Indirect 8/16-bit SPI Memory Interface Blending LCD Interface PIP Layer Pipe Register Memory 384KB LUT2 PLL Clock Test Mux Figure 5-1: Block Diagram 22 EPSON S1D13781 Series Hardware Functional Specification
23 Chapter 6 Embedded Memory 6.1 Memory Map 00000h 1 Layer Mode 2 Layer Mode must start 32-bit alignment must start 32-bit alignment Main Layer VRAM 384K Bytes Main Layer must start 32-bit alignment PIP Layer 5FFFFh 60000h 603FFh 60400h 607FFh 60800h 608FFh LUT 1 LUT 2 Registers LUT 1 LUT 1 LUT 2 Registers Registers Figure 6-1: Memory Construction for Direct Interface The S1D13781 has 384K bytes of memory. The VRAM, Registers, and LUT are directly mapped. S1D13781 Series Hardware Functional Specification EPSON 23
24 6.2 Sample Maximum Resolution When in 1 Layer Mode (PIP Layer off, REG[60h] bits 2-0 = 000b), all 384K bytes of VRAM are assigned for the Main Layer. The Main Layer start address (REG[42h] ~ REG[44h]) must maintain 32-bit alignment. Maximum Main Layer resolutions are shown in the following table. Table 6-1: Maximum Main Layer Resolutions for 1 Layer Mode Input Data Format Horizontal Vertical RGB 8:8: RGB 5:6: bpp + LUT When in 2 Layer Mode (PIP Layer on, REG[60h] bits 2-0 = 001b ~ 111b), the 384K bytes of VRAM are assigned to both the Main Layer and PIP Layer. Both the Main Layer Start Address (REG[42h] ~ REG[44h]) and PIP Layer Start Address (REG[52h] ~ REG[54h]) must maintain 32-bit alignment. maximum combination resolutions for Main and PIP layer are shown in the following table. Table 6-2: Maximum Combination Resolutions for 2 Layer Mode Example Layer Input Data Format Horizontal Vertical 1 Main RGB 8:8: PIP 8 bpp + LUT Main RGB 8:8: PIP RGB 5:6: Main RGB 8:8: PIP RGB 8:8: EPSON S1D13781 Series Hardware Functional Specification
25 Chapter 7 Clocks 7.1 Clock Tree REG[10h] bit 0 On/Off CLKI PLL 0 1 POCLK REG[10h] bit 1 REG[04h] bits 1-0 MCLK REG[16h] bits 3-0 DIV PCLK Figure 7-1: Clock Diagram 7.2 PLL Setting PLL related registers (REG[10h] through REG[14h]) must be set as shown in the following figure. PLL CLKI f CLKI 1~33MHz M-Divider PFDCLK f PFDCLK 1~2MHz N-Counter L-Counter POCLK f POCLK 33~66MHz REG[12h] bits 9-0 REG[12h] bits REG[14h] bits 9-0 (000h ~ 020h) (= 0h) (010h ~ 041h) Figure 7-2: PLL Settings Note If the S1D13781 is configured to use the PLL output as the MCLK source and the Host wants to turn off the input clock (CLKI), the Host must disable the PLL (REG[10h] bit 0 = 0b) before shutting off CLKI. This procedure ensures that the PLL Lock bit (REG[10h] bit 15) goes low. Once CLKI has been turned back on, the Host should reenable the PLL. S1D13781 Series Hardware Functional Specification EPSON 25
26 7.3 Clock Setting Minimum Requirement REG[16h], the Internal Clock Configuration Register, defines the PCLK (Pixel Clock) ratio from MCLK (Memory Clock). When the panel interface block requests more pixel data than the memory interface block can provide, garbage data will be displayed. This means that when the MCLK to PCLK divide ratio is too low (REG[16h] bits 3-0), the memory interface block cannot provide data to the PCLK at the rate set. Panel interface block requirements depend on PIP enable and rotation of both Main and PIP window. Following table shows minimum setting examples for REG[16h]. Table 7-1: REG[16] Minimum Setting Examples Bpp Main Window Rotation 0/180 90/270 0/180 90/270 0/180 90/270 0/180 90/270 Hit Ratio Bpp PIP Window Rotation - 0/180 0/180 0/180 0/180 0/180 0/180 90/270 Hit Ratio Total Hit Ratio REG[16] Minimum Setting 0 (1:1) 1 (2:1) 0 (1:1) 1 (2:1) 0 (1:1) 2 (3:1) 1 (2:1) 3 (4:1) Note The above table does not take into account 2D BitBLT and Host accessing. For actual settings, space must be reserved for 2D BitBLT and Host accessing. 26 EPSON S1D13781 Series Hardware Functional Specification
27 Chapter 8 D.C. Characteristics 8.1 Absolute Maximum Ratings Table 8-1: Absolute Maximum Ratings Symbol Parameter Rating Units Core V DD Core Supply Voltage GND to 2.0 V PLL V DD PLL Supply Voltage GND to 2.0 V IO V DD Host IO Supply Voltage COREVDD to 4.0 V V IN Input Voltage GND to IOVDD V V OUT Output Voltage GND to IOVDD V I OUT Output Current ±10 ma 8.2 Recommended Operating Conditions Table 8-2: Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units Core V DD Core Supply Voltage GND = 0 V V PLL V DD PLL Supply Voltage GND = 0 V V IO V DD Host IO Supply Voltage GND = 0 V / V V IN Input Voltage GND IOVDD V T OPR Operating Temperature S1D13781F00A*** C S1D13781F01A*** C S1D13781 Series Hardware Functional Specification EPSON 27
28 8.3 Electrical Characteristics The following characteristics are for: T OPR = -40 to 85 C (S1D13781F00A***) = -40 to 105 C (S1D13781F01A***) Table 8-3: IOVDD = 3.3V ± 0.3V, GND = 0V Symbol Parameter Condition Min Typ Max Units I IZ Input Leakage Current -5 5 μa I OZ Off State Leakage Current -5 5 IOV OH High Level Output Voltage IOVDD = Min. IOH = -4mA IOVDD-0.4 V IOV OL Low Level Output Voltage IOVDD = Min. IOL = 4mA 0.4 V V IH High Level Input Voltage LVCMOS Level, IOVDD = Max. 2.2 IOVDD+0.3 V IL Low Level Input Voltage LVCMOS Level, IOVDD = Min V V T+ Positive Trigger Voltage LVCMOS Schmitt V T- Negative Trigger Voltage LVCMOS Schmitt V ΔV Hysteresis Voltage LVCMOS Schmitt 0.3 V R PU Pull-up Resistance VI = 0V kω R PD Pull-down Resistance VI = IOVDD kω C IO Pin Capacitance f = 1MHz, IOVDD = 0V 10 pf Table 8-4: IOVDD = 1.8V ± 0.18V, GND = 0V Symbol Parameter Condition Min Typ Max Units I IZ Input Leakage Current -5 5 μa I OZ Off State Leakage Current -5 5 IOV OH IOV OL V IH V IL High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage IOVDD = Min. IOH = -1.8mA IOVDD = Min. IOL = 1.8mA LVCMOS Level, IOVDD = Max. LVCMOS Level, IOVDD = Min. IOVDD-0.4 V 0.4 V 1.39 IOVDD V T+ Positive Trigger Voltage LVCMOS Schmitt V T- Negative Trigger Voltage LVCMOS Schmitt ΔV Hysteresis Voltage LVCMOS Schmitt 0.17 V R PU Pull-up Resistance VI = 0V kω R PD Pull-down Resistance VI = IOVDD kω C IO Pin Capacitance f = 1MHz, IOVDD = 0V 10 pf V V 28 EPSON S1D13781 Series Hardware Functional Specification
29 Chapter 9 A.C. Characteristics Conditions: IOVDD = 1.62V ~ 3.60V T A = -40 C to 85 C (S1D13781F00A***) = -40 C to 105 C (S1D13781F01A***) T rise and T fall for all inputs except Schmitt and CLKI must be < 50 ns (10% ~ 90%) T rise and T fall for all Schmitt must be < 5 ms (10% ~ 90%) C L = 8pF ~ 30pF (Panel I/F) 9.1 Clock Timing Input Clocks t1 t2 90% V IH V IL 10% t3 t4 t CLKI t5 t cycle 1 t cycle 2 Figure 9-1 Clock Input Required (PLL) S1D13781 Series Hardware Functional Specification EPSON 29
30 Table 9-1: Clock Input Requirements for PLL (CLKI) Symbol Parameter Min Typ Max Units f CLKI Input clock frequency MHz t CLKI Input clock period 1/f CLKI μs t1 Input clock pulse width high t CLKI t2 Input clock pulse width low t CLKI t3 Input clock rise time (10% - 90%) 10 ns t4 Input clock fall time (90% - 10%) 10 ns t5 Input clock period jitter (see Note 1) ps 1. The input clock period jitter is the displacement relative to the center period (reciprocal of the center frequency). Table 9-2: Clock Input Requirements for PLL Bypassed (CLKI) Symbol Parameter Min Typ Max Units f CLKI Input clock frequency 66 MHz t CLKI Input clock period 1/f CLKI μs t1 Input clock pulse width high 6.8 ns t2 Input clock pulse width low 6.8 ns t3 Input clock rise time (10% - 90%) 5 ns t4 Input clock fall time (90% - 10%) 5 ns 30 EPSON S1D13781 Series Hardware Functional Specification
31 9.1.2 PLL Clock The PLL circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. Noise on the clock or the supplied power may cause the operation of the PLL circuit to become unstable or increase the jitter. Due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the PLL be isolated from those of other power supplies. Filtering should also be used to keep the power as clean as possible. The jitter of the input clock waveform should be as small as possible. PLL Enable 2.5 ms Lock In Time PLL Stable 1 ~ 33MHz Reference Clock PLL xxmhz Output (xx = 33 ~ 66MHz) Jitter (ns) Lock in time 2.5 ms Time (ms) The PLL frequency will ramp between the OFF state and the programmed frequency. To guarantee the lowest possible clock jitter, 2.5 ms is required for stabilization. Figure 9-2: PLL Start-Up Time S1D13781 Series Hardware Functional Specification EPSON 31
32 Table 9-3: PLL Characteristics Symbol Parameter Min Max Units f PLLI PLL input clock frequency after M-Divider 1 2 MHz f PLLI2 PLL input clock frequency before M-Divider 1 33 MHz f PLLO PLL output clock frequency MHz t PJref PLL output clock period jitter -3 3 % t PDuty PLL output clock duty cycle % t PStal PLL output stable time 2.5 ms 9.2 RESET# Timing t1 t2 RESET# Figure 9-3 RESET# Timing Table 9-4 RESET# Timing Symbol Parameter Min Max Units t1 Reset Pulse Width is ignored 42 ns t2 Active Reset Pulse Width (see Note) 150 ns 1. The RESET# line should be held low longer than 150ns to guarantee reset. 32 EPSON S1D13781 Series Hardware Functional Specification
33 9.3 Power Supply Sequence Power-On Sequence COREVDD PLLVDD t1 IOVDD Figure 9-4: Power-On Sequence Table 9-5: Power-On Sequence Symbol Parameter Min Max Units t1 IOVDD on delay from COREVDD, PLLVDD on ms Note The sequence of COREVDD to IOVDD may be reversed as long as the timing is within the 500ms maximum Power-Off Sequence COREVDD PLLVDD t1 IOVDD Figure 9-5: Power-Off Sequence Table 9-6: Power-Off Sequence Symbol Parameter Min Max Units t1 COREVDD, PLLVDD off delay from IOVDD ms Note The sequence of COREVDD to IOVDD may be reversed as long as the timing is within the 500ms maximum. S1D13781 Series Hardware Functional Specification EPSON 33
34 9.4 Host Interface Timing Direct 16-bit Mode 1 Timing AB[18:1] UB# LB# t1 t6 t1 t6 t1 CS# Control CS# WR# RD# RD#/WR# Control CS# t2 t2 t11 t10 t12w t11 t5 t5 t10 t2 t2 WR# RD# t11 t10 t11 DB[15:0] (write) t3 valid t4 t3 valid t4 t9 t9 DB[15:0] (read) t7 valid t7 valid t8 t8 Figure 9-6: Direct 16-bit Mode 1 Timing 34 EPSON S1D13781 Series Hardware Functional Specification
35 Table 9-7: Direct 16-bit Mode 1 Timing Symbol Parameter 3.3 Volt 1.8 Volt Min Max Min Max Units t1 AB[18:1], UB#, LB# setup time to CS# (WR#, RD#) ns t2 WR#,RD# (CS#) setup time to CS# (WR#, RD#) ns t3 DB[15:0] setup time to CS# (WR#) rising edge: write cycle ns t4 DB[15:0] hold time from CS# (WR#) rising edge: write cycle ns t5w WR# (CS#) hold time from CS# (WR#) rising edge: write cycle ns t5r RD# (CS#) hold time from CS# (RD#) rising edge: read cycle ns t6 AB[18:1], UB#, LB# hold time from CS# (WR#, RD#) rising edge ns t7 CS# (RD#) falling edge to DB[15:0] driven: read cycle ns t8 CS# (RD#) falling edge to valid Data: read cycle - 4xT mclk +16-4xT mclk +23 ns t9 DB[15:0] hold time from CS# (RD#) rising edge: read cycle ns t10w End of write to next read/write ns t10r End of read to next read/write T mclk +9 - T mclk ns t11w CS# (WR#) pulse width for write cycle ns t12w CS# (WR#) rise to next CS# (WR#) rise: write cycle 3xT mclk +6-3xT mclk +6 - ns T mclk = period of internal MCLK clock signal S1D13781 Series Hardware Functional Specification EPSON 35
36 9.4.2 Direct 16-bit Mode 2 Timing AB[18:1] t1 t6 t1 t6 t1 CS# Control CS# WRU#, WRL# RDU#, RDL# RD#/WR# Control CS# t2 t2 t11 t10 t12w t11 t5 t5 t10 t2 t2 WRU#, WRL# RDU#, RDL# t11 t10 t11 DB[15:0] (write) t3 valid t4 t3 valid t4 t9 t9 DB[15:0] (read) t7 valid t7 valid t8 t8 Figure 9-7: Direct 16-bit Mode 2 Timing 36 EPSON S1D13781 Series Hardware Functional Specification
37 Table 9-8: Direct 16-bit Mode 2 Timing Symbol Parameter 3.3 Volt 1.8 Volt Min Max Min Max Units t1 AB[18:1] setup time to CS# (WRU#, WRL#, RDU#, RDL#) ns t2 WRU#, WRL#, RDU#, RDL# (CS#) setup time to CS# (WRU#, WRL#, RDU#, RDL#) ns t3 DB[15:0] setup time to CS# (WRU#, WRL#) rising edge: write cycle ns t4 DB[15:0] hold time from CS# (WRU#, WRL#) rising edge: write cycle ns t5w WRU#, WRL# (CS#) hold time from CS# (WRU#, WRL#) rising edge: write cycle ns t5r RDU#, RDL# (CS#) hold time from CS# (RDU#, RDL#) rising edge: read cycle ns t6 AB[18:1] hold time from CS# (WRU#, WRL#, RDU#, RDL#) rising edge ns t7 CS# (RDU#, RDL#) falling edge to DB[15:0] driven: read cycle ns t8 CS# (RDU#, RDL#) falling edge to valid Data: read cycle - 4xT mclk +16-4xT mclk +23 ns t9 DB[15:0] hold time from CS# (RDU#, RDL#) rising edge: read cycle ns t10w End of write to next read/write ns t10r End of read to next read/write T mclk +9 - T mclk ns t11w CS# (WRU#, WRL#) pulse width for write cycle ns t12w CS# (WRU#, WRL#) rise to next CS# (WRU#, WRL#) rise: write cycle 3xT mclk +6-3xT mclk +6 - ns T mclk = period of internal MCLK clock signal S1D13781 Series Hardware Functional Specification EPSON 37
38 9.4.3 Indirect 16-bit Mode 1 Timing P/C# UB# LB# t1 t6 t1 t6 t1 CS# Control CS# WR# RD# t2 t11 t10 t11 t5 t10 t2 RD#/WR# Control CS# t2 t12w t5 t2 WR# RD# t11 t10 t11 DB[15:0] (write) t3 valid t4 t3 valid t4 t9 t9 DB[15:0] (read) t7 valid t7 valid t8 t8 Figure 9-8: Indirect 16-bit Mode 1 Timing 38 EPSON S1D13781 Series Hardware Functional Specification
39 Table 9-9: Indirect 16-bit Mode 1 Timing Symbol Parameter 3.3 Volt 1.8 Volt Min Max Min Max Units t1 P/C#, UB#, LB# setup time to CS# (WR#, RD#) ns t2 WR#, RD# (CS#) setup time to CS# (WR#, RD#) ns t3 DB[15:0] setup time to CS# (WR#) rising edge: write cycle ns t4 DB[15:0] hold time from CS# (WR#) rising edge: write cycle ns t5w WR# (CS#) hold time from CS# (WR#) rising edge: write cycle ns t5r RD# (CS#) hold time from CS# (RD#) rising edge: read cycle ns t6 P/C#, UB#, LB# hold time from CS# (WR#, RD#) rising edge ns t7 CS# (RD#) falling edge to DB[15:0] driven: read cycle ns t8 CS# (RD#) falling edge to valid Data: read cycle - 4xT mclk +16-4xT mclk +23 ns t9 DB[15:0] hold time from CS# (RD#) rising edge: read cycle ns t10w End of write to next read/write ns t10r End of read to next read/write T mclk +9 - T mclk ns t11w CS# (WR#) pulse width for write cycle ns t12w CS# (WR#) rise to next CS# (WR#) rise: write cycle 3xT mclk +6-3xT mclk +6 - ns T mclk = period of internal MCLK clock signal Table 9-10: Indirect 16-bit Mode 1 Function Select P/C# WR# RD# Comments Command Write (register address) Data (Parameter) Write inhibit Data (Parameter) Read S1D13781 Series Hardware Functional Specification EPSON 39
40 9.4.4 Indirect 16-bit Mode 2 Timing P/C# t1 t6 t1 t6 t1 CS# Control CS# WRU#, WRL# RDU#, RDL# t2 t11 t10 t11 t5 t10 t2 RD#/WR# Control t12w CS# t2 t5 t2 WRU#, WRL# RDU#, RDL# t11 t10 t11 DB[15:0] (write) t3 valid t4 t3 valid t4 t9 t9 DB[15:0] (read) t7 valid t7 valid t8 t8 Figure 9-9: Indirect 16-bit Mode 2 Timing 40 EPSON S1D13781 Series Hardware Functional Specification
41 Table 9-11: Indirect 16-bit Mode 2 Timing Symbol Parameter 3.3 Volt 1.8 Volt Min Max Min Max Units t1 P/C# setup time to CS# (WRU#, WRL#, RDU#, RDL#) ns t2 WRU#, WRL#, RDU#, RDL# (CS#) setup time to CS# (WRU#, WRL#, RDU#, RDL#) ns t3 DB[15:0] setup time to CS# (WRU#, WRL#) rising edge: write cycle ns t4 DB[15:0] hold time from CS# (WRU#, WRL#) rising edge: write cycle ns t5w WRU#, WRL# (CS#) hold time from CS# (WRU#, WRL#) rising edge: write cycle ns t5r RDU#, RDL# (CS#) hold time from CS# (RDU#, RDL#) rising edge: read cycle ns t6 P/C# hold time from CS# (WRU#, WRL#, RDU#, RDL#) rising edge ns t7 CS# (RDU#, RDL#) falling edge to DB[15:0] driven: read cycle ns t8 CS# (RDU#, RDL#) falling edge to valid Data: read cycle - 4xT mclk +16-4xT mclk +23 ns t9 DB[15:0] hold time from CS# (RDU#, RDL#) rising edge: read cycle ns t10w End of write to next read/write ns t10r End of read to next read/write T mclk +9 - T mclk ns t11w CS# (WRU#, WRL#) pulse width for write cycle ns t12w CS# (WRU#, WRL#) rise to next CS# (WRU#, WRL#) rise: write cycle 3xT mclk +6-3xT mclk +6 - ns T mclk = period of internal MCLK clock signal Table 9-12: Indirect 16-bit Mode 2 Function Select P/C# WRU#, WRL# RDU#, RDL# Comments Command Write (register address) Data (Parameter) Write inhibit Data (Parameter) Read S1D13781 Series Hardware Functional Specification EPSON 41
42 9.4.5 Direct 8-bit Timing AB[18:0] t1 t6 t1 t6 t1 CS# Control CS# WR# RD# t2 t11 t10 t11 t5 t10 t2 RD#/WR# Control CS# t2 t12w t5 t2 WR# RD# t11 t10 t11 DB[7:0] (write) t3 valid t4 t3 valid t4 t9 t9 DB[7:0] (read) t7 valid t7 valid t8 t8 Figure 9-10: Direct 8-bit Timing 42 EPSON S1D13781 Series Hardware Functional Specification
43 Table 9-13: Direct 8-bit Timing Symbol Parameter 3.3 Volt 1.8 Volt Min Max Min Max Units t1 AB[18:0] setup time to CS# (WR#, RD#) ns t2 WR#, RD# (CS#) setup time to CS# (WR#, RD#) ns t3 DB[7:0] setup time to CS# (WR#) rising edge: write cycle ns t4 DB[7:0] hold time from CS# (WR#) rising edge: write cycle ns t5w WR# (CS#) hold time from CS# (WR#) rising edge: write cycle ns t5r RD# (CS#) hold time from CS# (RD#) rising edge: read cycle ns t6 AB[18:0] hold time from CS# (WR#, RD#) rising edge ns t7 CS# (RD#) falling edge to DB[7:0] driven: read cycle ns t8 CS# (RD#) falling edge to valid Data: read cycle - 4xT mclk +17-4xT mclk +23 ns t9 DB[7:0] hold time from CS# (RD#) rising edge: read cycle ns t10w End of write to next read/write ns t10r End of read to next read/write T mclk +9 - T mclk ns t11w CS# (WR#) pulse width for write cycle ns t12w CS# (WR#) rise to next CS# (WR#) rise: write cycle 3xT mclk +6-3xT mclk +6 - ns T mclk = period of internal MCLK clock signal S1D13781 Series Hardware Functional Specification EPSON 43
44 9.4.6 Indirect 8-bit Timing t1 t6 t1 t6 t1 P/C# CS# Control CS# WR# RD# t2 t11 t10 t11 t5 t10 t2 RD#/WR# Control CS# t2 t12w t5 t2 WR# RD# t11 t10 t11 DB[7:0] (write) t3 valid t4 t3 valid t4 t9 t9 DB[7:0] (read) t7 valid t7 valid t8 t8 Figure 9-11: Indirect 8-bit Timing 44 EPSON S1D13781 Series Hardware Functional Specification
45 Table 9-14: Indirect 8-bit Timing Symbol Parameter 3.3 Volt 1.8 Volt Min Max Min Max Units t1 P/C# setup time to CS# (WR#, RD#) ns t2 WR#, RD# (CS#) setup time to CS# (WR#, RD#) ns t3 DB[7:0] setup time to CS# (WR#) rising edge: write cycle ns t4 DB[7:0] hold time from CS# (WR#) rising edge: write cycle ns t5w WR# (CS#) hold time from CS# (WR#) rising edge: write cycle ns t5r RD# (CS#) hold time from CS# (RD#) rising edge: read cycle ns t6 P/C# hold time from CS# (WR#, RD#) rising edge ns t7 CS# (RD#) falling edge to DB[7:0] driven: read cycle ns t8 CS# (RD#) falling edge to valid Data: read cycle - 4xT mclk +17-4xT mclk +23 ns t9 DB[7:0] hold time from CS# (RD#) rising edge: read cycle ns t10w End of write to next read/write ns t10r End of read to next read/write T mclk +9 - T mclk ns t11w CS# (WR#) pulse width for write cycle ns t12w CS# (WR#) rise to next CS# (WR#) rise: write cycle 3xT mclk +6-3xT mclk +6 - ns T mclk = period of internal MCLK clock signal Table 9-15: Indirect 8-bit Function Select P/C# WR# RD# Comments Command Write (register address) Data (Parameter) Write inhibit Data (Parameter) Read S1D13781 Series Hardware Functional Specification EPSON 45
46 9.4.7 SPI Timing SCS# t1 t7 t8 D15 D14 D13 D2 D1 D0 SI D7 D6 D5 D4 D2 D1 D0 t2 t3 D15 D14 D13 D2 D1 D0 SO D7 D6 D5 D4 D2 D1 D0 Driven Low t9 Driven Low SCK t4 t5 t6 Burst Transfer SCS# SI D15D14 D13 D2 D1 D0 D15 D14 D13 D7 D6 D5 D4 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D15 D14 D2 D1 D0 D7 D6 D2 D1 D0 D15D14 D13 D2 D1 D0 D15 D14 D13 D3 D2 D1 D0 D15 D14 D2 D1 D0 SO D7 D6 D5 D4 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D2 D1 D0 SCK Note: SPI data is always MSB first. SO is always driven Low when no data is present. Figure 9-12: SPI Timing 46 EPSON S1D13781 Series Hardware Functional Specification
47 Table 9-16: SPI Timing Symbol Parameter 3.3 Volt 1.8 Volt Units Min Max Min Max t1 Chip select setup time ns t2 SI Data setup time ns t3 SI Data hold time ns t4 Serial clock pulse width low (high) ns t5 Serial clock pulse width high (low) ns t6 Serial clock period ns t7 Chip select hold time ns t8 Chip select de-assert to reassert ns t9 SCK falling edge to SO hold time ns NOTE: C L = 10pF for SPI timing Table 9-17: SPI Function Select Command bit Write bit Read bit Write bit Read the other reserved Comments S1D13781 Series Hardware Functional Specification EPSON 47
48 9.5 Panel Interface Timing General STN Panel Timing The timing parameters required to drive an STN panel are shown below. Timing details for each supported panel type are provided in the following sections. 18Ts MOD/VS TE 11 TE 10 MOD 2 VS VPS HS HDISP HPS HNDP HSW VDISP VNDP VSW HDISP VDISP Figure 9-13: STN Panel Timing Parameters 48 EPSON S1D13781 Series Hardware Functional Specification
49 Table 9-18: STN Panel Timing Parameter Definition and Register Summary Symbol Description Derived From Units HDISP 9 Horizontal Display Width (REG[24h] bits 6-0) x 8 HNDP 4 Horizontal Non-Display Period REG[26h] bits 6-0 HPS 5 HS Pulse Start Position REG[2Eh] bits 6-0 Ts HSW 5 HS Pulse Width REG[2Ch] bits 6-0 VDISP 7,8 Vertical Display Height REG[28h] bits 9-0 VNDP 6,7 Vertical Non-Display Period REG[2Ah] bits 7-0 Lines VPS 3,8 VS Pulse Start Position (REG[32h] bits 7-0) + 1 (HT) VSW 3 VS Pulse Width REG[30h] bits T S = pixel clock period 2. MOD toggles every frame when REG[20h] bits 13-8 (MOD rate) is 00h. 3. REG[32h] bits 7-0 should be programmed to 00h, REG[30h] bits 5-0 should be programmed to 01h. 4. HNDP >= 18Ts 5. 18Ts <= (HPS + HSW) <= HNDP 6. VNDP > 0 7. VDISP + VNDP < VDISP + VPS < For STN panels, HDISP must be set to a minimum of 32 pixels and must be increased by multiples of 16 pixels. 10. REG[22h] bits 6-5 = 01b 11. REG[22h] bits 6-5 = 10b S1D13781 Series Hardware Functional Specification EPSON 49
50 9.5.2 Single Color 8-Bit Panel Format 2 Timing VS HS DE (MOD) PDT[7:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 HS DE (MOD) PDCLK (CK) 2Ts Ts 2Ts 2Ts Ts 2Ts 2Ts Ts 2Ts PDT7 PDT6 PDT5 PDT4 PDT3 PDT2 PDT1 PDT0 1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3 Ts 1-B3 1-R4 1-G4 1-B4 1-R5 1-G5 1-B5 1-R6 Ts Ts Ts Ts 1-G6 1-B6 1-R7 1-G7 1-B7 1-R8 1-G8 1-B8 Ts Ts 1-G318 1-B318 1-R319 1-G319 1-B319 1-R320 1-G320 1-B320 Notes: - The duty cycle of PDCLK (CK) changes in order to process 8 pixels in 3 PDCLK (CK) rising clocks - Ts = Pixel clock period, PDCLK (CK) - Diagram drawn with 2 HS vertical blank period - Example timing for a 320x240 panel Figure 9-14: Single Color 8-Bit Panel Timing (Format 2) 50 EPSON S1D13781 Series Hardware Functional Specification
51 Sync Timing t1 t2 VS t4 t3 HS t5 DE (MOD) Data Timing HS t6 t7 t8 t14 t11 t9 t10 PDCLK (CK) t12 t13 PDT[7:0] 1 2 Figure 9-15: Single Color 8-Bit Panel AC Timing (Format 2) 1. Ts = pixel clock period Table 9-19: Single Color 8-Bit Panel AC Timing (Format 2) Symbol Parameter Min Units t1 VS setup to HS falling edge HPS + HSW. Ts (Note 1) t2 VS hold from HS falling edge HDISP + HNDP - t1 Ts t3 HS period HDISP + HNDP Ts t4 HS pulse width HSW Ts t5 DE (MOD) transition to HS rising edge HPS Ts t6 PDCLK (CK) falling edge to HS rising edge HPS - 17 Ts t7 PDCLK (CK) falling edge to HS falling edge HPS + HPW - 17 Ts t8 HS falling edge to PDCLK (CK) falling edge HNDP HPS - HSW Ts t9 PDCLK (CK) period 2 Ts t10 PDCLK (CK) pulse width low 1 Ts t11 PDCLK (CK) pulse width high 1 Ts t12 PDT[7:0] setup to PDCLK (CK) falling edge 1 Ts t13 PDT[7:0] hold to PDCLK (CK) falling edge 1 Ts t14 HS falling edge to PDCLK (CK) rising edge HNDP HPS - HSW Ts S1D13781 Series Hardware Functional Specification EPSON 51
52 9.5.3 Single Color 16-Bit Panel Timing VS HS DE (MOD) PDT[15:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 HS DE (MOD) PDCLK (CK) Notes: PDT15 PDT14 PDT13 PDT12 PDT11 PDT10 PDT9 PDT8 PDT7 PDT6 PDT5 PDT4 PDT3 PDT2 PDT1 PDT0 3Ts 2Ts 3Ts 3Ts 2Ts 3Ts 3Ts 2Ts 2Ts 3Ts 3Ts 1-R1 1-G6 1-B11 1-G635 1-B1 1-R7 1-G12 1-G636 1-G2 1-B7 1-R13 1-R637 1-R3 1-G8 1-B13 1-B637 1-B3 1-R9 1-G14 1-G638 1-G4 1-B9 1-R15 1-R639 1-R5 1-G10 1-B15 1-B639 1-B5 1-R11 1-G16 1-G640 1-G1 1-B6 1-R12 1-R636 1-R2 1-G7 1-B12 1-B636 1-B2 1-R8 1-G13 1-G637 1-G3 1-B8 1-R14 1-R638 1-R4 1-G9 1-B14 1-B638 1-B4 1-R10 1-G15 1-G639 1-G5 1-B10 1-R16 1-R640 1-R6 1-G11 1-B16 1-B640 - The duty cycle of PDCLK (CK) changes in order to process 16 pixels in 3 PDCLK (CK) rising clocks - Ts = Pixel clock period, PDCLK (CK) - Diagram drawn with 2 HS vertical blank period - Example timing for a 640x480 panel 3Ts 3Ts 2Ts Figure 9-16: Single Color 16-Bit Panel Timing 3Ts 3Ts 3Ts 3Ts 2Ts 3Ts 52 EPSON S1D13781 Series Hardware Functional Specification
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