184PIN DDR400 Unbuffered DIMM 512MB With 64Mx8 CL3. Description. Placement. Features PCB: Transcend Information Inc.

Transcription

1 TS6DNJ S Description The TS64MLD64V4J is a 64M x 64bits Double Data Rate SDRAM high-density Module for 400.The TS64MLD64V4J consists of 8pcs CMOS 64Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP-II 400mil packages and a 2048 bits serial EEPROM on a 184-pin printed circuit board. The TS64MLD64V4J is a Dual In-Line Memory Module and is intended for mounting into 184-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Placement A B Features RoHS compliant products. Power supply: VDD: 2.6V ± 0.1V, VDDQ: 2.6V ± 0.1V Max clock Freq: 200MHZ. Double-data-rate architecture; two data transfers per clock cycle Differential clock inputs (CK and /CK) DLL aligns DQ and transition with CK transition Auto and Self Refresh 7.8us refresh interval. Data I/O transactions on both edge of data strobe. Edge aligned data output, center aligned data Serial Presence Detect (SPD) with serial EEPROM SSTL-2 compatible inputs and outputs. MRS cycle with address key programs. CAS Latency (Access from column address): 3 Burst Length (2,4,8) Data Sequence (Sequential & Interleave) H G F E PCB: D C I Transcend Information Inc.

2 TS6DNJ S Dimensions Identification Side Millimeters Inches A ± ±0.008 B C D E 29.46± ± F G H I 1.27± ±0.004 (Refer Placement) Symbol BA0, BA1 DQ0~DQ63 0~7 CK0, /CK0 CK1, /CK1 CK2, /CK ~7 VDD VDDQ VREF VDDSPD SA0~SA2 SCL SDA VSS NC Function Address input Data Input / Output. Data strobe input/output Clock Input. Clock Enable Input. Chip Select Input. Row Address Strobe Column Address Strobe Write Enable Data-in Mask +2.6 Voltage power supply +2.6 Voltage Power Supply for Power Supply for Reference +2.5 Voltage Serial EEPROM Power Supply Address in EEPROM Serial PD Clock Serial PD Add/Data input/output Ground No Connection Transcend Information Inc.

3 TS6DNJ S outs: No Name No Name No Name No Name 01 VREF 47 *8 93 VSS 139 VSS 02 DQ0 48 A0 94 DQ4 140 *8 03 VSS 49 *CB2 95 DQ5 141 A10 04 DQ1 50 VSS 96 VDDQ 142 *CB *CB VDDQ 06 DQ2 52 BA1 98 DQ6 144 *CB7 07 VDD 53 DQ32 99 DQ7 145 VSS 08 DQ3 54 VDDQ 100 VSS 146 DQ36 09 NC 55 DQ NC 147 DQ37 10 NC NC 148 VDD 11 VSS 57 DQ NC DQ8 58 VSS 104 VDDQ 150 DQ38 13 DQ9 59 BA0 105 DQ DQ DQ DQ VSS 15 VDDQ 61 DQ DQ44 16 *CK1 62 VDDQ 108 VDD */CK DQ DQ45 18 VSS 64 DQ DQ VDDQ 19 DQ * DQ11 66 VSS 112 VDDQ 158 * NC VDDQ 68 DQ DQ VSS 23 DQ16 69 DQ *A DQ46 24 DQ17 70 VDD 116 VSS 162 DQ NC 117 DQ NC 26 VSS 72 DQ A VDDQ 27 A9 73 DQ DQ52 28 DQ18 74 VSS 120 VDD 166 DQ53 29 A7 75 */CK2 121 DQ NC 30 VDDQ 76 *CK2 122 A8 168 VDD 31 DQ19 77 VDDQ 123 DQ A VSS 170 DQ54 33 DQ24 79 DQ A6 171 DQ55 34 VSS 80 DQ DQ VDDQ 35 DQ25 81 VSS 127 DQ NC NC 128 VDDQ 174 DQ60 37 A4 83 DQ DQ61 38 VDD 84 DQ A3 176 VSS 39 DQ26 85 VDD 131 DQ DQ VSS 178 DQ62 41 A2 87 DQ DQ DQ63 42 VSS 88 DQ *CB4 180 VDDQ 43 A1 89 VSS 135 *CB5 181 SA0 44 *CB0 90 NC 136 VDDQ 182 SA1 45 *CB1 91 SDA 137 CK0 183 SA2 46 VDD 92 SCL 138 /CK0 184 VDDSPD *Please refer Block Diagram Transcend Information Inc.

4 TS6DNJ S Block Diagram DQ0~DQ CK1,/CK MX8 SDRAM 64MX8 64MX8 SDRAM SDRAM MX8 SDRAM CK2,/CK2 64MX8 SDRAM 64MX8 SDRAM 64MX8 SDRAM 64MX8 SDRAM SCL Serial EEPROM SCL SDA A0 A1 A2 SDA SA0 SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. Transcend Information Inc.

5 TS6DNJ S ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply to Vss VDD, VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55~+150 C Power dissipation PD 12 W Short circuit current IOS 50 ma Operating Temperature TA 0 ~ 70 C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70 C) Parameter Symbol Min Max Unit Note Supply voltage VDD V I/O Supply voltage VDDQ V I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination voltage VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V 4 Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4 Input Voltage Level, CK and /CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and /CK inputs VID(DC) 0.3 VDDQ+0.6 V 3 Input crossing point voltage, CK and /CK inputs VIX(DC) V 5 Input leakage current II -2 2 ua Output leakage current IOZ -5 5 ua Output High Current (Normal strength driver) VOUT= VTT V IOH ma Output Low Current (Normal strength driver) VOUT= VTT 0.84V IOL 16.8 ma Output High Current (Half strength driver) VOUT= VTT V IOH -9 ma Output High Current (Half strength driver) IOL 9 ma VOUT= VTT V Note: 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled. TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of <=3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. Transcend Information Inc.

6 TS6DNJ S DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, VDD=2.7V TA = 10 C) Operating current - One bank Active-Precharge; trc=trcmin; DQ, and inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle Parameter Symbol Max. Unit Note IDD0 1,320 ma Operating current - One bank operation; One bank open, Burst=4; Reads refer to the following page for detailed test condition. IDD1 1,480 ma Percharge power-down standby current; All banks idle; power-down mode; = <VIL(max); VIN = VREF for DQ, and IDD2P 40 ma Precharge Floating standby current; CS# > =VIH(min);All banks idle; > = VIH(min); Address and other control inputs changing once per clock IDD2F 240 ma cycle; VIN = VREF for DQ, and Active power - down standby current; one bank active; power-down mode; <= VIL (max); VIN = VREF for DQ, and IDD3P 280 ma Active standby current; CS# >= VIH(min); >=VIH(min); one bank active; active - precharge; trc=trasmax; DQ, and inputs changing twice per clock cycle; IDD3N 760 ma address and other control inputs changing once per clock cycle Operating current - burst read; Burst length = 2; reads; continuous burst; One bank active; address and control inputs changing once per clock cycle; IDD4R 1,600 ma 50% of data changing at every burst; lout = 0 ma Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; DQ, and inputs changing twice per clock cycle, IDD4W 1,920 ma 50% of input data changing at every burst Auto refresh current; trc = trfc(min), 10*tCK for 400 at 200MHz; distributed refresh IDD5 2,120 ma Self refresh current; <= 0.2V; External clock should be on; IDD6 40 ma Operating current - Four bank operation; Four bank interleaving with BL=4 -Refer to the following page for detailed test condition IDD7 3,440 ma Note: 1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor. Transcend Information Inc.

7 TS6DNJ S AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Note Input High (Logic 1) Voltage, DQ, and signals VIH(AC) VREF V Input Low (Logic 0) Voltage, DQ, and signals VIL(AC) VREF V Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ V 1 Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ *VDDQ V 2 Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz. AC OPERATING TEST CONDITIONS (VDD=2.6, VDDQ=2.6, TA=0 to 70 C) Parameter Value Unit Note Input reference voltage for Clock 0.5*VDDQ V Input signal maximum peak swing 1.5 V Input Levels (VIH/VIL) VREF+0.31/VREF-0.31 V Input timing measurement reference level VREF V Output timing measurement reference level VTT V Output load condition See Load Circuit INPUT / OUTPUT CAPACITANCE (VDD = 2.6V, VDDQ = 2.6V, TA = 25 C, f = 1MHz) Parameter Symbol Min Max Unit Input capacitance ( BA0~BA1,,, ) Input capacitance (0) Input capacitance (0) Input capacitance (CK1~CK2) Input capacitance (0~7) Data and input/output capacitance (DQ0~DQ63) CIN1 CIN2 CIN3 CIN4 CIN5 COUT pf pf pf pf pf pf Transcend Information Inc.

8 TS6DNJ S AC TIMING PARAMETERS & SPECIFICATIONS (These AC characteristics were tested on the Component) Parameter Symbol Min Max Unit Note Row cycle time trc 55 ns Refresh row cycle time trfc 70 ns Row active time tras 40 70K ns to delay trcd 15 ns Row active to Row active delay trp 15 ns Row active to Row active delay trrd 10 ns Write recovery time twr 15 ns Last data in to Read command twtr 2 tck Clock cycle time tck 5 10 ns 16 Clock high level width tch tck Clock low level width tcl tck -out access time from CK /CK tck ns Output data access time from CK /CK tac ns Data strobe edge to output data edge tq 0.4 ns 13 Read Preamble trpre tck Read Postamble trpst tck CK to valid -in ts tck Write preamble setup time twpres 0 ps 5 Write preamble twpre 0.25 tck Write postamble twpst tck 4 falling edge to CK rising-setup time tdss 0.2 tck falling edge from CK rising-hold time tdsh 0.2 tck -in high level width th 0.35 tck -in low level width tl 0.35 tck Address and Control input setup time tis 0.6 ns 7~10 Address and Control input hold time tih 0.6 ns 7~10 Data-out high-impedance time from CK, /CK thz - tac max ns 3 Data-out low-impedance time from CK, /CK tlz tac min tac max ns 3 Mode register set cycle time tmrd 2 ns DQ & setup time to tds 0.4 ns DQ & hold time to tdh 0.4 ns DQ & input pulse width tdipw 1.75 ns 9 Transcend Information Inc.

9 TS6DNJ S Control &Address input pulse width for each input tipw 2.2 ns 9 Refresh interval time tref 7.8 us 6 Output valid window TQH thp-tqhs ns 12 Clock half period thp tclmin/tchmin ns 11,12 Data hold skew factor tqhs 0.5 ns 12 Auto Precharge write recovery + precharge time tdal - - ns 14 Exit self refresh to non-read command txsnr 75 ns Exit self refresh to read command txsrd 200 Note: 1.VID is the magnitude of the difference between the input level on CK and the input level on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 3. thz and tlz transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). 4. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 5. The specific requirement is that be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, will be transitioning from High-Z to logic LOW. If a previous write was in progress, could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on ts. 6. A maximum of eight AUTO REFRESH commands can be posted to any given SDRAM device. 7. For command/address input slew rate 0.5 V/ns 8. For CK & CK slew rate 0.5 V/ns 9. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 10. Slew Rate is measured between VOH(ac) and VOL(ac). 11. Min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch)... For example, tcl and tch are = 50% of the period, less the half period jitter (tjit(hp)) of the clock source, and less the half period jitter due to crosstalk (tjit(crosstalk)) into 12. tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tq:consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 14. tdal = (twr/tck) + (trp/tck) 15. In all circumstances, txsnr can be satisfied using txsnr=trfcmin+1*tck 16. The only time that the clock frequency is allowed to change is during self-refresh mode. ns Transcend Information Inc.

10 TS6DNJ S SIMPLIFIED TRUTH TABLE (V=Valid, X=Don t Care, H=Logic High, L=Logic Low) COMMAND n-1 n BA0,1 A10/AP A0~A9, A11, A12 Note Register Extended Mode Register Set H X L L L L OP CODE 1,2 Register Mode Register Set H X L L L L OP CODE 1,2 Refresh Auto Refresh H 3 H L L L H X Entry L 3 Self Refresh L H H H 3 Exit L H X H X X X 3 Bank Active & Row Addr. H X L L H H V Row Address Read & Column Address Write & Column Address Auto Precharge Disable L Column 4 H X L H L H V Address Auto Precharge Enable H (A0~A9) 4 Auto Precharge Disable L Column 4 H X L H L L V Address Auto Precharge Enable H (A0~A9) 4, 6 Burst Stop H X L H H L X 7 Bank Selection V L Precharge H X L L H L X All Banks X H 5 Active Power Down Entry H L H X X X L V V V Exit L H X X X X X Precharge Power Down Mode Entry H L Exit L H H X X X L H H H H X X X L V V V H X X 8 No Operation Command H X H X X X 9 X L H H H 9 Note: 1. OP Code: Operand Code. A0 ~ A12 & BA0 ~ BA1: Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatically precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1: Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at trp after the end of burst. 7. Burst stop command is valid at every burst length. 8. sampled at the rising and falling edges of the and Data-in is masked at the both edges (Write latency is 0). 9. This combination is not defined for any function, which means "No Operation (NOP)" in SDRAM. X Transcend Information Inc.

11 TS6DNJ S SERIAL PRESENCE DETECT SPECIFICATION Serial Presence Detect Byte No. Function Described Standard Specification Vendor Part 0 # of Bytes Written into Serial Memory 128bytes 80 1 Total # of Bytes of S.P.D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 07 3 # of Row Addresses on this Assembly 13 0D 4 # of Column Addresses on this Assembly 11 0B 5 # of Module Rows on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width of this Assembly VDDQ and Interface Standard of this Assembly SSTL SDRAM Cycle Time at CAS Latency=3 5ns SDRAM Access Time from Clock at CL=3 0.65ns DIMM configuration type (non-parity, Parity, ECC) Non ECC Refresh Rate Type 7.8us/Self Refresh Primary SDRAM Width X Error Checking SDRAM Width X Min Clock Delay for Back to Back Random Column Address tccd=1clk Burst Lengths Supported 2,4,8 0E 17 # of banks on each SDRAM device 4 bank CAS Latency supported 2.5, CS Latency 0 CLK WE Latency 1 CLK SDRAM Module Attributes Differential Clock Input SDRAM Device Attributes: General Fast/concurrent AP C0 23 SDRAM Cycle Time CL=2.5 6ns SDRAM Access from Clock CL= ns SDRAM Cycle Time CL= SDRAM Access from Clock CL= Minimum Row Precharge Time (trp) 15ns 3C 28 Minimum Row Active to Row Activate delay (trrd) 10ns Minimum RAS to CAS Delay (trcd) 15ns 3C 30 Minimum active to Precharge time (tras) 40ns Module ROW density 512MB Command/Address Input Setup Time 0.6ns Command/Address Input Hold Time 0.6ns Data Signal Input Setup Time 0.4ns Data Signal Input Hold Time 0.4ns Superset Information SDRAM Minimum Active to Active/Auto Refresh Time(tRC) 55ns SDRAM Minimim Auto-Refresh to Active/Auto-Refresh Commmand Period(tRFC) 70ns 46 Transcend Information Inc.

12 TS6DNJ S 43 SDRAM Maximum Device Cycle Time(tCK max) 10ns SDRAM -DQ Skew for and associated DQ signals(tq max) 0.4ns SDRAM Read Data Hold Skew Factor(tQHS) 0.5ns PLL Relock Time ~61 Superset Information SPD Data Revision Code REV Checksum for Bytes 0-62 AF BE Manufacturers JEDEC ID Transcend 7F, 4F 72 Manufacturing Location T D 4C Manufacturers Part Number TS64MLD64V4J A Revision Code Manufacturing Date By Manufacturer Variable Assembly Serial Number By Manufacturer Variable Manufacturer Specific Data ~255 Unused Storage Locations Undefined - Transcend Information Inc.