DIGITAL SYSTEM DESIGN LAB

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1 EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flip-flops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC 74 NAND gate IC, IC 742 NOR gate IC, IC 744 NOT gate IC, 7476 IC THEORY: FLIP-FLOP: "Flip-flop" is the common name given to two-state devices which offer basic memory for sequential logic operations. Flip-flops are heavily used for digital data storage and transfer and are commonly used in banks called "register" for the storage of binary numerical data. CLOCKED FLIP-FLOPS The clock is a continuous sequence of square wave pulses. There are a number of reasons for the importance of the clock. Clearly it is essential for doing any kind of counting or timing operation. But, its most important role is in providing synchronization to the digital circuit. Each clock pulse may represent the transition to a new digital state of a so-called state machine (simple processor) we will soon encounter. Or a clock pulse may correspond to the movement of a bit of data from one location in memory to another. A digital circuit coordinates these various functions by the synchronization provided by a single clock signal which is shared throughout the circuit.. DEPARTMENT OF ECE, VKCET Page 44

2 SR FLIP- FLOP LOGIC DIAGRAM SYMBOL TRUTH TABLE T FLIP- FLOP LOGIC DIAGRAM USING IC 7476 TRUTH TABLE D FLIP- FLOP LOGIC DIAGRAM USING IC 7476 TRUTH TABLE DEPARTMENT OF ECE, VKCET Page 45

3 SR FLIP-FLOP: An S-R flip-flop consists of two cross-coupled NOR gates. An S-R flip-flop can also be design using cross-coupled NAND gates. A clocked S-R flip-flop has an additional clock input so that the S and R inputs are active only when the clock is high. When the clock goes low, the state of flip-flop is latched and cannot change until the clock goes high again. Therefore, the clocked S-R flip-flop is also called enabled S-R flip-flop. A D latch combines the S and R inputs of an S-R latch into one input by adding an inverter. When the clock is high, the output follows the D input, and when the clock goes low, the state is latched. A S-R flip-flop can be converted to T-flip flop by connecting S input to Q and R to Q. T FLIP FLOP: The basic digital memory circuit is known as flip flop. Its two stable states which are known as the state state. It can be obtained by using NAND or NOR gates. Generally there are two inputs to the flip flops (R, S or J K) and two outputs Q and Q. The outputs Q and Q are always complementary. The circuit has two stable state Q=which is referred to as the state( or set state ) whereas in the other stable state Q= which is referred to as the sate ( or reset state ). If the circuit is in state. It continues to remain in this state and similarly if it is in state, it continues to remain in this state. This property of the circuit is referred to as memory, that is it can store bit of digital information. In a JK flip flop, if J=K the resulting flip flop is referred to as a T Flip Flop, It has only input, referred to as T input. Its truth table is given in table. If T= it acts as a toggle witch for every clock pulse the output Q changes. D- FLIP-FLOP (TOGGLE SWITCH): The operations of a D flip-flop are much more simpler. It has only one input addition to the clock. It is very useful when a single data bit ( or ) is to be stored. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and. DEPARTMENT OF ECE, VKCET Page 46

4 JK FLIP- FLOP LOGIC DIAGRAM USING IC 7476 TRUTH TABLE MASTER SLAVE JK FLIP- FLOP LOGIC DIAGRAM TRUTH TABLE DEPARTMENT OF ECE, VKCET Page 47

5 stores a. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a. To implement D flip-flop we require NAND gates and NOR gates J-K FLIP-FLOP: JK Flip-Flop is the most versatile binary strange element. It can perform all the functions of SR and D flip-flop. The uncertainty in the State of SR Flip- Flop when S = R = can be eliminated by using JK Flip-Flop. MASTER-SLAVE JK FLIP-FLOP: Although JK flip-flop is an improvement on the clocked SR flip-flop it still suffers from timing problems called "race" if the output Q changes state before the timing pulse of the clock input has time to go "OFF", so the timing pulse period (T) must be kept as short as possible (high frequency). As this is sometimes not possible with modern TTL IC's the much improved Master-Slave J-K Flip-Flop was developed. This eliminates all the timing problems by using two SR flip-flops connected together in series, one for the "Master" circuit, which triggers on the leading edge of the clock pulse and the other, the "Slave" circuit, which triggers on the falling edge of the clock pulse. The master-slave JK flip flop consists of two flip flops arranged so that when the clock pulse enables the first, or master, it disables the second, or slave. When the clock changes state again (i.e., on its falling edge) the output of the master latch is transferred to the slave latch. Again, toggling is accomplished by the connection of the output with the input AND gates. PROCEDURE:. Place the IC on IC Trainer Kit. 2. Connect VCC and ground to respective pins of IC Trainer Kit. 3. Connect the inputs to the input switches provided in the IC Trainer Kit. DEPARTMENT OF ECE, VKCET Page 48

6 4. Connect the outputs to the switches of O/P LEDs 5. Apply various combinations of inputs according to the truth table and observe condition of LEDs. 6. Disconnect output from the LEDs and note down the corresponding multimeter voltage readings for various combinations of inputs. PRELAB QUESTIONS:. What is the difference between Flip-Flop & latch? 2. Give examples for synchronous & asynchronous inputs? 3. What are the applications of different Flip-Flops? 4. What is the advantage of Edge triggering over level triggering? 5. What is the relation between propagation delay & clock frequency of flip-flop? 6. What is race around in flip-flop & how to over come it? 7. Convert the J K Flip-Flop into D flip-flop and T flip-flop? 8. List the functions of asynchronous inputs? 9. What are the functions of preset and clear pins? RESULT: Various flip flops were identified and verified their truth tables. DEPARTMENT OF ECE, VKCET Page 49

7 EXPERIMENT NO: 8 DESIGN AND IMPLEMENTATION OF CODE CONVERTOR AIM: To design and implement 4-bit (i) (ii) Binary to gray code converter Gray to binary code converter APPARATUS REQUIRED: IC TRAINER KIT, IC 7486, IC 748, IC 7432, IC 744 THEORY: The availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code. The bit combination assigned to binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B, B and the output variables are designated as C3, C2, C, Co. from the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as specified by code and the output lines generate the corresponding bit combination of code. Each one of the four DEPARTMENT OF ECE, VKCET Page 5

8 DEPARTMENT OF ECE, VKCET Page 5 BINARY TO GRAY CODE CONVERTOR TRUTH TABLE: K-Map for G : K-Map for G 2 : K-Map for G 3 : G 3 = B 3 K-Map for G : LOGIC DIAGRAM: B3 B2 B B G3 G2 G G

9 maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is C+D has been used to implement partially each of three outputs. PROCEDURE:. Place the IC on IC Trainer Kit. 2. Connect VCC and ground to respective pins of IC Trainer Kit. 3. Connect the inputs to the input switches provided in the IC Trainer Kit. 4. Connect the outputs to the switches of O/P LEDs 5. Apply various combinations of inputs according to the truth table and observe condition of LEDs. 6. Disconnect output from the LEDs and note down the corresponding multimeter voltage readings for various combinations of inputs. RESULT: Code converters were designed, assembled and verified the truth tables DEPARTMENT OF ECE, VKCET Page 52

10 DEPARTMENT OF ECE, VKCET Page 53 GRAY CODE TO BINARY CONVERTOR TRUTH TABLE: K-Map for B 3 : B3 = G3 K-Map for B 2 : K-Map for B : K-Map for B : LOGIC DIAGRAM G3 G2 G G B3 B2 B B

11 DEPARTMENT OF ECE, VKCET Page 54

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