Small-Signal Analysis of CMOS Two-Stage Op Amp

Transcription

1 Small-Signal Analysis of CMOS Two-Stage Op Amp Cascade two-port models of differential ampliþer with current-mirror supply (input stage) and common-source ampliþer with current supply (second gain stage) v i v d G m1 v d R out1 v i2 G m2 v i2 R out v o v i First stage: polarity of G m1 is inverted to reßect reversal of input terminals... which is done to make the overall gain positive for v d > 0 G m1 = g m1 R out1 = r o2 r o4 Second stage: G m2 = g m5 R out = r o5 r o6 a vdo = ( ÐG m1 R out1 )( ÐG m2 R out ) a vdo = g m1 ( r o2 r o4 )g m5 ( r o5 r o6 )

2 Two-Stage CMOS Design Example Design constraints Typical situation for an internal op amp: area and power are both limited. SimpliÞed area constraint -- set W max = 150 µm (for minimize channel-length modulation, set L min = 3 µm) Set DC power budget at 1.25 mw (including reference current) for case where we have symmetrical supplies: V = 2.5 V and V - = V. Initial Transistor Sizing: Make (W/L) 1 = (150 µm / 3 µm) in order to maximize G m1 and maximize common-mode input voltage range DC currents: assume I REF = 50 µa Set DC bias current of differential ampliþer = DC bias of common-source stage = 100 µa each as a Þrst-cut --> total current drawn is 250 µa --> power spec. is just met Transistor dimensions: (W/L) 5 = (150 µm / 3 µm) to maximize g m5 ( W L) 5 Ð I D µa = = = 1 2( W L) 34, I D µa Therefore (W/L) 3,4 = (W/L) 5 /2 = 25 --> W 3,4 = 75 µm since we use L min to save area. For symmetrical output swing, we set (W/L) 6 = (W/L) 5 = (150 µm / 3 µm) To maximize common-mode input range, we also set (W/L) 7 = (150 µm / 3 µm)

3 First-Cut CMOS Two-Stage Op Amp 2.5 V M 8 (75/3) 1 M 7 (150/3) M 6 (150/3) 2 50 µa _ C v I v L (150/3) (150/3) I M 3 (75/3) M 1 3 M 2 M 4 (75/3) 4 C c M 5 (150/3) v O 2.5 V µa µ n C ox = 50 V 2 V TOn = 1.0 V γ n = 0.6 V 1/2 t ox = 15 nm 0.1(µm/V) λ n = L 2φ p = 0.8 V n-channel MOSFET C ov = 0.5 ff/µm C jno = 0.1 ff/µm 2 C jswno = 0.5 ff/µm φ Bn = 0.95 V m jn = 0.5 m jswn = 0.33 µa µ p C ox = 25 V 2 V TOp = 1.0 V γ p = 0.6 V 1/2 t ox = 15 nm 0.1(µm/V) λ p = L 2φ n = 0.8 V p-channel MOSFET C ov = 0.5 ff/µm C jpo = 0.3 ff/µm 2 C jswpo = 0.35 ff/µm φ Bp = 0.95 V m jp = 0.5 m jswp = 0.33

4 DC Bias Solution Assume that the DC input voltages are V I = V I- = 0 V and V O = 0 V Input common-mode voltage range V IC,max = 2.5 V Ð ( Ð1 V) Ð 1.28 V Ð 1.4 V = 0.82 V V IC,min = Ð 2.5 V 1.28 V ( Ð1 V) = Ð2.22 V room for improvement in the upper limit -- possible at the expense of increased area (W/L) ratios must be increased. Output voltage swing V O,max = 2.5 V Ð 0.4 V = 2.1 V V O,min = Ð 2.5 V 0.28 V = Ð2.22 V output range in nearly symmetrical and adequate

5 Small-Signal Performance Small-signal parameters: g m1 = g m2 = 357 µs g m5 = 2 g m1 = 714 µs r o2 = r o4 = 600 kω r o5 = r o6 = 300 kω Differential voltage gain: 4 a vdo = ( 0.357) ( ) ( 714) ( ) = in decibels, a vdo db = 81 db.

6 Stability -- A Brief Introduction Non-inverting, unity gain conþguration v s (t) _ Op Amp v o (t) _ v s (t) = v s sin(ω s t) Feedback is to negative terminal of op amp, which tends to stabilize the output voltage v o (t) to be nearly equal to v s (t) What happens when the phase of a vd (jω s ) = 180 o?... the sign of a vd is ßipped! Consider and - terminals to be reversed!... if a vd (jω s ) > 1, then the output is destabilized if the input is perturbed.

7 Ensuring Stability If the gain of the op amp is less than 1 (in magnitude) when the phase is 180 o, then the unity-gain non-inverting configuation (worst-case) will be stable One solution: locate the second pole of the op amp ω 2 at approximately the unity gain frequency ω 2 a vdo ω 1 The second gain stage is responsible for both poles C' c I s V i2 G m2 V i2 C' L V o C 1 R 1 R out Device capacitances are lumped together in the circuit: C 1 = C gs5 C gd4 C db4 C gd2 C db2 C L = C L C db5 C db6 C gd6 C c = C c C gd5 The compensation capacitor C c sets the dominant pole ω 1 by the Miller effect: where R 1 = R out1 Ð1 ω 1 R 1 C 1 R 1 ( 1 G m2 R out )C c

8 Second Pole Location Direct factoring of transfer function --> ÒexactÓ expression for ω 2 For the case when C 1 Ç C c, C L ω 2 G m2 C L = ( 1 G m2 )C L Interpretation: At frequencies around ω 2 (>> ω 1 ), the impedance Z c = (1 / jω 2 C c ) is small enough that M 5 can be considered diode-connected Load capacitance sees a ThŽvenin resistance of 1 / g m5 --> ω 2 is set by the load capacitance in parallel with 1 / g m5 Adjusting compensation and load capacitors to satisfy ω 2 a vdo ω 1 G m 2 ( G m 1 R out1 )( G m2 R out ) ( G m 1 R out1 )( G m2 R out ) ω C L R 1 C 1 R 1 ( 1 G m2 R out )C c G m2 R 1 R C out c since G m2 R out >> 1 G m1 C c C L G m2

9 Capacitor Sizing The load capacitor is set by system speciþcations: C L = 7.5 pf with parasitic capacitances --> C L = C L 350 ff = 7.85 pf The compensation capacitor is approximately 357 µs C c CL = 3.9 pf 714 µs the ÒexactÓ result is signiþcantly higher... C c = 5.3 pf Area requirement with a 500 thick oxide is less than 100 x 100 µm 2 --> not a signiþcant addition to the op amp area Pole locations: ω 1 = 5.8 krad/s ω 2 = 67.2 Mrad/s SPICE: must increase C c to 20 pf in order to have ω 1 = 1.3 krad/s ω 2 = 10.4 Mrad/s ω 2 a vdo ω 1

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