USB 3.x Receiver Testing. Thorsten Götzelmann July 16 th 2014
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1 USB 3.x Receiver Testing Thorsten Götzelmann July 16 th 2014
2 When Separated, Agilent s EM Business will be named Page 2
3 Our Key Purpose Has Not Changed We believe in Firsts It s in our DNA. Bill Hewlett and Dave Packard shaped our purpose of believing in firsts 75 years ago. It launched Silicon Valley. We are committed to bring you a new generation of firsts unlocking insights for you so you can bring a new generation of technologies into the world. Agilent Technologies January
4 USB 3.x Receiver Testing Thorsten Götzelmann July 16 th 2014
5 Agenda Intro USB 2.0, 3.0 and 3.1 Overview RX Stress Signal Calibration RX Test Setup Data Encoding & Clock Compensation Loopback Training N5990A Test Automation SW Summary 5
6 Introduction Receiver Test Challenges Getting the stress signal calibration Dealing with asynchronous testing on the BERT error detector data encoding and filler primitive filtering Getting a device under test into a respective test mode 6
7 USB 2.0 vs. USB 3.x USB Mb/s NRZ half duplex 1 bi-directional link 4 signals (D+, D-, V BUS, GND) USB 3.x 5Gb/s / 10Gb/s 8B/10B coded / 128b/132b coded 2 uni-directional links 4 additional signals 7
8 USB 2.0 RX Testing Overview Performed at 480Mb/s +/- 500ppm Uses SEO_NAK test mode Checks sensitivity on minimum data eye threshold and squelch threshold Data rate variations Offset variations USB 2.0 test fixtures available from Agilent 8
9 Typical USB 3.0 Communication System Non- Super Speed TX RX Type-A Connector Type-B Connector TX RX Non- Super Speed Super Speed TX RX RX TX Super Speed USB 3.0 Host USB 3.0 Device USB 2.0 signals SuperSpeed signals D+ D- V BUS GND SSTX+ SSTX- SSRX+ SSRX- D+ D- V BUS GND SSRX+ SSRX- SSTX+ SSTX- 9
10 SuperSpeed Communication Physical Layer Focus Point to point communication, concurrent data flow Low power mode Link training Independent clock domains both using Spread Spectrum Clocking (SSC) Non- Super Speed TX RX TX RX Non- Super Speed Super Speed TX RX RX TX Super Speed -or- -or- Transmitter (TX) De-emphasis 8B/10B coding Data scrambling Insertion of Skip Cable / Channel Backward compatible EMI requirements Signal integrity requirements Receiver (RX) Channel equalization Clock recovery Re-timing (deletion or insertion of addition Skips) 10
11 USB C Connector Key Features: USB 2.0 (HS, FS, LS) USB 3.1 (5G, 10G) USB Power Delivery (up to 100W) Smaller size Reversible plug orientation and direction 11
12 USB 3.1 Gen 1 vs. Gen 2 Overview Gen 1 Gen 2 Data rate 5Gb/s ±300ppm (SSC variations not accounted for) 10Gb/s ±300ppm (SSC variations not accounted for) Coding 8b/10b scrambler: G(X) = X 16 + X 5 + X 4 + X scrambler reset by COM (K28.5) or BRST seed: FFFFh Symbol lock: K28.5, some implementations might be able to use K28.1or K b/132b scrambler: G(X) = X 23 + X 21 + X 16 + X 8 + X 5 + X scrambler reset by SYNC OS seed: 1D BFBCh Block alignment: SYNC OS + SDS OS and realignment through SKP OS SKP K28.1, K28.1 SKPOS with variable number of SKPs LFPS CDR PLL transfer: f 3dB = 10MHz peaking max = 2dB HPF transfer: f 3dB = 4.9MHz peaking 0dB damping factor = SSC Modulation rate: 30kHz to 33kHz Deviation: +0 to -4000(min)/-5000(max) Max slew rate: 10ms/s De-emphasis Post: -3dB Pre: 2.7dB Post: -3.3dB Device host capability negotiation is done during LFPS phase using LFPS modulation schemes PLL transfer: f 3dB = 15MHz peaking max = 2dB HPF transfer: f 3dB = 7.5MHz peaking 0dB damping factor = Modulation rate: 30kHz to 33kHz Deviation: +0 to -4000(min)/-5000(max) New df/dt requirement: 1250 (max) ppm/μs instead of max slew rate spec 12
13 LFPS SCD1 & SCD2 trepeat Modulation trepeat is modulated to express 0 (short) and 1 (long) SCD1.LFPS (4 b0100), and SCD2.LFPS (4 b1101) SuperSpeed+ identity check 13
14 LFPS LBPM Encoding Rate (speed and lane) announcement and negotiation Repeater declaration Power state transition in repeater Can be expanded to: VBus control on/off, overcurrent sensing Power delivery Vendor specific operation 14
15 USB 3.0 ECN 015 and ECN 018 ECN 015: Changed minimum SSC spread from -0.4% to -0.2% New SSC spec: +0% to min. -0.2% / max. -0.5% Compliance testing is done with 0.5% spread ECN 018: Allows a -0.2% offset on data rate to be more wireless friendly Limits SSC deviation for wireless friendly data rate New data rate and SSC spec for wireless friendly use case: Data rate is 5Gb/s -0.2% 4.99Gb/s +/- 300ppm SSC for 4.99Gb/s is +0% to min -0.2% / max. -0.3% 15
16 Normative Receiver Tolerance Compliance Test Requirements According to the Standard USB 3.0 Test setup and calibration point *): Test equipment Setup Calibration Point emulated with J-BERT Interference Channel Test cases *): Stressed Signal Generator Test RJ (rms) RJ (p-p) ber 10^- 12 SSC SJ Frequency SJ V_full_swing de-emphasis mui 0.17 UI on 500 khz 2 UI 750 mv p-p -3 db mui 0.17 UI on 1 MHz 1 UI 750 mv p-p -3 db mui 0.17 UI on 2 MHz 0.5 UI 750 mv p-p -3 db mui 0.17 UI on 4.9 MHz 0.2 UI 750 mv p-p -3 db mui 0.17 UI on 50 MHz 0.2 UI 750 mv p-p -3 db *) Taken from Universal Serial Bus 3.0 Specification, calibration setup: figure 6-18, input jitter requirements: table
17 Total Jitter [UI] More SJ Frequencies to Ensure Compliance USB 3.0 Critical receiver SJ problem area between 8MHz and 30MHz Additional test point recommendation: 10 MHz (f_3db_pll) 20 MHz (identified as critical frequency) 33 MHz (frequency typically present in hosts) Jitter Tolerance Example Measured at USB-IF Workshop #69, 9/15~9/ USB SuperSpeed Device low freq. PLL LBW & peaking high freq Sinusoidal Jitter Frequency [MHz] Max Passed Jitter Min Spec Test RJ (rms) RJ (p-p) ber 10^- 12 SSC SJ Frequency SJ V_full_swing de-emphasis mui 0.17 UI on 10 MHz 0.2 UI 750 mv p-p -3 db mui 0.17 UI on 20 MHz 0.2 UI 750 mv p-p -3 db mui 0.17 UI on 33 MHz 0.2 UI 750 mv p-p -3 db 17
18 Random Jitter (RJ) Requirement RJ occurs in the transmitter and is caused by thermal and noise effects. These effects are statistical by nature, so RJ is typically unbounded Generally test instruments can be classified by Crest factor important to use the right tool to reach a sufficient distribution Crest factor of 7 needed for SuperSpeed (BER of ) Noise generated by digital noise generators and arbitrary waveform generators is bounded by design. Some can be adjusted to the desired Crest factor (e.g. Agilent 81150A) Different Crest Factors BER And The Crest Factor BER unbounded bounded s CF=5 CF=7 18
19 Compliance Channels Compliance Channels are used to test TX and RX for worst case channel conditions Standard connector: Channel loss will dominate 11 PCB trace for device testing 5 PCB trace for host testing 3 meter USB 3.0 cable Micro connector: Channel loss will dominate 11 PCB trace for device testing 5 PCB trace for host testing 1 meter USB 3.0 cable Tethered: Channel loss will dominate 11 PCB trace for device testing 5 PCB trace for host testing short USB 3.0 cable Short Channel = no cable and shortest possible PCB traces 19
20 SuperSpeed Host Receiver Test Calibration and compliance channel Device 5 of trace 3 meter USB 3.0 cable Host Channel setup 20
21 SuperSpeed Device Receiver Test Calibration and compliance channel Host 11 of trace 3 meter USB 3.0 cable Device Channel setup 21
22 Why is Spread Spectrum Clocking Included in Receiver Compliance Test? SSC stresses clock data recovery and elastic buffer, required for compliance test Max. SSC deviation is 5000ppm, modulation rate between 30kHz and 33kHz Nominal data rate: 5Gb/s Frequency down spread: 5000ppm i.e Gb/s TX Non-SS SuperSpeed RX RX 1 2 loopback TX -or- error count read 1 2 ss kk p p ssss kkkk p p p p s s k k p p ss kk p p ssss kkkk p p p p s k p s k p Original un-modulated data at 5Gb/s Data with SSC at receiver (RX) pins Receiver (RX) elastic buffer compensates for clock difference 22
23 J-BERT SSC Setup and Capabilities Data rate and spread direction 4 2. Deviation 3. Modulation Frequency 4. Arbitrary modulation profiles or standard triangular. Arbitrary profiles can be used to emulate real world SSC profiles 23
24 USB 3.0 RX Jitter Tolerance Calibration De-Emphasis Calibration Stressed signal generator + DC-blocks connected to scope Eye diagram Either cursor based or histogram based measurement RJ Cal Through fixtures and 3m cable SIGTEST based measurement SJ Cal Through fixtures and 3m cable SIGTEST based measurement Two step approach via TJ SJ = TJ - TJ base Eye Height Calibration Through fixtures and 3m cable SIGTEST based measurement TJ Verification Through fixtures and 3m cable SIGTEST based measurement 24
25 USB 3.0 RX Jitter Tolerance Calibration Parameter Min Max Unit Pattern SigTest Technology Template De-Emphasis -3 db CP0 N/A N/A RJ (Random Jitter) ps RMS CP1 USB_3_5gb USB_3_5gb_CP1 SJ (Sinusoidal Jitter) ber UI 500kHz 1UI +0/-10%@ 1MHz 0.5UI 2MHz 0.2UI 4.9MHz 0.2UI 10MHZ 0.2UI 20MHZ 0.2UI 33MHZ 0.2UI 50MHz ps CP0 USB_3_5gb USB_3_5gb_CP0_RjIN_SjCal Eye Height Device: 145 Device: 150 mv CP0 USB_3_5gb USB_3_5gb_CP0_RjIN Host: 180 Host: 185 TJ (Total Jitter) ber ps CP0 USB_3_5gb USB_3_5gb_CP0_RjIN_SjCal DUT is retrained for each SJ test point Each SJ test point is tested to 1 error max in compared bits 25
26 Agilent J-BERT GUI Jitter Setup for USB
27 USB 3.0 RX Jitter Tolerance Calibration De-Emphasis Cal De-emphasis is defined as 20log 10 [(non-transition amplitude) / (transition amplitude)] This calibration is done at the end of the SMA to SMA cables feeding the signal into the Device Test Fixture 2 or Host Test Fixture 2 Use CP0 as test pattern Measurement is done on differential signal No embedded channels Calibration is done for -3dB de-emphasis The target peak to peak amplitude is 750mV differential The target accuracy is +/- 0.2dB SSC off Either a histogram based method for transition bit or non-transition bits or cursor based method to measure the different amplitudes can be applied. Do not use the scope built-in pp measurements. Use educated averaging for cursor based measurements. 27
28 USB 3.0 RX Jitter Tolerance Device Cal Setup DSA RT-Scope Stressed Signal Generator 11742A DC Block 11742A DC Block 28
29 USB 3.0 RX Jitter Tolerance Host Cal Setup DSA RT-Scope Stressed Signal Generator 11742A DC Block 11742A DC Block 29
30 USB 3.0 RX Jitter Tolerance Calibration RJ Cal This calibration is done through the fixtures and 3m USB 3.0 cable. A short USB 3.0 cable is used to connect to the Agilent USB 3.0 fixture or the USB-IF calibration fixture: Device Cal Fixture in case of a device calibration Device Test Fixture 1 in case of a host calibration The pattern used is CP1 which is clk/2 (1010) SIGTEST is used to measure RJ Target value is 2.178ps (10.8mUI) rms to 2.42ps (12.1mUI) rms SSC off Scope setup: Use Differential measurement on the scope Set to 40GSa/s Deactivate Sin(x)/x Interpolation Deactivate averaging Set memory depth to manual 8Mpts Set SIGTEST to Technology: USB_3_5gb Template file: USB_3_5gb_CP1 30
31 USB 3.0 RX Jitter Tolerance Calibration SJ Cal This calibration is done through the fixtures and 3m USB 3.0 cable. A short USB 3.0 cable is used to connect to the Agilent USB 3.0 fixture or the USB-IF calibration fixture: Device Cal Fixture in case of a device calibration Device Test Fixture 1 in case of a host calibration The pattern used is CP0 SIGTEST is used to measure SJ in a two step approach. [Max peak peak jitter for SJ freq ]-[Max peak peak jitter for SJ = 0UI] SSC off RJ from RJ cal is entered in SIGTEST SJ targets: 2UI 500kHz 1UI +0/-10%@ 1MHz 0.5UI 2MHz 0.2UI 4.9MHz 0.2UI 10MHZ 0.2UI 20MHZ 0.2UI 33MHZ 0.2UI 50MHz Scope setup similar to RJ cal Set SIGTEST to Technology: USB_3_5gb Template file: USB_3_5gb_CP0_RjIN_SjCal 31
32 USB 3.0 RX Jitter Tolerance Calibration EH Cal This calibration is done through the fixtures and 3m USB 3.0 cable. A short USB 3.0 cable is used to connect to the Agilent USB 3.0 fixture or the USB-IF calibration fixture: Device Cal Fixture in case of a device calibration Device Test Fixture 1 in case of a host calibration The pattern used is CP0 SIGTEST is used to measure EH (eye height) Full stress applied RJ SJ@50MHz SSC on RJ from RJ cal is entered in SIGTEST Target EH: Device: 145mV to 150mV Host: 180mV to 185mV Scope setup similar to RJ cal Set SIGTEST to Technology: USB_3_5gb Template file: USB_3_5gb_CP0_RjIN 32
33 USB 3.0 RX Jitter Tolerance Calibration TJ Verification This calibration is done through the fixtures and 3m USB 3.0 cable. A short USB 3.0 cable is used to connect to the Agilent USB 3.0 fixture or the USB-IF calibration fixture: Device Cal Fixture in case of a device calibration Device Test Fixture 1 in case of a host calibration The pattern used is CP0 SIGTEST is used to measure TJ Stressed eye applied except for SSC TJ is verified for all jitter frequencies above 2MHz Set SIGTEST to Technology: USB_3_5gb Template file: USB_3_5gb_CP0_RjIN_SjCal 33
34 Jitter Tolerance Stress Components Base Spec Gen1 5G Gen2 10G TJ after RX EQ 450mUI 394mUI RJ rms / RJ pp ber=1e mUI / 177.9mUI 13.08mUI / 192.3mUI SJ out of CDR tracking range 200mUI 170mUI Channel 20.6dB 5GHz M8048A 24.4 trace ~18dB@5GHz leaves -2.6dB for test board / fixture and cables or trace ~20.5dB loss 34
35 Jitter Tolerance Settings Base Spec Center Data Rate with SSC: 9.975Gb/s SSC: Center Spread 33kHz with 0.25% Voltage TP1: 800mV TP1: 2.7dB -3.3dB RJ: 1.308ps RMS channel 5GHz Center Data Rate with SSC: Gb/s SSC: Center Spread 33kHz with 0.25% Voltage TP1: 750mV -3.0dB RJ: 2.42ps RMS 35
36 USB 3.1 RX Jitter Tolerance Compliance Testing Outlook Like the calibration for USB 3.0 the calibration for USB 3.1 will most likely be done using SIGTEST measurements at the end of the test channel Pre-calibration for pre-shoot and de-emphasis, RJ, SJ most likely will use similar approach Problematic for USB 3.0 RX testing are variances in the channel loss. Rather than increasing RJ for instance it is possible that a calibration element to control this loss will be added A calibration which measures eye height (EH) and eye width (EW) using SIGTEST and adjust EH and EW by tuning stress parameters is likely 36
37 SS Test Adapter USB 3.0 Receiver Test Setup N4916B J-BERT N4903B J-BERT clock ouput used to add offset to DUT signal to adjust levels for pattern generator trigger input Sequence trigger BIAS-T ~1.8V offset voltage 50Ω 50Ω N4916B Channel integrated in USB-IF test fixtures 11742A DC Block 11742A DC Block Stress signal + RX - DUT 50Ω Loopback signal for SER analysis with J-BERT analyzer - TX + Key capabilities: Analysis of coded & retimed data with SER/FER analysis (option A02) Simplified loopback training with pattern sequencer with 120 blocks, pre- defined USB pattern sequences for host and device Generates calibrated stress conditions for RX test (SSC, SJ, RJ, De-emphasis, ISI) N4903B with C07 or C13, J10, J11, A02 N4916B, N4915A
38 SS Test Adapter USB 3.0 Receiver Test Setup Channel Add J-BERT N4903B J-BERT clock ouput used to add offset to DUT signal to adjust levels for pattern generator trigger input Sequence trigger BIAS-T ~1.8V offset voltage Stress signal 50Ω 50Ω 11636C 11636C 11742A DC Block 11742A DC Block Loopback signal for SER analysis with J-BERT analyzer Channel integrated in USB-IF test fixtures + RX - - TX + DUT Key capabilities: Analysis of coded & retimed data with SER/FER analysis (option A02) Simplified loopback training with pattern sequencer with 120 blocks, pre- defined USB pattern sequences for host and device Generates calibrated stress conditions for RX test (SSC, SJ, RJ, De-emphasis, ISI) Emulate LFPS 3-level signals with second output channel (option 002) for LFPS tests N4903B with C07 or C13, J10, J11, A02, 002 2x 11636C, 2x N4915A
39 USB 3.0 Receiver Test Setup M8020A Key capabilities: Analysis of coded & retimed data with SER/FER analysis (option 0S2) Simplified loopback training with pattern sequencer and 8b/10b pattern mode supporting 8b/10b HW coding and decoding as well as HW scrambling Generates calibrated stress conditions for RX test (SSC, SJ, RJ, De-emphasis, ISI) Emulate LFPS 3-level signals with built-in electrical idle for loopback training and via channel add of second output channel (option 0G2) for fast transition into and outof electrical idle for LFPS tests M8020A with M8041A-C16, -0S2, -0G3, - 0G4, (-0G2), M8070A-0TP and M8020A- BU2 39
40 USB 3.1 gen2 10G Instrument Setup for RX Testing Expected RX Test Setup Without Accessories for J-BERT N4903B: J-BERT N4903B with following options: C G BERT Jitter Options: J10, J11, J20 jitter options J12 JTOL compliance option recommended Error Detector Options: A02 8b/10b SER/FER for 5Gb/s A03 New SW option for 128b/132b SKPOS filtering for 10G/s. A01 Bit Recovery Mode for debugging recommended N4916B De-Emphasis Signal Converter: STD 4-tap de-emphasis N4915A-010 connection cable kit Possible Extensions: Expected RX Test Setup Without Accessories for J-BERT M8020A: J-BERT M8020A with following options: M8041A-C16 BERT 16G M8041A-0S2 SKP and SKP OS filtering M8041A-0G3 Jitter Sources M8041A-0G4 Multi-Tap De-Emphasis M8020A-BU2 5-slot AXIe chassis with USB M8070A-0TP System Software for M8020A Control PC, e.g. a laptop with Win7 / Win8 and 8G RAM or AXIe control PC module Possible Extensions: M8041A-0G2 Second PG option useful for external channel add for faster more controllable electrical idle during LFPS and LFPS testing N4877A CDR useful for increased CDR loop bandwidth A second N4916B + N4903B-002 option useful for external channel add for faster more controllable electrical idle during LFPS and LFPS testing 40
41 USB 3.x 5Gb/s 8b/10b Coding 8b/10b coding after scrambling Same scrambler polynomial as PCIE 2.5G & 5G: G(X) = X 16 + X 5 + X 4 + X Command block scrambler rules SKP symbols bypass and do not advance the scrambler K symbols are not scrambled but advance scrambler except for the SKP symbol D symbols advance scrambler and are scrambled except D symbols within a Training Sequence Ordered Set K28.5 (comma) resets scrambler K28.5(comma), K28.7 and K28.1 (SKP) can be used to gain symbol lock A symbol is always 10 bit long after coding 41
42 Possible Effects Due to Bit Errors A symbol may turn into a different symbol A symbol may turn into an illegal 10 bit string Some standards substitute illegal 10 bit codes (e.g. USB 3.0 uses K28.4) Also sometimes implementation specific The error could flip the running disparity All subsequent data could be coded with the new running disparity The error could violate the running disparity rules For the target BER of most standards a meaningful measure is to count one error only for all of above cases 42
43 Illustration Of A Disparity Flip Caused By A Bit Error A single bit error at the receiver will cause the DUT to receive a different symbol and may change the running disparity when being in loopback Only a BERT which understands 8B/10B encoded symbols will show the correct error count. A traditional BERT would show too many errors. The screen shot shows a repeated D12.0, D11.4 pattern received/looped by a SATA drive. A bit error in a D11.4 results in a D11.3 and flips the running disparity 43
44 128b/132b Coding 4 bit header to avoid link reset problems from PCIe 8G 0011 marks a data block and 1100 a command block SYNC block is used to reset scrambler and to gain block alignment Same scrambler polynomial as PCIe 8G: G(X) = X 23 + X 21 + X 16 + X 8 + X 5 + X Block header bypasses scrambler and does not advance scrambler Command block scrambler rules TS1, TS2, TSEQ symbol 0 bypasses but advances scrambler symbols 1 to 13 are scrambled symbols 14 and 15 bypass scrambler but advance scrambler if used for DC balance. Otherwise they are scrambled SKP OS bypasses scrambler and does not advance scrambler SDS OS bypasses scrambler but advance scrambler All blocks are 132 bit long except SKP OS which can be shorter or longer SKP END symbol is used to regain block alignment 44
45 128b/132b Coding SYNC / Data Block / SKP OS SYNC Data SKP OS
46 Encoding Summary 8b/10b Coding 8 bit data is encoded into 10 bit symbols There are a lot of combinations of 10 bits which aren t a valid 10B symbol. USB 3.0 substitutes illegal symbols by K28.4 For many 8 symbols exist two valid 10b symbols. Correct 10b code is chosen on the running disparity. Only comma characters (K28.1, K28.5, K28.7) can be used to gain symbol. Challenges for error detection: Single bit error can cause disparity changes, illegal symbol substitution as well as change the symbol entirely which can lead to false error counts when bits are compared in the 10b domain symbol comparison in the 8b domain is required Check for additional information on 8B/10B encoding 128b/132b Coding Sixteen 8bit symbols form a block which is preceded by a 4 bit header No coding of the block payload. 128b/132b relies on scrambler to ensure sufficient transition density for CDR Challenges for error detection: Variable length of SKP OS destroys 132bit block granularity which makes filtering of SKP OS more difficult compared to 8b/10b SKPs. 46
47 Independent Clock Domains And Clock Compensation In many standards there is no common clock. Therefore in a communication system each product has its own oscillator Typical host/device configuration in USB 3.0, SATA, SAS, etc: Clock A Device function Loopback Elastic buffer Transmitter Receiver CDR FF EQ Channel EQ FF CDR Receiver Transmitter Elastic buffer Loopback Device function Clock B Host Device Clock A and clock B will never be identical, often SSC is used The elastic buffer compensates the slight differences in data rate (i.e. performs re-timing): 47
48 Handling of Filler Primitives Clock Compensation Filler primitives are symbols in the data stream that carry no information original data and filler symbols sent with f A Retimed data with f B < f A data-symbol filler-primitive f B > f A Clock A Device function Loopback Elastic buffer Transmitter Receiver CDR FF EQ Channel EQ FF CDR Receiver Transmitter Elastic buffer Loopback Device function Clock B f B < f A f B > f A Host Device If clock B is running slower symbols from the incoming data must be dropped. Therefore the incoming data already contains filler primitives If clock B is faster filler primitives must be inserted to prevent the buffer from running empty 48
49 SKP USB 3.1 gen2 SKP OS: 2n *SKPs + SKPEND symbol + 3 symbols for LTSSM state; n = 0 to 18 SKP..CCh SKPEND..33h SKP OS in average every 22 blocks The variable length of SKP OS is challenging for BERT EDs The N4903B with option A03 (available now) and the M8020A with option 0S2 (SKP OS filtering for USB 3.1 will be added late summer 2014) can filter SKP OS for USB 3.1 with variable numbers of SKPs Remark: SKP OS rules might change to n *(4*SKPs) + SKPEND symbol + 3 symbols for LTSSM state; n = 1 to 9 This would ensure that every receiver in the link has at least 4 SKPs for clock compensation available 49
50 SKP OS USB 3.x gen1 SKP character: K28.1 Always in pairs: K28.1 K28.1 Pairs can be attached directly behind each other SKP SKP insertion every 384 dwords 50
51 Loopback 1 BERT and DUT run in separate clock domains DUT has to modify SK POS for clock compensation Test pattern is modified normal BER comparison does no longer work What to do? 51
52 Loopback 2 Modification is within SKPOS only BERT ED needs to filter SKP OS on expected as well as received pattern and compare remaining bits Available for 8b/10b USB 3.x 5G for J-BERT N4903B, option A02 and J-BERT M8020A, option M8041A-0S2, Available for 128b/132b USB G for J-BERT N4903B now, option A03, and will be available for J-BERT M8020A late summer 2014 as part of option 0S2 52
53 Repeater Re-Driver Re-Timer Host Host Side Re- Timer Re- Driver Re- Driver Re- Driver Re- Driver Active Cable Assembly Re- Timer Device Side Device A link can contain multiple repeaters Repeater devices can be of different types Re-timer Re-driver Repeaters are declared in LBPM A maximum of 10 elastic buffers could be involved in loopback more SKP OS required send SKP OS more frequently instead of 1 SKP OS every 22 blocks in presence of repeater devices, e.g. 1 SKP OS every 4 to 5 blocks 53
54 Clock Compensation Summarized Filler primitives are needed to compensate for differences in clock speed Filler primitives carry no information, they can be inserted or removed at any location without changing anything Usually standards have a minimum filler occurrence requirement (e.g. every 256 dwords in SATA, every 384 dwords in USB 3.0) this is based on clock stability spec, SSC clock deviation and min buffer size requirement 128b/130b PCIe and 128b/132b USB 3.1filler primitives, called SKP OS, are not necessarily removed entirely by a RX but their length can be altered which requires special SKP OS filtering Check your instrument before using it for receiver tests: Can it deal with fillers at arbitrary locations? Can it deal with filler primitives of variable length? modes for 128b/130b PCIe and 128b/132b USB
55 J-BERT Error Detection Modes Summarized Both J-BERT models, N4903B and M8020B, provide error detector options to deal with clock compensation and encoded data 8b/10b encoded data N4903B-A02 and M8020A-0S2: Filtering of filler primitives up to four symbols long and up to four primitives. In case of USB 3.x 5G filtering of SKP (K28.1) Expected and received data comparison in 8b domain disparity errors are not counted as symbol errors but are reported separately Symbol error counter, frame error counter, disparity error counter, illegal symbol counter as well as filler primitive ratio 128b/132b encoded data for USB 3.1 gen2 10G N4903B-A03 and M8020A- 0S2: Filtering of SKP OS with variable SKP counts Bit error counter 55
56 Typical USB 3.0 Link Turn-on Sequence LTSSM states: Host Power-up Rx. Detect. Reset Rx. Detect. Active Polling. LFPS Polling. RxEQ Polling. Active Polling. Configuration Polling. Idle Loopback warm reset de-assert termination detected LFPS handshake TSEQ transmitted TS1 received TS2 received if directed Device Compliance warm reset Rx. Detect. Reset Rx. Detect. Active Polling. LFPS Polling. RxEQ Polling. Active Polling. Configuration Polling. Idle Loopback multiple states Power-up J-BERT s sequence trigger can be used to trigger scope captures for each trainings step in combination with scope s protocol decode very helpful for debugging a trainings sequence 56
57 Loopback Training A trainings sequence generation tool is part of the N5990A Test Automation SW for USB 3.0 Easy manipulation of LFPS cycles TSEQ count TS1 count TS2 count Choice of: Power On sequence Warm Reset sequence 57
58 USB 3 Reciever Test Automation using N5990A automation sw Only with channel add setup 58
59 Receiver Characterization Example Automated instrument control for: Setup calibration Compliance test Characterization test Support for debugging Operator guidance Sophisticated test reports Controls J-BERT, Oscilloscope. Supports full product characterization including transmitter measurements 59
60 Same Setup Supports Multiple Standards J-BERT, oscilloscope and test automation software also cover PCI Express 1.1, 2.0, 3.0 SATA 1.5, 3, and 6Gb/s DisplayPort 1.1 Note: Additional applications may require additional instruments and accessories 60
61 Agilent U7243A USB 3.0 Compliance Test Software Automated Oscilloscope control for: Test Setup Transmitter test point Channel embedding CTLE Support for debugging Operator prompted test sequencing Standardized test reports Integrated USB 3.0 SigTest Compliance SW Advanced jitter analysis for design debug and verification using Agilent SDA SW 61
62 Summary Receiver Test Challenges Getting the stress signal calibration N5990A Test Automation Dealing with asynchronous testing on the BERT error detector SKP and SKP OS Filtering options for J-BERT N4903B A02 and A03 and for J-BERT M8020A 0S2 enable error counting for USB 3.x Getting a device under test into a respective test mode J-BERT s powerful pattern sequencer in combination with link training sequence generation capabilities integrated into the N5990A Test Automation SW 62
63 Thank You for Attending Questions? 63
64 Links USB Design & Test Information Resource Center: &pageMode=OVW&lc=eng&cc=US J-BERT M8020A: J-BERT N4903B: USB-IF: 64 Confidentiality Label
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