1 Using Atmel s ATAD00B Dual -bit Gsps ADC with Atmel s ATmegaL AVR Introduction With its "smart" feature (-wire serial interface), Atmel s ATAD00B dual -bit Gsps ADC provides you with digital control over the various functions offered with the dual ADC: calibration, gain and offset adjustments, DMUX ratio selection, analog and clock input mode, and partial or full standby mode. This digital control via the -wire serial interface can be managed using Atmel s ATmegaL AVR. The aim of this application note is to provide you with the relevant information for interfacing these two devices. ATAD00B and ATmegaL AVR Application Note A-BDC-0/0
2 Driving Atmel s ATAD00B ADC -wire Serial Interface with Atmel s ATmegaL AVR Atmel s ATmegaL AVR can be used to drive the -wire serial interface of the ATAD00B dual -bit Gsps ADC. This section provides a simple configuration for interfacing the AVR with the ADC. Note: All the information pertaining to the AVR contained in this document complies with the version available at the date the document was created. Before design, compliance of this information with the current version of the device should be verified. ATAD00B Dual -bit Gsps ADC -wire Serial Interface The ATmegaL AVR can drive four signals of the ATAD00B dual -bit Gsps ADC. These are: The MODE signal (pin of the -LQFP packaged device): used in the ADC to activate the -wire serial interface The CLK signal (pin of the -LQFP packaged device): input clock for the serial interface The DATA signal (pin of the -LQFP packaged device): input data for the serial interface The LDN signal (pin of the -LQFP packaged device): beginning and end of the register line for the serial interface The ADC s -wire serial interface only accepts.v CMOS digital signals while Atmel s ATmegaL must be supplied with V CC ranging from.v to V. Hence, it was necessary during the design to add a buffer and line driver with.v to tolerant I/Os used as translators in this mixed.v and environment. As the AVR can manage only four of the ADC s signals, a quad buffer is sufficient to translate the four signals from the AVR (WAKEUP, SPICLOCK, SPIDATA, SLE) to the MODE, CLK, DATA and LDN signals (.V) of the ADC. Possible devices enabling a translation between the of the AVR and the.v required by the ADC are the LCX and LCX low voltage quad buffer and line with V-tolerant I/Os or the LCX low voltage octal buffer and line with V-tolerant I/Os available from any digital buffer manufacturer. The LCX and LCX devices have the advantage of using only four inputs. Their main drawback, however, is that all four inputs cannot be connected to the same side of the device for a simplified layout. Figures to illustrate the possible application diagrams for the LCX, LCX and LCX low voltage buffers with V tolerant I/Os. ATAD00B and ATmegaL AVR
3 ATAD00B and ATmegaL AVR Figure. Application Diagram Using the LCX Buffer.V OE 0 00 nf SPICLOCK A 0 OE CLK O 0 A SPIDATA OE O DATA SLE A OE 0 LDN O A WAKEUP O MODE Table is the truth table of the LCX device. Table. LCX Truth Table Inputs Outputs OE n A n O n L L L L H H H Z Z Figure. Application Diagram Using the LCX Buffer.V.V OE 0 00 nf SPICLOCK A 0 OE CLK O 0 A SPIDATA OE O DATA SLE A OE 0 LDN O A WAKEUP O MODE
4 Table is the truth table of the LCX device. Table. LCX Truth Table Inputs Outputs OE n A n O n H L L H H H L Z Z Figure. Application Diagram Using the LCX Buffer.V OE 0 00 nf SPICLOCK I 0 OE O O 0 CLK SLE I I O O LDN SPIDATA I O I O DATA WAKEUP I I O O MODE 0 I Notes:. It is highly recommended the unused inputs of the octal buffer be connected to ground (directly to ground or via a 0Ω resistor in case future signal access is required) so that the buffers will never toggle and consequently dissipate power while they are not in use.. It may be useful to connect the OE signals to ground (LCX and LCX devices) or to.v (LCX) via a 0Ω resistor in case the application s signal level needs to be changed.. The WAKEUP signal is considered here as an input for both the LCX device and the AVR. When connected to.v, the ADC s serial interface becomes active. When connected to ground, the ADC s serial interface is disabled. In the case of a demonstrator design, the serial interface can be useful to connect the WAKEUP signal to a LED to indicate that the -wire serial interface has been activated (LED lit) and to a push button (between ground and ), as illustrated in Figure on page. ATAD00B and ATmegaL AVR
5 ATAD00B and ATmegaL AVR Table is the truth table of the LCX device. Table. LCX Truth Table Inputs Outputs (O 0, O, O, O ) OE I n L L L L H H H X Z Inputs Outputs (O, O, O, O ) I n L L L L H H H X Z
6 Figure. Global Schematic Using ATAD00B ADC with ATmega AVR and LCX Buffer A AREF PF0 PF PF PF PF PF PF PF PEN PE0 PE PE PE PE PE PB PB PB PB PB XTAL XTAL PD0 PD PD PD.. KΩ KΩ KΩ RX TX ATmegaL 0 KΩ 0 KΩ pf. MHz pf LCX.V SPICLOCK SLE SPIDATA WAKEUP 0 OE I 0 O I O I O I O OE O 0 I O I O I O I 0 00nF... Mode Clk ATAD00B Dual -bit Gsps ADC. 0 Data Ldn ATAD00B and ATmegaL AVR
7 ATAD00B and ATmegaL AVR Figure. Manual Management of the WAKEUP Signal (as in a Demonstrator Design, for example) WAKEUP To LCX Device 00Ω ATmegaL -bit Microcontroller In-System Programmable Flash On the AVR side, eight bi-directional I/O ports are provided but only four bits of one port are used for the interface between the LCX device and the AVR (for the WAKEUP, SPICLOCK, SPIDATA and SLE signals). Because Port B provides the pins for the SPI channel, this is the port chosen for the four previously-mentioned signals: SPICLOCK: PB (SCK = SPI bus serial clock) SPIDATA: PB (MOSI = SPI bus Master Output/Slave Input) SLE: PB (OC0 = Output Compare and PWM Output for Timer/Counter0) WAKEUP: PB (OCA = Output Compare and PWM Output A for Timer/Counter) The other pins PB0 (SS), PB (OCB) and PB (OC/OCC) can be left floating (open). Pin PB (MISO = SPI Bus Master Input/Slave Output) must be pulled up to via a KΩ resistor so as to be forced to a high level and not left open. Pins SPICLOCK = PB and SPIDATA = PB need to be pulled down to ground via a 0 KΩ resistor to be forced to a low level (inhibition of the SPI during reset of the microcontroller). Pin SLE = PB (OC0 = Output Compare and PWM Output for Timer/Counter0) must be pulled up to via a. KΩ (or KΩ if the power consumption is not critical) resistor in order to protect the line during reset of the microcontroller (during which phase the signal becomes an input). Ports A and C of the AVR can be left floating (open) but must be internally configured with pull-ups. For Port D, pins PD, PD, PD and PD can be left unused (open) but must be internally configured with pull-ups. Pins PD, PD, PD and PD0 have to be pulled up in order to inhibit the external interrupts. For port E, pins PE and PE can be left unused (open) but must be internally configured with pull-ups. Pins PE, PE, PE and PE must be pulled up to via a. KΩ (or KΩ if the power consumption is not critical) resistor in order to inhibit the external interrupts. PE and PE0 can be used as the Programming Data Output (TX) and Input (RX) to be connected to the TX and RX of the system (in the case of the ATAD00-EB evaluation board, these signals are sent to the PC via an RS- port).
8 All the Port F pins must be connected to ground so that they are in a known fixed state (no internal pull-down is available for these pins). All the Port G pins can be left floating (open). Finally, the five remaining signal pins are to be connected as follows: PEN: Programming Enable pin for the SPI serial programming mode, to be connected to V CC, set to, to activate the SPI programming mode : master reset of the AVR, to be connected to a microcontroller supervisory circuit (for example and for information only: MCP0 from Microchip one possible configuration is given in the next section) XTAL and XTAL: input and output to and from the inverting oscillator amplifier AREF: analog reference for the A/D internal converter Finally, V CC and AV CC must be connected to a source and must be connected to ground. This gives the configuration depicted in Figure on page (AVR only). Figure. ATmegaL Application Diagram (for Use with Atmel s ATAD00B Dual -bit Gsps ADC) KΩ KΩ KΩ A AREF PF0 PF PF PF PF PF PF PF RX TX SPICLOCK SPIDATA SLE WAKEUP PEN PE0 PE PE PE PE PE PB PB PB PB PB ATmegaL KΩ 0 KΩ XTAL XTAL PD0 PD PD PD pf. MHz pf Note: Only the connected pins are shown (the unused pins are left open). ATAD00B and ATmegaL AVR
9 ATAD00B and ATmegaL AVR Reset of the ATmegaL AVR can be controlled through a voltage supervisory circuit comparable to the MCP0 device from Microchip (for information only). Such a device allows you to keep the microcontroller in reset until the system voltage has reached its final level. It also ensures that the microcontroller is reset whenever a power drop occurs. Any voltage supervisory circuit compliant with V CC set to and with a reset pulse longer than a 0 ns width (minimum/active low) would work. In Figure on page, the reset voltage level of MicroChip s supervisory device is set to V with a pulse of 0 ms. Figure. Typical Application Diagram for the Circuit 00 nf MCP0 VDD ATmegaL VSS RST Programming Atmel s ATmegaL AVR Atmel s ATmegaL AVR can be programmed through the AVR ISP (In-System Programmer) tool using AVR Studio, Atmel's Integrated Development Environment (IDE) for code writing and debugging. The programming software can be controlled from both the Windows environment and a DOS command line interface. For more information on the AVR Studio programming software, please refer to Atmel s Web site at A - or 0-pin ISP connector is required to program the AVR. For this application, an HE0 -pin connector is used: pin : PDO, AVR Programming Data Out pin : AVR target application card power supply () pin : SCK, AVR programming clock pin : PDI, AVR programming Data In pin : RST_ISP, AVR programming reset pin : ground Notes:. The ISP card s power supply comes from the AVR card (). No additional power supply is required.. The AVR is programmed in serial mode. The RST_ISP signal is used to set the AVR to programming or SPI mode.
10 This signal is sent to the AVR s so that: When RST_ISP is set to 0, = 0 also and the AVR is in reset (ISP) mode, PE0 is used as the Data In for programming of the AVR, PE is the Data Out and PB is the programming clock When RST_ISP is set to, = also and the AVR is in normal mode, PE0 = RX, PE = TX and PB = SPICLOCK The three AVR signals mentioned previously (PE0, PE and PB) therefore have two functions, both of which are controlled by the RST_ISP signal. Caution should be taken when implementing these signals, series resistors on the SCK, PDO and PDI data may be needed to manage possible conflicts, please see below and Figure on page. Similarly, the signal has two possible sources: the signal generated by the microcontroller supervisory device, and the RST_ISP signal from the ISP To control this signal and in a case where the microcontroller supervisory device is not configured with an open collector (ex. MCP0 device), two head-to-tail diodes are required, as illustrated in Figure. The line going to the signal of the AVR is then in open-collector mode and a pull-up resistor (. KΩ) to is required. Figure. Typical Application Diagram for the Circuit with the ISP Connector 00 nf MCP0 VDD VSS RST. KΩ ATmegaL PDO SCK PDI RST_ISP 0 ATAD00B and ATmegaL AVR
11 ATAD00B and ATmegaL AVR A basic diagram illustrating the interface between the ISP connector and the AVR is depicted in Figure on page. In this general case, PE and PE0 interconnections are left to the user's responsibility. If these signals conflict (for example PE is driven by both PDO and another signal), it may be necessary to add a KΩ resistor in series so that any voltage difference is dissipated in this resistor. No additional protection is required on the AVR PB signal if there is no conflict between SCK and SPICLOCK. It is nevertheless recommended the ADC be set to standby mode or the -wire serial interface be disabled by using the MODE bit during programming of the AVR. Figure. General Application Diagram for the ISP Connector and the AVR 00 nf MCP0 VDD VSS RST. KΩ ATmegaL PB PE PE0 SPICLOCK K K Depends on the application PDO SCK PDI RST_ISP If the RX and TX signals are to be connected to a transceiver (RS- connector to a PC, for example), a low voltage buffer/line driver with a -state output device can be used to multiplex the AVR s signals (PE0, PE and PB) between the ISP and the RX signals and between the TX and SPICLOCK signals. The LVQ devices are wellsuited for this application (clock driver and bus-oriented transmitter or receiver).
12 The LVQ device has eight inputs and eight corresponding outputs and two -state output enable inputs. The latter (-state output enable inputs) can be managed by the RST_ISP signal: When RST_ISP is set to 0, OE and OE = 0 and O 0 to O are low and O to O are in high impedance When RST_ISP is set to, OE and OE = and O 0 to O are in high impedance and O to O are low Table is the truth table of the LVQ device: Table. LVQ Truth Table Inputs Outputs(O 0, O, O, O ) OE I n L L L L H H H X Z Inputs Outputs (O, O, O, O ) OE I n L X Z H L L H H H ATAD00B and ATmegaL AVR
13 ATAD00B and ATmegaL AVR Figure 0. Typical Application Diagram for the LVQ Device 00 nf MCP0 VDD VSS RST. KΩ ATmegaL PB PE PE0 PDO SCK PDI RST_ISP KΩ KΩ KΩ OE OE I0 I I I LVQ 0 O0 O O O 00 nf RX I I I I 0 O O O O TX Notes:. The unused inputs are connected to ground to prevent them from toggling.. OE and OE are connected together and to RST_ISP via a KΩ resistor.. SCK, RST-ISP and PDI are connected to I, OE and OE, and I 0 respectively via KΩ resistors in order to manage possible conflicts on the signals when the connector is used to program several AVRs.. PE0 is connected to both O 0 and O, which are respectively the inputs for SCK and RX. PE0 is generated by either SCK or RX, depending on the mode.. PE is connected to both I and I, which are the outputs for PDO and TX respectively. PE is generated by either PDO or TX, depending on the mode. Programming of the AVR itself as well as the connections of the RX and TX signals are not described in this application note as they depend on the final application. For further information on the ATAD00B dual -bit Gsps ADC, please contact the Broadband Data Conversion hotline at For more information on the AVR, please contact the AVR hotline at
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