Properties of Flip-Flops
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1 Dr. Anthony D. Johnson sl_dild.fm- Lab Assignment # Properties of Flip-Flops. Objective - gaining a close insight into the functioning and properties of basic static memory circuits, - verifying the superior performance of the edge triggered JK-flip-flop over other kinds of JK-flip-flops regarding the multiple toggling and s catching properties, - gaining insight into the static hazard property of some combinational logic circuits, - getting familiar with characteristic tables and characteristic functions of the D-type flip-flops, - getting familiar with state transition graphs of flip-flops, - getting familiar with characteristic tables and characteristic functions of the T-type flip-flops, - developing skills in the composition and testing of sequential logic circuits.. Prelab Assignment. Edge-triggered JK-flip-flop.. Using the present stable state variables J, K, and, and the next stable state variable +, prepare a characteristic table of the edge-triggered JK-flip-flop and show it as Table T.-... ompare the characteristic table T.- to the truth table T.- of the Lab Assignment #, and state their common features and their differences. ould the difference be attributed to the differing transparency properties of the edge-triggered JK-flip-flop and the level-controlled JK-flip-flop circuits?.. Using the prepared characteristic table T.- and the Karnaugh map minimization method, derive a minimized expression of the characteristic equation of the edge-triggered JK-flip-flop. Show the derived equation as equation (.-)...4 Based on the prepared characteristic table T.-, draw a graphical representation of the state transition graph (state diagram) of the edge-triggered JK-flip-flop, and show it as Figure.-... Prepare a computer generated drawing of the logic circuit of Figure A.- and show it as Figure.-(a). Hint# Note that the NOR and AND gates in Figure A.- create a combinational circuit with a static 0-hazard, which establishes conditions for the s catching to take place. To that effect, the static 0-hazard circuit will deliver a positive glitch to the input of the OR gate on every positive edge of the signal A ; the glitch will be transferred to J input of the JKflip-flop while B is at logical 0. The buffer-connected AND gate increases the time delay of the signal generated by the NOR gate to make the duration of the glitch longer.
2 Dr. Anthony D. Johnson sl_dild.fm- +V Function generator 4 A B R R V 74 A B D t A O 4 6 LR J LS76A K V PRE 4 0 Figure A.- A circuit for experimenting with the Edge-Triggered JK-flip-flop...6 Design a physical layout of the logic circuit shown as Figure.-(a). Prepare a computer generated drawing of the layout and show it as Figure.-(b). Provide the I package pinouts on both drawings of Figure Data sheets of the 74LS76A dual negative-edge-triggered JK-flip-flop are available for downloading from the course web site where they are posted as the file sdls.pdf. Hint#: Pinouts not shown in Figure A.- are available in Figure. of the course text book, p. 07-0, and in the TTL Data Book, a few copies of which are available in NE-06 Lab.. Negative Edge triggered D-flip-flop.. Using the present state variables D and, and the next state variable +, prepare a characteristic table of the D-flip-flop and show it as Table T.-... Using the prepared characteristic table T.- and the Karnaugh map minimization method, derive a minimized expression of the characteristic equation of the D-flip-flop and show it as equation (.-)... Based on the prepared characteristic table T.-, derive a graphical representation of the state transition graph (state diagram) of the edge-triggered D-flip-flop, and show it as Figure Design a logic circuit which implements a negative edge-triggered D-flip-flop by "gating" the D input to the inputs of a JK-flip-flop circuit. Show a graphical representation of the D-flip-flop circuit as Figure.-(a). Hint# onsider using an inverter... Using integrated circuit components listed in section., design a physical layout of the logic circuit shown in Figure.-(a). Show a computer generated drawing of the designed layout as Figure.-(b). Provide I package pinouts in all drawings of Figure.-. Hint#4 Pinouts are shown in Figure., pp.07-0 of the textbook, and in 74LS76A data sheets.
3 Dr. Anthony D. Johnson sl_dild.fm-. T-flip-flop.. Using the present state variables T and, and the next state variable +, prepare a characteristic table of the T-flip-flop and show it as Table T.-... Using the prepared characteristic table T.- and the Karnaugh map minimization method, derive a minimized expression of the characteristic equation of the T-flip-flop and show it as equation (.-)... Based on the prepared characteristic table T.-, derive a graphical representation of the state transition graph (state diagram) of the edge-triggered T-flip-flop, and show it as Figure Design a logic circuit which implements an edge-triggered T-flip-flop by "gating" the T input to the inputs of a JK-flip-flop circuit. Show a computer generated graphical representation of the T-flip-flop circuit as Figure.-(a). Hint# ompare the characteristic tables of the T-flip-flop and the JK-flip-flop to find out how to connect the T-input to inputs J and K... Design a physical layout of the logic circuit shown in Figure.-(a). Show a computer generated drawing of the designed layout as Figure.-(b). Provide I package pinouts in all drawings of Figure.-.. Lab equipment and circuit components. Equipment Equipment to be used includes: - Proto board: ETS-7000, - Mixed signal oscilloscope HP464D, - Dell GxaEM computer system.. Logic gate and circuit components - integrated circuit 740, quad -input NOR gates - integrated circuit 7404, hex inverters - integrated circuit 740, quad -input AND gates - integrated circuit 74, quad -input OR gates - integrated circuit 74LS76A, dual negative-edge triggered JK-flip-flop - integrated circuit 74, 4-bit ripple counter 4. Lab Experiments 4. Edge-Triggered JK-flip-flop Experiment 4.. Using the prepared physical layout of Figure.-(b), build on the protoboard the circuit shown in Figure A onnect the digital channels D0 through D7 of the Mixed signal oscilloscope HP 464D to
4 Dr. Anthony D. Johnson sl_dild.fm- 4 the circuit constructed under 4..: - digital channel D0: to the output of the function generator, - digital channel D: to the flip-flop input signal J, - digital channel D: to the flip-flop input signal K, - digital channel D: to the flip-flop clock signal, - digital channel D4: to the flip-flop output, - digital channel D: to the flip-flop output. - digital channel D6: to the output of the -input AND gate A O, - digital channel D7: to and to ripple counter s output A. Establish a ground connection. Turn on digital channels D0 through D7, and rename the channels D0 through D7 as A, J, K,,, B, AO, and A respectively. 4.. Adjust the frequency of the function generator to MHz. Set the triggering mode of the HP 464D to combination 00 on channels D through D. Hit the key Single on the HP 464D. Adjust the display of waveforms so that the first appearance of the combination of signal values 00 on channels D through D is positioned at the left end of the screen, and that the whole screen shows ten percent more than two periods of the clock signal Investigate the waveforms obtained under 4.., looking for the evidence of errors caused by the multiple toggling or s catching properties of some flip-flops. ould you observe occurrence of any of those? Based on your observations: Is the Edge-Triggered JK-flip-flop a reliable memory element? 4.. Save the Screen Image of the correct waveforms of the digital channels D0 through D6 to a file named sl_4.tif on the Dell GxaEM computer system. (Alternatively, use the Screen apture tool.) 4..6 reate the circuit of Figure A.4- by making necessary modifications to the circuit of Figure A.-. Leave the connections of the digital channels D0 through D of the HP 464D oscilloscope unchanged, and remove the connections to D6 and D7. Repeat the actions specified under Using the instructions from the BenchLink tutorial posted at the course webpage, transfer the Screen Image of the correct waveforms of the digital channels D0 through D6 to a file named sl_4.tif on the Dell GxaEM computer system. 4.. Observe the waveforms and compare them with those obtained in the circuit of Figure A.-. State the differences that you can observe. Explain what causes the differences. Hint#7 The ratio of the clock signal (control signal ) frequency to the frequencies of the input signals J and K is smaller than one in the circuit of Figure A.-, while it is greater than one in the circuit of Figure A.4-. onsider how this affects the selection of input signal combinations at which the triggering of the flip-flop takes place. 4. Edge-Triggered D-type flip-flop Experiment 4.. Using as a reference the prepared physical circuit diagram from Figure.-(b), build on the proto board an implementation of the circuit of Figure A.4-.
5 Dr. Anthony D. Johnson sl_dild.fm- +V V Function generator 4 A B R R 74 A B D V LR PRE J K 7476A 4 Figure A.4- A circuit for experimenting with the Edge-Triggered JK flip-flop. +V PRE LR FUNTION GENERATOR 4 V A 74 A B B R R D D 0 Figure A.4- ircuit for experimenting with the Edge-Triggered D-flip-flop. 4.. onnect the digital channels D0 through D4 of the Mixed signal oscilloscope HP 464D to the circuit shown in Figure A.4-: - digital channel D0: to the output of the function generator, - digital channel D: to the flip-flop input signal D, - digital channel D: to the flip-flop control signal (clock) input, - digital channel D: to the flip-flop output signal, - digital channel D4: to the flip-flop output signal B, Establish a ground connection. Turn on digital channels D0 through D4, and rename the channels D0 through D4 as A, D,, and B respectively. 4.. Adjust the frequency of the function generator to MHz. Set the triggering mode of the HP 464D to combination 00 on channels D and D. Hit the key Single on the HP 464D.
6 Dr. Anthony D. Johnson sl_dild.fm- 6 Adjust the display of waveforms so that the first appearance of the combination of signal values 00 on channels D through D is positioned at the left end of the screen, and that the whole screen shows ten percent more than two periods of the signal at the input D. ompare the obtained waveforms with the contents of Table T.-. In case of a discrepancy remove the cause and repeat the experiment Save the Screen Image of the correct waveforms of channels D0 through D4 to a file named sl_44.tif on the Dell GxaEM computer system. (Alternatively, use the Screen apture tool.) 4.. Disconnect the input from the output B of the 74 pulse source and connect it to the output A of the 74. Obtain a new set of waveforms in the same way as in Section 4... Observe the obtained waveforms. ompare the new set of waveforms with the one obtained in Section 4... Explain the cause of the difference in the time moment when the output of the D-flip-flop changes Hint#6 onsider the time delay of the signal at the input D with respect to the time of the negative edge of the signal at. Was it greater in the circuit of the experiment performed under 4.., or 4..? Zoom in at the moment of the negative edge of the clock signal and determine the actual timing sequences at D and. onsider the influence of the setup time of the flip-flop Using the instructions from the BenchLink tutorial posted at the course webpage, transfer the Screen Image of the correct waveforms of channels D0 through D4 to a file named sl_4.6.tif on the Dell GxaEM computer system. 4. Edge-Triggered T-flip-flop Experiment 4.. Using as a reference the prepared physical circuit diagram of Figure -(b), build on the protoboard the test circuit shown in Figure A.4-. +V FUNTION GENERATOR 4 A B R R V 74 A B D PRE T LR 0 Figure A.4- ircuit for experimenting with the Edge-Triggered T-flip-flop. 4.. onnect the logic channels D0 through D4 of the Mixed signal oscilloscope HP 464D to the circuit shown in Figure A.4-:
7 Dr. Anthony D. Johnson sl_dild.fm- 7 - digital channel D0: to the output of the function generator, - digital channel D: to the flip-flop input signal T, - digital channel D: to the flip-flop control signal, - digital channel D: to the flip-flop output signal, - digital channel D4: to the flip-flop output signal B, Establish a ground connection. Turn on digital channels D0 through D4, and rename the channels D0 through D4 as A, T,, and B respectively. 4.. Repeat the steps of Section 4... Investigate the obtained waveforms and compare them with the contents of Table T.-. In case of a discrepancy remove the cause and repeat the experiment Using the instructions from the BenchLink tutorial posted at the course webpage, transfer the Screen Image of the correct waveforms of channels D0 through D4 to a file named sl_44.tif on the Dell GxaEM computer system. 4.4 TRANSFER OF APTURED WAVEFORMS. Upload the files sl_*.tif from the Lab computer Dell GxaEM to the :\H-drive of your account in the UTAD file system using the instructions from the tutorial named uploading_to_h_drive.pdf posted at the course webpage.. LAB REPORT To be considered complete the lab report must contain the following,. over sheet - Lab style, filled out,. The truth tables prepared under. through... The characteristic functions of flip-flops derived under. through.. 4. The logic and physical circuit diagrams prepared under. through... The waveforms obtained in experiments 4. through Answers to all questions asked in conjunction with experiments 4. through A report on items not included under. and. above, but listed in the document Guidelines for Preparing Lab Reports that is posted at the course web page and which asks for: - a discussion of the insights gained through the conducted experiments, - textual description and graphical/ tabular illustration of the design procedure(s), - description of implemented testing procedures, - comments and suggestions that might lead to easier and/or deeper understanding of the topics covered by the assignment.
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