Miniature, 2W Isolated UNREGULATED DC/DC CONVERTERS
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1 Series For most current data sheet and other product information, visit Miniature, W Isolated UNREGULATED DC/DC CONVERTERS FEATURES UP TO 89% EFFICIEY THERMAL PROTECTION DEVICE-TO-DEVICE SYHRONIZATION SO-8 () POWER DENSITY OF 6W/in 3 (6.5W/cm 3 ) EN55 CLASS B EMC PERFORMAE UL95 RECOGNIZED JEDEC -PIN AND SO-8 () PACKAGES APPLICATIONS POINT-OF-USE POWER CONVERSION GROUND LOOP ELIMINATION DATA ACQUISITION INDUSTRIAL CONTROL AND INSTRUMENTATION TEST EQUIPMENT DESCRIPTION The series is a family of W, unregulated, isolated DC/DC converters. Requiring a minimum of external components and including on-chip device protection, the series provides extra features such as output disable and synchronization of switching frequencies. The use of a highly integrated package design results in highly reliable products with power densities of 79W/in 3 (4.8W/cm 3 ) for the -PDIP, and 6W/in 3 (6.5W/cm 3 ) for the SO-8 (). This combination of features and small size makes the suitable for a wide range of applications. NOTE: () SO-8 version available January,. 8kHz Oscillator Reset Power Stage V OUT SY/DISABLE Watch-dog/ start-up PSU Thermal Shutdown I BIAS Power Controller IC International Airport Industrial Park Mailing Address: PO Box, Tucson, AZ Street Address: 673 S. Tucson Blvd., Tucson, AZ 8576 Tel: (5) 746- Twx: Internet: Cable: BBRCORP Telex: FAX: (5) Immediate Product Info: (8) Burr-Brown Corporation PDS-558A Printed in U.S.A. December, 999
2 SPECIFICATIONS At T A = +5 C, unless otherwise specified. SERIES PARAMETER CONDITIONS MIN TYP MAX UNITS OUTPUT Power % Full Load W Ripple O/P Capacitor = µf, 5% Load mvp-p INPUT Voltage Range on % ISOLATION Voltage s Flash Test kvrms 6s Test, UL95 () kvrms LINE Regulation %/% of SWITCHING/SYHRONIZATION Oscillator Frequency (f OSC ) Switching Frequency = f OSC / 8 khz Sync Input Low.4 V Sync Input Current Y = +V 75 µa Disable Time µs Capacitance Loading on Sync Pin External pf RELIABILITY Demonstrated T A = +55 C 75 FITS THERMAL SHUTDOWN IC Temperature at Shutdown 5 C Shutdown Current 3 ma TEMPERATURE RANGE Operating C INPUT OUTPUT LOAD NO LOAD BARRIER VOLTAGE (V) VOLTAGE (V) REGULATION (%) CURRENT (ma) EFFICIEY (%) CAPACITAE (pf) V NOM I Q C ISO 75% LOAD () % TO % LOAD % LOAD % LOAD V ISO = 75 RMS PRODUCT MIN TYP MAX MIN TYP MAX TYP MAX TYP TYP TYP 53P (3), U (3) P, U (4) P, U (4) P, U (4) DP, U (4) ±.5 ±5 ± P, U (4) P DP.8 3. ±.4 ± ± P P DP ±4.75 ±5 ± DP ±.5 ±5 ± NOTES: () During UL95 recognition tests only. () % Load Current = W/V NOM TYP. (3) 53P and U models available January,. (4) SO-8 version available January,. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
3 PIN CONFIGURATION (Single-DIP) PIN CONFIGURATION (Dual-DIP) DIP DIP SY SY PIN DEFINITION (Single-DIP) PIN DEFINITION (Dual-DIP) Voltage Input Input Side Common 5 Output Side Common 6 +Voltage Out 7 Not Connected 8 Not Connected SY Synchronization Pin Voltage Input Input Side Common 5 Output Side Common 6 +Voltage Out 7 Voltage Out 8 Not Connected SY Synchronization Pin PIN CONFIGURATION (Single-SOIC) () PIN CONFIGURATION (Dual-SOIC) () SOIC SOIC 8 SY 8 SY PIN DEFINITION (Single-SOIC) () PIN DEFINITION (Dual-SOIC) () Voltage Input Input Side Common 3 Input Side Common Output Side Common 3 +Voltage Out Not Connected 5 Not Connected 6 Not Connected 7 Not Connected 6 Not Connected 7 Not Connected 8 SY Synchronization Pin Voltage Input Input Side Common 3 Input Side Common Output Side Common 3 +Voltage Out Voltage Out 5 Not Connected 6 Not Connected 7 Not Connected 6 Not Connected 7 Not Connected 8 SY Synchronization Pin NOTE: () SO-8 version available January,. 3
4 ABSOLUTE MAXIMUM RATINGS Input Voltage 5V Input Models... 7V V Input Models... 5V 5V Input Models... 8V 4V Input Models... 9V Storage Temperature... 6 C to +5 C Lead Temperature (soldering, s)... 7 C ORDERING INFORMATION Basic Model Number: W Product Voltage Input: 5V In Voltage Output: 5V Out Dual Output: Package Code: P = -Pin Plastic DIP U = 8-Lead SOIC () 5 5 (D ) ( ) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: () SO-8 version available Q. PACKAGE/ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER () MEDIA Single 53P () DIP- - 4 C to +85 C 53P 53P Rails 53U () SOIC C to +85 C 53U 53U/K Tape and Reels 55P DIP- - 4 C to +85 C 55P 55P Rails 55U () SOIC C to +85 C 55U 55U/K Tape and Reels 57P DIP- - 4 C to +85 C 57P 57P Rails 57U () SOIC C to +85 C 57U 57U/K Tape and Reels 59P DIP- - 4 C to +85 C 59P 59P Rails 59U () SOIC C to +85 C 59U 59U/K Tape and Reels 5P DIP- - 4 C to +85 C 5P 5P Rails 5U () SOIC C to +85 C 5U 5U/K Tape and Reels P DIP- - 4 C to +85 C P P Rails 55P DIP- - 4 C to +85 C 55P 55P Rails 45P DIP- - 4 C to +85 C 45P 45P Rails Dual 55DP DIP- - 4 C to +85 C 55DP 55DP Rails 55DU () SOIC C to +85 C 55DU 55DU/K Tape and Reels DP DIP- - 4 C to +85 C DP DP Rails 45DP DIP- - 4 C to +85 C 45DP 45DP Rails 45DP DIP- - 4 C to +85 C 45DP 45DP Rails NOTES: () Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /K indicates devices per reel). Ordering pieces of 53U/K will get a single -piece Tape and Reel. () Shaded models available January,. 4
5 TYPICAL PERFORMAE CURVES At T A = +5 C, unless otherwise noted. 6 55P CONDUCTED EMISSIONS (5mA Load) P V OUT vs TEMPERATURE (75% Load) Emission Level, Peak (dbµa) V OUT (V) Frequency (MHz) Temperature ( C) 5.4 5P V OUT vs LOAD.5 5P POWER OUT vs TEMPERATURE (4mA Load) 5.3. V OUT (V) P OUT (W) Load (%) Temperature ( C) Efficiency (%) EFFICIEY vs LOAD DCPDP DCP5P Ripple (mvp-p) P OUTPUT AC RIPPLE (MHz Band).µF 5 µf Load (%) Load Current (ma) 4 5
6 FUTIONAL DESCRIPTION OVERVIEW The offers up to W of unregulated output power from a 5V, V, 5V, or 4V input source with a typical efficiency of up to 89%. This is achieved through highly integrated packaging technology and the implementation of a custom power stage and control IC. The circuit design utilizes an advanced BiCMOS/DMOS process. POWER STAGE This uses a push-pull, center-tapped topology switching at 4kHz (divide by from 8kHz oscillator). OSCILLATOR AND WATCHDOG The onboard 8kHz oscillator generates the switching frequency via a divide by circuit. The oscillator can be synchronized to other circuits or an external source, and is used to minimize system noise. A watchdog circuit checks the operation of the oscillator circuit. The oscillator can be stopped by pulling the SY pin LOW. The output pins will be tri-stated. This will occur in µs. THERMAL SHUTDOWN The is protected by a thermal shutdown circuit. If the on-chip temperature exceeds 5 C, the device will shut down. Once the temperature falls below 5 C, normal operation will resume. SYHRONIZATION In the event that more than one DC/DC converter is needed onboard, beat frequencies and other electrical interference can be generated. This is due to the variation in switching frequencies between the DC/DC converters. The overcomes this by allowing devices to be synchronized to one another. Up to eight devices can be synchronized by connecting the SY pins together, taking care to minimize the capacitance of tracking. Significant stray capacitance (> pf) will have the effect of reducing the switching frequency, or even stopping the oscillator circuit. It is also recommended that power and ground lines are star connected. If synchronized devices are used, it should be noted that, at start up, all devices will draw maximum current simultaneously. This can cause the input voltage to dip and should it dip below the minimum input voltage (4.5V), the devices may not start up. A.µF capacitor should be connected close to the input pins. If more than eight devices are to be synchronized, it is recommended that the SY pins are driven by an external device. Details are contained in a separate applications bulletin (AB-53). CONSTRUCTION The s basic construction is the same as standard ICs. There is no substrate within the molded package. The is constructed using an IC, rectifier diodes, and a wound magnetic toroid on a leadframe. As there is no solder within the package, the does not require any special PCB assembly processing. This results in an isolated DC/DC converter with inherently high reliability. UPPLY V OUT SY V OUT + V OUT V OUT SY COM FIGURE. Connecting the in Series. 6
7 ADDITIONAL FUTIONS DISABLE/ENABLE The can be disabled or enabled by driving the SY pin using an open drain CMOS gate. If the SY pin is pulled low, the will be disabled. The disable time depends upon the external loading; the internal disable function is implemented in µs. Removal of the pull down will cause the to be enabled. Capacitive loading on the SY pin should be minimized in order to prevent a reduction in the oscillator frequency. DECOUPLING Ripple Reduction The high switching frequency of 4kHz allows simple filtering. To reduce ripple, it is recommended that a µf capacitor is used on V OUT. Dual outputs should both be decoupled to pin 5. A.µF capacitor on the input is recommended. Connecting the in Series Multiple isolated W DC/DC converters can be connected in series to provide nonstandard voltage rails. This is possible by utilizing the floating outputs provided by the s galvanic isolation. Connect the positive V OUT from one to the negative V OUT () of another (see Figure ). If the SY pins are tied together, the self-synchronization feature of the will prevent beat frequencies on the voltage rails. The SY feature of the allows easy series connection without external filtering, minimizing cost. The outputs on dual output versions can also be connected in series to provide two times the magnitude of V OUT as shown in Figure. For example, a dual 5V 45D could be connected to provide a 3 rail. Connecting the in Parallel If the output power from one is not sufficient, it is possible to parallel the outputs of multiple s, as shown in Figure 3. Again, the SY feature allows easy synchronization to prevent power-rail beat frequencies at no additional filtering cost. UPPLY COM FIGURE. Connecting Dual Outputs in Series. UPPLY V OUT SY x Power Out V OUT SY COM FIGURE 3. Connecting Multiple s in Parallel. 7
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