CIRCUITS LABORATORY EXPERIMENT 7


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1 CIRCUITS LABORATORY EXPERIMENT 7 Design of a Single Tansisto Amplifie 7. OBJECTIVES The objectives of this laboatoy ae to: (a) Gain expeience in the analysis and design of an elementay, single tansisto amplifie, (b) Build and thooughly test the amplifie, (c) Make a caeful compaison between the amplifie's design specifications and the expeimental measuements with coective action being taken fo any esults that do not agee with theoy. 7.2 INTRODUCTION The single tansisto amplifie is one of the majo keys to undestanding the analysis and design of all analog electonic systems. Steeos, television sets, adios, long distance telephone communication cicuits, and many othe pactical systems employ pinciples that we will exploe in this expeiment. An elementay common emitte (CE) tansisto amplifie will be designed fom pinciples eviewed hee. The amplifie will be constucted duing the laboatoy peiod and measuements caefully taken to veify that the design is coect and that all esults agee with theoetical pedictions. Extensive calculations must be made to insue that the amplifie data agees accuately with theoy befoe leaving the laboatoy. 7 
2 7.3. THEORY 7.3. THE BASIC CE EQUATIONS The common emitte (CE) emitte amplifie configuation will be employed in this expeiment. The basic CE cicuit is shown in Figue 7.. T 4 50Ω T Function Geneato Figue 7.. The Basic Common Emitte Amplifie Figue 7.2 below is the small signal, midfequency, incemental model coesponding to ou CE cicuit. Note that the midfequency model assumes that the B C oc v o R L Figue 7.2 Small signal midfequency model fo a CE amplifie E impedances due to C and C 2 ae negligible compaed to the impedance of elated components in the cicuit. Using the Voltage Amplifie model shown in Section 7.6., 72
3 the vaious elations shown in Table can be deived fom the cicuit of Figue 7.2. The "Remaks" column gives futhe insight elative to each equation. Table I. Fundamental Design Equations fo the Common Emitte Amplifie Quantity Equation Eq. No. Remaks Theoetical BJT T AC (7.) V T Themal Voltage, input esistance V (β ) π I π is in ohms. CQ Input esistance i π //R B (7.2) i π if R B >> π. (T to common) Output esistance o R C // oc (7.3) o R C if oc >>R C. (T 4 to common) No load incemental voc β ACo a (7.4) Deived fom Figue 7.2 with VO voltage gain v R L (Open Cicuit.) in π Collecto bias VCC VCEQ I (7.5) V CEQ v CE at tansisto Q pt. CQ Cuent R See Fig. 7.4 C Base bias esisto ( VCC on be DC (7.6) v be (on) 0.7 volt fo Silicon value R v ( ))( β ) B I BJT tansistos CQ Input coupling C /[ω i (R S + i )] (7.7) C /(ω i i ) if i >>R S capacito value ω i half powe fequency Output coupling C 2 /[ω o ( o + R L )] (7.8) C 2 /(ω o R L ) if R L >> o capacito value ω o half powe fequency Notes: (a) See Appendix 7.6. on page 77 fo a standad Voltage Amplifie model. (b) Equation (7.4) negative sign epesents invesion, i.e., a 80 phase shift. (c) Uppe case lettes epesent quiescent o DC values, e.g., V CEQ. (d) Lowe case lettes epesent incemental o AC values, e.g., v in and v o. (e) β DC Common emitte quiescent cuent gain I CQ / I BQ. (f) β AC Common emitte incemental cuent gain Δi C / Δi B fo V CEQ constant. (g) oc output esistance Δv CE /Δi C at constant I BQ. 73
4 This table contains many of the fundamental elations fo the design of the CE amplifie. Fo example, if i, o, and a v wee given in a set of specifications, Equations (7.) though (7.4) could be employed to find the β AC equied of the tansisto fo a satisfactoy design. All of these equations will be employed late in ou wok THE INPUT COUPLING CAPACITOR Figue 7.3 is a basic model fo detemining the lowe cutoff fequency, f i, fo the amplifie input coupling capacito, C l, but the fom of the equation is the same fo detemining C 2. Note that v s is the souce voltage, v in is the input voltage to the coupling capacito, i is the input esistance of the amplifie, and v is the voltage acoss i. R s + Vs v in  Figue 7.3: Equivalent cicuit fo coupling capacito Using phasos and applying the voltage divide ule we find that V V s R + whee ω is the adian fequency of v s. Equation (7.8) yields s i + jωc V i i Vs ( R ) 2 S + i + jω C ( R + ) + S i ω C At adian fequencies well above cutoff, Equation (7.9) educes to V V s i ( RS + i) i 2 (7.8) (7.9) (7.0) 74
5 Fom Equation (7.0), it is clea that the lowe cutoff fequency o the lowe 3dB fequency occus when ω i, we get V V V V Fom Equation (7.), we see that C s s 2 2 ω i ( RS + i) 2 i ( RS + i) ω 2π f i i. Denoting the lowe cutoff fequency by (7.). (7.2) 2πf + Note that C if i >> R S. See Equation (7.7) in Table I. ω ii 2πf i i As an example, if an amplifie has an input esistance i of kω and it is desied to capacitively couple a low impedance input signal v s to it so that the cutoff fequency, 2 i ωi 2 2 i C + ( R ) 2 S + i + C o, altenatively, ( RS i) ( RS + i) i ( RS i) f, is 200 Hz, we substitute into Equation (7.7) and find C 7.96(0) μ F. 2π (200)(000) 4π (7.3) THE LOAD LINE The load line is a valuable design tool, paticulaly in detemining the effect of lage signals on tansisto cicuit pefomance. In Expeiment 6, the emphasis was on the static load line with a slope /R C and thee was no capacitively coupled load. Equivalently, load was R L. When R L, the AC signal "sees" the dynamic load line descibed below. Figue 7.4 shows idealized tansisto chaacteistics with both static and dynamic of load lines. Fist, the static line is constucted in the usual way and the quiescent point established. Then, the dynamic line having a slope of /(R L R C ) is placed on the gaph with the new line also passing though the same Q point. 75
6 V CE (Sat) V CEQ' V CEQ V CED' V CED V CC Figue 7.4: Static and Dynamic Load Lines Fom the static line it is seen that v o v CE has a positive swing of S + (V CC  V CEQ ) befoe the tansisto is cutoff and a negative swing of S  (V CE (Sat)  V CEQ ) V CEQ befoe satuation. To get the maximum positive and negative voltage swings with a static line, the opeating point is fequently placed nea the cente, i.e., V CEQ 0.5 V CC, which is temed midpoint biasing. In this case, the total peaktopeak output voltage v opp (S +  S  ) 2 V CEQ V CC. On the othe hand, the dynamic line poduces cutoff at a lowe voltage and has a smalle positive swing of S + (V CED  V CEQ ) so that the maximum unclipped v opp 2 (V CED  V CEQ ). The positive swing S + fo the dynamic line may be inceased by establishing a new quiescent point called Q' at V CEQ' as shown in Figue 7.4. Obseve that the slopes of both dynamic lines ae the same, but the Q' point is moved to the left along the static line. This pocess can be done eithe analytically o by inspection of the gaph. Usually, Q' is moved to a new point whee a symmetic swing is established fo both positive and negative going signals. The esult is that v opp 2 V CEQ' whee V CEQ' [R L /(R C + 2 R L )] V CC. 76
7 7.3.4 Nonlinea Response and Distotion Fom the actual chaacteistic fo the 2N78A tansisto shown in Figue 7.5, it is seen that an actual tansisto has a nonideal family of cuves. Equal incements in I B ae not unifomly spaced on the gaph. Figue 7.5: A bief data sheet fo the 2N78A tansisto. Moeove, the patten of the I B cuves changes with both V CE and I C. Thus, a load line on the gaph with a Q point nea the cente pesents a diffeent effective β AC to pats of a sinewave input signal falling some distance on eithe side of Q. The esult is distotion in the output signal, i.e., it is no longe a pue sinewave. 77
8 7.3.5 Design Specifications Specifications may occu in one of seveal classes. At one exteme is the situation whee the amplifie is ove specified; i.e., too many vaiables ae constained. Conside the following elementay set as a case of ove specification: a vo 200, β AC 50, R C 2kΩ and π kω. Substitute into Equation (7.4) to obtain a Vo ( 50)(2kΩ) kω (7.4) The above is a tivial example of an invalid specification, but the designe must be alet to moe subtle conflicting specifications. At the othe exteme is a vey common situation whee the amplifie is unde specified, e.g., a vo 200 and β AC 0 ae the only constaints. Hee the designe has a infinite numbe of satisfactoy values fo R C and π fo Equation (7.4). Nevetheless, the values selected fo the fee paamete(s) must fist be consistent with good electonic engineeing pactices, and, beyond that, they must be the best possible fit within the context of the application as it is undestood by the enginee. A common vaiation of unde specification happens when one o moe paametes ae specified as "geate than o equal to". Since components have toleances and values that often change with age, it is good pactice to take advantage of the "inequality" specifications, but by "how much" involves judgment and knowledge of the application. Fo simplicity we do not conside cost hee, but be awae that in pactice it fequently is one of the most citical paametes. 78
9 7.3.6 A Design Example 6. Specifications. The desied design is a CE amplifie with the following specified paametes: R C 2 kω, V CEQ 3 V, a vo > 250, and f i 200 Hz. The load esistance is to also be the collecto esisto of the tansisto cicuit, i.e., C 2 is omitted and R L. Chaacteistics given fo the tansisto ae β AC β DC 50 and I Cmax 9 ma. Standad 5% esistos ae to be employed. See Appendix II in Section The Design Pocess. The equations needed fo ou wok ae numbeed sequentially and found in Table. Fom the above specification that R C 2 kω, which is a standad 5% esisto, and assuming that oc is vey lage, we get fom Eq. (7.3) that o 2 kω. Since V CEQ 3 V, then V CC >> 6 V. Abitaily, ty V CC 9 V. Then fom Equations (7.5) and (7.) we get and Fom Equation (7.4), I V V CC CEQ CQ RC π (26) β I CQ AC (26)(50) 3 3mA Ω. (7.5) (7.6) a Vo β AC R π C (50)(2) (7.7) which does not satisfy the specification. Thus, we must modify some of the pevious values to get a satisfactoy a vo. Fom the pevious wok, we obseve that a lage V CC will lead to a lage I C, leading to a smalle π and finally to a lage a vo. So, as a fist iteation in the design, we will incease V CC to 20 V. 7 9
10 Recomputing, fom Equation (7.5), and fom Equation (7.), and fom Equation (7.4), 20 V 3V I CQ 8.5 ma ; 2 kω (26)(50) 8.5 π 53 Ω ; (7.8) (7.9) a Vo (50)(2 kω).53 kω 654. (7.20) Since a vo is so much lage than the specification equies and since I CQ is close to the specification limit, a easonable appoach is to select V CC about midway between 9 V and 20 V, say at V CC 5 V. Tying this value and using the same set of equations, we find: I CQ 6 ma, which is significantly less than the maximum. π 27 Ω, which is acceptable since its value is unspecified, and a vo 46 V/V, which is well above the specified minimum. The design is completed by finding R B and C. Fom Equation (7.6), R B ( VCC 0.7) (5 V 0.7 V )(50) ( β DC ) 9 kω 20 kω, I 6 CQ (7.2) which is a standad 5% esisto. Note that 20kΩ >> i 0.27kΩ; theefoe, ou oiginal assumption of R B >> π is satisfied fo Equation (7.2). The change to R B 20 kω has negligible effect on seveal pevious paametes, e.g., I CQ 5.96 ma instead of 6 ma, but these ae of no pactical consequence fo the design. Finally, fom Equation (7.7), C ω 3.7 μ. 2π (200)(27) F i i (7.22) The next lagest standad sized capacito would be suitable. 7 0
11 7.4 Expeiment 7.4. Design Poblem Design Specifications Design an open cicuit (R L ) common emitte tansisto amplifie to meet the following chaacteistics: i kω, o < 2 kω, 60 a vo 240, f i 400 Hz, v opp 0 V whee v opp is the unclipped peaktopeak output voltage. Select an intege value fo supply voltage V CC and assume V CC has an accuacy of ±2 %. A 2N2222A tansisto with β DC β AC 75 ± 25 and oc > 25 kω is to be used. The base and/o collecto esistances may each use two standad ± 5% esistos combined in seies Initial Design As a laboatoy team, you ae to design a capacito coupled tansisto amplifie that satisfies the design specifications based on the nominal tansisto chaacteistics given in Section The design must include a cicuit diagam of the tansisto amplifie and values must be defined fo all components shown on the diagam. These may be shown diectly on the cicuit diagam o in a table. As a team, you must pesent the initial design to the instucto fo appoval pio to obtaining a 2N2222A tansisto Revised Design Obtain a 2N2222A tansisto and use the Tektonix 57 Cuve Tace to obtain its chaacteistics. Daw the load line fo you initial design on the tansisto chaacteistics and mak the design Q point. Fo this Q point, calculate the β DC, β AC, and oc fo the tansisto. If the tansisto meets the equiements, complete a evised design by modifying the base esistance and pesent it to the instucto. If the tansisto does not meet equiements, obtain a diffeent tansisto and epeat the above steps. 7 
12 Final Design You final design must opeate at the initial design Q point, i.e., the initial design V CEQ and I CQ. Once you have assembled you amplifie pe Section 7.4.4, tun on powe, allow it to stabilize at opeating tempeatue, and measue V CEQ and I CQ. If necessay, change the base esistance to obtain the coect Q point. Recod any design changes made Waning The tansisto is a small device with little themal capacity. Even an extemely bief ovevoltage o ovecuent fault will destoy the device o pemanently alte its popeties. Theefoe, you must not attempt to build a tansisto cicuit o alte any connections while the powe is on. Also, you must not apply any input signal voltage diectly to the base of the tansisto without a seies esisto o capacito Equipment List Tansisto cuve tace Motoola 2N2222A tansisto (50 ma, 60 V) with β DC β AC 75 ± 25 2 Capacitos values detemined by design calculations 4 Quate watt, 5% esistos (Values selected fom 0% list in Sect ) 0 40 V DC powe supply 2 0x Pobes Digital Oscilloscope HP 3320A Function Geneato 50Ω, 20dB signal attenuato Decade esisto box 3 Digital multimetes (DMMs) Expeimental Pocedue Geneal Guidelines (a) A digital oscilloscope, with its sensitive measuement capability, high input esistance, and low input capacitance, can be used to make accuate signal voltage measuements and should be used in pefeence to the DMM fo this pupose. To 7 2
13 accuately measue powe supply o bias voltages, the DMM is pefeable. (b) Since the amplifie that is to be designed is elatively high gain, the LOW output of the HP3320A function geneato and a 50Ω, 20dB signal attenuato must be used fo the signal souce. Since the attenuato output impedance is 50Ω, its value can often be neglected in gain measuements, but should be taken into account in measuing i. (c) Fequency can most conveniently be measued with the oscilloscope. Do not depend on the accuacy of the dial eading of the HP 3320A function geneato Detailed Laboatoy Steps (a) Pefom the initial and evised designs pe paagaphs and (b) Constuct you amplifie cicuit using o 2 standad esistos fo collecto esistance (R C ) and a kω shunt esisto and the decade box in seies fo the base esistance (R B ). See the cicuit shown in Figue 7.. Adjust the powe supply voltage to the design V CC value ± 2% befoe connecting the amplifie. (c) With v s 0, measue the bias voltages and cuents, e.g., V CEQ, I CQ, V BEQ, and I BQ. Refe to Expeiment 6 fo the best ways to measue I CQ and I BQ. If duing this step the measued values of V CEQ and I CQ fail to agee with the design values, adjust the decade box esistance to change the base esistance as needed to achieve the Q point values. Be sue to ecod any changes made fo this amplifie final design. (d) Replace the base esistance with o 2 standad esistos in seies and veify that the coect Q point is obtained. (e) With v s set at midfequency value (40 khz) and an output voltage v o 2 V RMS: () Detemine a vo using the digital oscilloscope. Note R L, and v in is measued just to the souce side of C. See Figue
14 (2) Place a decade box with esistance R DB 0 Ω between the Function Geneato and the coupling capacito (See Figue 7.) and measue v o with the scope. Incease R DB until v o dops to onehalf its oiginal value, which is the "half voltage method" fo detemining i. (The decade box should yield at least thee significant figues.) Now emove the decade box fom the cicuit and measue and ecod its value. (3) Simila to step (e.2) diectly above, measue o by placing a decade box in the R L position with R DB 999,999 Ω. Be sue C 2 C is lage enough so that its impedance has a negligible effect on the o measuement. Measue v o with the scope while adjusting R DB until v o dops to onehalf its oiginal value, yielding the measued o value. Recod o and etun the cicuit to R L. If any of the measued values fall outside the specification limits of paagaph 7.4.., you must note this and check with the instucto befoe poceeding any futhe. (f) Ranging fom about 2 octaves below the lowe cutoff up to 2 octaves above the uppe cutoff, take appopiate fequency esponse data with the oscilloscope. Fo this un, R L and R S 50 Ω. Note that v in should be measued and ecoded to be sue it stays essentially constant. Use the scope's fequency measuing featue to set accuate fequency values, but check them using the function geneato's fequency scale. Fequency esponse testing can best be accomplished as follows. Fist, with v in at a midfequency value, set v o to 5.66 V peaktopeak (2 V RMS) by obseving v o on the scope and adjusting the magnitude of v in. Next, incease and decease the fequency of v s in ode to detemine the lowe cutoff fequency (f l ) and the uppe cutoff fequency (f 2 ), espectively. Since the cutoff fequency is defined as the halfpowe point, then it follows that v o (5.66 V) 4 V peaktopeak at the espective cutoff fequencies. 74
15 To obtain adequate data points nea the two cutoff fequencies, ecod the peaktopeak values of v o and v in at the following fequencies without adjusting v s : f / 4 two octaves down fom the lowe cutoff fequency f / 2 one octave down fom the lowe cutoff fequency f lowe cutoff fequency 2 f one octave up fom the lowe cutoff fequency 4 f two octaves up fom the lowe cutoff fequency 0 f one decade up fom the lowe cutoff fequency f o /4 two octaves down fom the midange fequency f o midange fequency whee f o f f 2 4 f 0 two octaves up fom the midange fequency f 2 /0 one decade down fom the uppe cutoff fequency f 2 / 4 two octaves down fom the uppe cutoff fequency f 2 / 2 one octave down fom the uppe cutoff fequency f 2 uppe cutoff fequency 2 f 2 one octave up fom the uppe cutoff fequency 4 f 2 two octaves up fom the uppe cutoff fequency (g) Retun to a midfequency value, i.e., f o, and take data, v o vs. v in with the scope to detemine the lineaity of the amplifie fom v o 0.5 V RMS until obvious clipping occus. When clipping occus, instead of being a pue sinusoid, v o will have a significant flattening, eithe on the top due to cutoff o on the bottom due to satuation o both. Monito v in and v o with sepaate oscilloscope channels. Recod whee distotion stats by noting the value of v o whee the gain (a vo v o /v in ) begins to noticeably decease. Also, ecod the value of v o whee clipping occus. (h) Connect a load esisto R L 2R C using a coupling capacito C 2 C. Now ecod the value of v o whee clipping occus. This value should be noticeably smalle than that of Section (g). Also, daw the dynamic load line on the tansisto chaacteistics and compae measued and pedicted esults. 75
16 (i) Gaphically detemine a new Q' point that will lead to the lagest total possible output voltage swing with R L 2R C. Plot the dynamic load lines though Q and Q'. Note that it will be necessay to change the value of base esistance R B when implementing the new opeating point, Q'. Now epeat pat (h) fo a new dynamic quiescent point Q' Repot 7.5. Pesent the cuve tace chaacteistics fo you 2N2222A tansisto and show the constuction of you static load line. Be sue to label you Q point including I BQ, V CEQ, and I CQ. Show all the data points used to detemine β DC, β AC, and oc on the chaacteistics and also show you calculations fo β DC, β AC, and oc Pesent the initial and evised designs that wee appoved by the instucto. Pesent all petinent infomation, e.g., i, o, a vo, v opp (output voltage swing), f i, R B, R C, C, V CC, V CEQ, I CQ, I BQ, β DC, β AC, π, oc, etc., on the table povided Pesent a compaison showing you appoved amplifie initial, evised, and final design values and the actual measuements made duing test. Include all petinent infomation, e.g., i, o, a v, v opp (output voltage swing), f i, R B, R C, C, V CC, V CEQ, I CQ, I BQ, β DC, β AC, π, oc, etc., on the table povided Make a gaph showing the measued fequency esponse of you amplifie by plotting a vo v o / v in vesus fequency. Use a log scale fo fequency. Indicate the half powe points and the amplifie bandwidth Make a gaph fo the lineaity measuements made at midfequency by plotting v o vesus v in. Indicate on you gaph whee distotion and clipping each begin Show the constuction of you dynamic load lines with the Q & Q' point(s) included as elated to Sect (h) and (i) and calculate v opp fo each case. 76
17 7.5.7 The v opp is descibed on page 76 and measuements ae taken in expeiment steps (g), (h), and (i) of Section Make a table pesenting the calculated and measued data fo v opp () without R L and (2) with R L using both the Q and Q' opeating points Deive Equation (7.4) in Table I on page 73 fom basic pinciples. 7.6 Appendices 7.6. Appendix I  Standad Amplifie Models Thee ae fou standad amplifie models as shown in the table below. Even though the tansisto is a cuent contolled device, we will make use of the Voltage Amplifie fo this expeiment since it is the most often used model. 77
18 7.6.2 Appendix II  Resisto Value Multiplies These values all apply to ± 5% toleance esistos. Resistos with ± 0% toleance ae only available in values maked by a *. The multiplies ae:.0*.5* 2.2 * 3.3* 4.7* 6.8* *.8* 2.7* 3.9* 5.6* 8.2* Refeences. Seda, Adel S. and Smith, Kenneth C., Micoelectonic Cicuits, 5 th Edition, Oxfod Univesity Pess, New Yok, Boylestead, Robet and L. Nashelsby, Electonic Devices and Cicuit Theoy (4 th ed.), PenticeHall, Englewood Cliffs NJ, Chilian, Paul M., Analysis and Design of Integated Electonic Cicuits, Hape and Row, Cambidge MA, Ginich, Victo H., and H. G. Jackson, Intoduction to Integated Cicuits, McGawHill, New Yok NY, Millman, Jacob, Micoelectonics  Digital and Analog Cicuits and Systems, McGawHill, New Yok NY, Mitchell, J., F. H., and F. H. Mitchell, Intoduction to Electonics Design, PenticeHall, Englewood Cliffs NJ,
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